Scribd
Upload
19 views

Noise

Uploaded by

22119228
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
19 views

Noise

Uploaded by

22119228
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 8

noise

module noise_add (
input [7:0] i_data,
input [4:0] i_noise, // the noise is emulated using
output [7:0] o_data
);

reg [6:0] noise;

wire [2:0] error_at_bit;


assign error_at_bit = i_noise[2:0]; // only for debug

always @(*) begin


case(i_noise[2:0])
3'd1: noise = {i_noise[3], 6'b00_0001}; // 1bit or 2bit error
3'd2: noise = {i_noise[3], 6'b00_0010};
3'd3: noise = {i_noise[3], 6'b00_0100};
3'd4: noise = {i_noise[3], 6'b00_1000};
3'd5: noise = {i_noise[3], 6'b01_0000};
3'd6: noise = {i_noise[3], 6'b10_0000};
3'd7: noise = {6'b100_000, i_noise[3]};
default: noise = {i_noise[3], 6'b00_0000}; // no error or 1 bit error at MSB (bit
6)
endcase
end

assign o_data = i_data ^ {i_noise[4], noise};


endmodule
decoder
module hamming74_dec(
input [6:0] i_data,
input i_parity,
output [6:0] o_syndrome, // optional -> used to display the 7Segment Display
output [3:0] o_data,
output o_1bit_error,
output o_2bit_error,
output o_parity_error
);

// Intermediary logic
reg p1, p2, p4;
reg [6:0] syndrome; // one hot value for the bit to be corrected
wire [6:0] data_decoded;
wire overall_parity;

// Create the logic for the p1, p2, p4 signals (the syndrome)
always @(*) begin
p1 = i_data[0] ^ i_data[2] ^ i_data[4] ^ i_data[6];
p2 = i_data[1] ^ i_data[2] ^ i_data[5] ^ i_data[6];
p4 = i_data[3] ^ i_data[4] ^ i_data[5] ^ i_data[6];
end

// Create the 3-to-8 decoder


always @(*) begin
case({p4,p2,p1})
3'd1: syndrome = 7'b0000_001;
3'd2: syndrome = 7'b0000_010;
3'd3: syndrome = 7'b0000_100;
3'd4: syndrome = 7'b0001_000;
3'd5: syndrome = 7'b0010_000;
3'd6: syndrome = 7'b0100_000;
3'd7: syndrome = 7'b1000_000;
default : syndrome = 7'b0;
endcase
end

assign data_decoded = syndrome ^ i_data;


assign o_syndrome = syndrome; // used only for debug

// Create the overall_parity and the output errors


assign overall_parity = ^{i_parity, i_data};
/*
Syndrome Overall Parity Error Type Notes
0 0 No Error
/=0 1 Single Error Correctable. Syndrome holds incorrect bit position.
/=0 0 Double Error Not correctable.
0 1 Parity Error Overall parity, parity is in error and can be corrected.
*/

assign o_1bit_error = ({p4,p2,p1} != 3'b0) & overall_parity;


assign o_2bit_error = ({p4,p2,p1} != 3'b0) & ~overall_parity;
assign o_parity_error = ({p4,p2,p1} == 3'b0) & overall_parity;

// Rearrange the data bits for the output


// Input: d7 d6 d5 p4 d3 p2 p1
// Output: d3 d2 d1 d0
assign o_data = {data_decoded[6:4], data_decoded[2]};

endmodule

encoder

module hamming74_enc(
input [3:0] i_data,
output [6:0] o_hamming_code,
output o_parity // optional
);

reg p1, p2, p4;

always @(*) begin


p1 = i_data[0] ^ i_data[1] ^ i_data[3];
p2 = i_data[0] ^ i_data[2] ^ i_data[3];
p4 = i_data[1] ^ i_data[2] ^ i_data[3];
end

// Rearrange the data bits for the output


// Input: d3 d2 d1 d0
// Output: d7 d6 d5 p4 d3 p2 p1
assign o_hamming_code = {i_data[3:1],p4,i_data[0],p2,p1};

// Create the optional parity bit


assign o_parity = ^o_hamming_code;

endmodule

prio
module prio_enc_8to3
(input [7:0] d,
output reg [2:0] q,
output reg v
);

always @(*) begin


case (1) // checks if a signal is set
d[7]: begin q = 3'd7; v = 1'b1; end
d[6]: begin q = 3'd6; v = 1'b1; end
d[5]: begin q = 3'd5; v = 1'b1; end
d[4]: begin q = 3'd4; v = 1'b1; end
d[3]: begin q = 3'd3; v = 1'b1; end
d[2]: begin q = 3'd2; v = 1'b1; end
d[1]: begin q = 3'd1; v = 1'b1; end
d[0]: begin q = 3'd0; v = 1'b1; end
default: begin q = 3'd0; v = 1'b0; end
endcase
end

endmodule

led
module hex_7seg_decoder
// Parameters section
#( parameter COMMON_ANODE_CATHODE = 0) // 0 for common Anode / 1 for common
cathode
// Ports section
(
input [3:0]in,
output o_a,
output o_b,
output o_c,
output o_d,
output o_e,
output o_f,
output o_g
//output dot // optional - NOT used on DE1-SoC board
);

// Internal logic
reg a,b,c,d,e,f,g;

// Use concatenation to pass values to all outputs in the same time


always @(*) begin
case (in)
4'd0 : {a,b,c,d,e,f,g} = 7'b1111110; // common cathode value
4'd1 : {a,b,c,d,e,f,g} = 7'b0110000;
4'd2 : {a,b,c,d,e,f,g} = 7'b1101101;
4'd3 : {a,b,c,d,e,f,g} = 7'b1111001;
4'd4 : {a,b,c,d,e,f,g} = 7'b0110011;
4'd5 : {a,b,c,d,e,f,g} = 7'b1011011;
4'd6 : {a,b,c,d,e,f,g} = 7'b1011111;
4'd7 : {a,b,c,d,e,f,g} = 7'b1110000;
4'd8 : {a,b,c,d,e,f,g} = 7'b1111111;
4'd9 : {a,b,c,d,e,f,g} = 7'b1111011;
4'd10: {a,b,c,d,e,f,g} = 7'b1110111;
4'd11: {a,b,c,d,e,f,g} = 7'b0011111;
4'd12: {a,b,c,d,e,f,g} = 7'b1001110;
4'd13: {a,b,c,d,e,f,g} = 7'b0111101;
4'd14: {a,b,c,d,e,f,g} = 7'b1001111;
4'd15: {a,b,c,d,e,f,g} = 7'b1000111;
default : {a,b,c,d,e,f,g} = 7'b1111110; // best practice
endcase
end

assign {o_a, o_b, o_c, o_d, o_e, o_f, o_g} = COMMON_ANODE_CATHODE ?


{a,b,c,d,e,f,g} : ~{a,b,c,d,e,f,g};

// If you want the dot open assign 0 to it otherwise 1


//assign dot = 1'b1;
endmodule

You might also like