BEG4204: Microprocessor Systems II

Contact Hours: 42
Credit Hours: 3
Prerequisites: BEG4106 Microprocessor Systems I

Purpose:
The aim of this course is to enable the learners to develop skills in microprocessor
programming and application;

Expected Learning Outcomes:

By the end of this course, the learner should be able to;
1. Describe the internal structure of a microprocessor
2. Design systems requiring microprocessor controllers
3. Describe signals and physical memory organization

Course Content:
Architecture of a 16-bit microprocessor: internal organization of 8086, signal descriptions,
physical memory organization, BIU, EU, minimum mode 8086 system and timings, maximum
mode 8086 system and timing.

Assembly Language Programming: addressing modes, instruction set, assembler directives and
operators, data movement instructions, arithmetic and logic instructions, program control
instructions, recursive procedures. Special architectural features and related programming:
stack structure, interrupts and interrupt service routine, interrupt programming, macros, timings
and delays. Basic peripherals and their interfacing: memory interfacing, interfacing I/O ports,
programmable peripheral interface (8255), interfacing A/D and D/A converters. Special
purpose programmable peripheral devices and their interfacing: Programmable Interval Timer
(8253/8254), Programmable Interrupt Controller (8259), Keyboard/Display Controller (8279),
Programmable Communication Interface (8251), DMA Controller
(8237/8257).Microprocessor Applications: Interfacing scanned multiplexed displays and
Liquid crystal displays, Interfacing matrix keyboard, Stepper motor interfacing, Case studies
of microprocessor based systems, Standards for bus architecture and ports. Bus structure, and
timing and activities of bus cycles of 8086 microprocessor

Teaching Methodology:
2 hour lecture and 1 hour tutorial per week and at least three 3-hour laboratory session per
semester organized on a rotational basis.

Instructional Materials/Equipment:
1. Digital Electronics Laboratory
2. Overhead projector

Course Assessment:
Regular Examination at end of Semester: 70 %, Continuous Assessment: 30% where 10 %
shall be continuous assessment tests, 5 % shall be assignments, and 15 % shall be labs. The
learners must complete and pass all the labs before they can be allowed to proceed to the next
class.

Core Text Books:

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 1. Crisp J. (2004), Introduction to Microprocessors and Microcontrollers, Amsterdam,
Boston, Elsevier/Newnes, 2nd Ed.
2. Tocci R.J, &Ambrosio F.J., (2002), Microprocessors and Microcomputers: hardware
and software, Prentice Hall, 6th Ed.

Recommended Text book(s) for further reading:

1. Ramesh S.G.,(2002), Microprocessor Architecture, Programming, and Application
with 8085, Prentice Hall, 5th Ed
2. Khambata, Adi J, (1986), Microprocessors/Microcomputers: architecture, software and
Systems, Wile, New York.

Instructor: Eng. Fredrick M. Mulei

Email: [email protected]
Phone: 0722 785 035

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Architecture of a 16-bit microprocessor: internal organization of 8086, signal descriptions,
physical memory organization, BIU, EU, minimum mode 8086 system and timings, maximum
mode 8086 system and timing.

Assembly Language Programming

Assembly language is a low-level programming language that corresponds closely to the
architecture of a computer's central processing unit (CPU). It is specific to the type of processor
and provides a human-readable representation of the machine code instructions that the CPU
executes. Microprocessors, being the central component of a computer system, are often
programmed using assembly language to perform tasks at a very low level.
Here are some key aspects of assembly language programming in the context of
microprocessors:
1. Registers: Assembly language instructions often involve manipulating data stored in
registers. Registers are small, fast storage locations within the CPU. Assembly language
instructions can perform operations directly on data in registers, making it a low-level
and efficient programming approach.
2. Instruction Set Architecture (ISA): Each microprocessor has its own instruction set
architecture, which is a set of instructions that the CPU can execute. Assembly language
programs are written using these instructions. Common instructions include arithmetic
operations (add, subtract, multiply), logic operations (AND, OR, XOR), memory
operations (load, store), and control flow operations (jump, branch).
3. Memory Access: Assembly language instructions allow the programmer to read from
and write to memory locations. This involves specifying memory addresses and data
movement instructions. The ability to work with memory is crucial for performing tasks
such as storing and retrieving data.
4. Labels and Branching: Assembly language includes features for controlling the flow
of the program. Labels are used to mark locations in the code, and branching
instructions (e.g., jumps and conditional branches) enable the program to transfer
control to different parts of the code based on certain conditions.
5. Stack Operations: Many microprocessors use a stack to manage subroutine calls, local
variables, and return addresses. Assembly language instructions often include stack-
related operations, such as push and pop, to manipulate the stack.
6. Direct Hardware Manipulation: Assembly language allows direct manipulation of
hardware resources. This includes configuring hardware settings, interacting with
input/output ports, and managing interrupts.
7. Assembler: An assembler is a program that translates assembly language code into
machine code. It converts human-readable mnemonics and symbols into the binary
instructions that the microprocessor understands.
Here's a simple example in x86 assembly language to give you a sense of how it looks:

section .data
msg db 'Hello, Assembly!', 0

section .text
global _start

_start:
; write the message to stdout
mov eax, 4 ; syscall: write
mov ebx, 1 ; file descriptor: stdout

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 mov ecx, msg ; pointer to the message
mov edx, 16 ; length of the message
int 0x80 ; interrupt to invoke the kernel

; exit the program

mov eax, 1 ; syscall: exit
xor ebx, ebx ; exit code 0
int 0x80 ; interrupt to invoke the kernel

This example, written for the x86 architecture, uses Linux system calls to write a message to
the standard output and then exits the program. Note that assembly language syntax and
instructions can vary between different processor architectures.

1. Addressing Modes: Addressing modes define how the operand of an instruction is

specified. Common addressing modes include:
 Immediate Mode: Operand is a constant value.
 Register Mode: Operand is in a processor register.
 Direct Mode: Operand is the address of the data.
 Indirect Mode: Operand is the address of a memory location that contains the
actual address of the data.
 Indexed Mode: Operand is obtained by adding a constant value to the contents
of a register.

Addressing modes in a microprocessor refer to the various ways in which the CPU can access
operands in memory during the execution of instructions. Different addressing modes provide
flexibility in programming and allow efficient utilization of memory and registers. Here are
some common addressing modes found in microprocessors:

Immediate Addressing Mode:

Operand is specified directly in the instruction.

Example: MOV A, #5 (Move immediate value 5 to register A).
Register Addressing Mode:

Operand is specified in a register.

Example: ADD A, B (Add the content of register B to register A).
Direct Addressing Mode:

Operand is the actual memory address where data is stored.

Example: MOV A, 2000H (Move the content of memory location 2000H to register A).
Indirect Addressing Mode:

Operand is not the actual data but contains the address of the data.
Example: MOV A, [BX] (Move the content of the memory location whose address is in register
BX to register A).
Register Indirect Addressing Mode:

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Similar to indirect addressing, but the address is in a register.
Example: MOV A, [BX] (Move the content of the memory location whose address is in register
BX to register A).
Indexed Addressing Mode:

An index is added to a base register to get the effective address.

Example: MOV A, [BX + SI] (Move the content of the memory location whose address is the
sum of BX and SI registers to register A).
Relative Addressing Mode:

Address is specified relative to the current program counter (PC).

Example: JMP 100H (Jump to the instruction at address 100H).
Base-Register Addressing Mode:

Similar to register addressing, but an offset is added to a base register.

Example: MOV A, 100H[BX] (Move the content of the memory location whose address is
100H plus the content of register BX to register A).

2. Instruction Set: An instruction set is the collection of instructions that a particular

processor understands and can execute. It includes operations such as data movement,
arithmetic and logic operations, and control flow instructions.
An instruction set in the context of a microprocessor refers to the collection of instructions that
the CPU can execute. These instructions define the operations that the processor can perform,
and they are encoded as binary patterns or opcodes. Here are some key points regarding
instruction sets in microprocessors:

Instruction Types:

Data Transfer Instructions: Move data between registers, memory, and other devices.
Arithmetic Instructions: Perform arithmetic operations like addition, subtraction,
multiplication, and division.
Logical Instructions: Perform logical operations like AND, OR, XOR, and NOT.
Control Transfer Instructions: Change the sequence of execution by altering the program
counter (e.g., branch or jump instructions).
I/O Instructions: Communicate with input/output devices.

Instruction Format:

Instructions are typically divided into fields, including the opcode (operation code), source and
destination operands, addressing mode, etc.
The format varies between different instructions and architectures.
Addressing Modes:

As mentioned earlier, addressing modes define how operands are specified for instructions.
The instruction set includes a variety of addressing modes to provide flexibility in accessing
data.

Registers:

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The instruction set defines the available registers and their use.
Registers are used for temporary storage and quick access, and different instructions may use
different registers.

Flags and Status Bits:

Many instruction sets include flags or status bits to indicate conditions such as zero result, carry
out, overflow, etc.
Conditional branch instructions use these flags to determine the flow of control.

Privileged Instructions:

Some instructions may be privileged and can only be executed in a privileged mode or
supervisor mode.
Privileged instructions often include operations that could impact system integrity or security.
Vector Instructions:

Some modern instruction sets include vector instructions for parallel processing, allowing the
simultaneous execution of multiple data elements.

5trInstruction Pipelining:

In pipelined architectures, instructions are broken down into stages, and each stage is executed
in a separate clock cycle.
Instructions may overlap in execution to improve throughput.
CISC vs. RISC:

Complex Instruction Set Computing (CISC) architectures have a large set of complex
instructions.
Reduced Instruction Set Computing (RISC) architectures have a smaller set of simple
instructions, aiming for faster execution.
Assembly Language:

Assembly language instructions correspond directly to the machine code instructions of the
processor.
Programmers write code in assembly language, which is then translated into machine code by
an assembler.

3. Assembler Directives and Operators:

 Assembler Directives: These are instructions to the assembler itself, not the
CPU. They provide information about the program structure, memory
allocation, and other details.
 Operators: These are symbols that represent basic operations in assembly
language, such as addition, subtraction, multiplication, and division.
4. Data Movement Instructions: These instructions involve transferring data between
registers, memory, and other locations. Examples include LOAD, STORE, MOVE, etc.
5. Arithmetic and Logic Instructions:
 Arithmetic Instructions: Perform basic arithmetic operations like addition,
subtraction, multiplication, and division.

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  Logic Instructions: Execute logical operations such as AND, OR, XOR, etc.
6. Program Control Instructions: These instructions manage the flow of a program.
Common examples include conditional branches, unconditional jumps, subroutine
calls, and returns.
7. Recursive Procedures: Recursive procedures involve a function or subroutine calling
itself. This is a programming technique where a problem is solved by solving smaller
instances of the same problem.

Microprocessor Addressing modes

An instruction consists of an opcode and an operand. The operand may reside in the
accumulator, or in a general purpose register or in a memory location. The manner in which an
operand is specified (or referred to) in an instruction is called addressing mode.

The following are the different addressing modes of 8086:

 Register operand addressing.
 Immediate operand addressing.
 Memory operand addressing.

The different memory addressing modes are:

 Direct Addressing
 Register Indirect Addressing
 Based Addressing
 Indexed Addressing
 Based Indexed Addressing and
 Based Indexed with displacement.
Physical address (for the operand) is the address from which either a read or write operation is
initiated. The following shows the manner of generation of physical address.

Physical address = Segment base : Effective address

= Segment base : Base + Index + Displacement

i.e., effective address, for its generation, can have as many as three elements: Base, Index and
Displacement. Thus the effective address is generated from the following:

Effective address = Base + Index + Displacement

The segment registers can be CS, SS, DS or ES. Base can be BX or PB. Index can be SI or DI
and the Displacement can either be 8-bit or 16-bit. It should be noted that not all the three
elements viz., base, index or displacement are always used for effective address calculations.

(a) Register Addressing Mode.

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In this mode, either an 8-bit or a 16-bit general purpose register contains the operand.
Some examples are:
MOV AX, BX
MOV CX, DX
ADD AL, DH
ADD DX, CX
The content of BX register is moved to AX register in the first example, while
in the third example, content of DH is added to the content of AL.
Here, source and destination of data are CPU registers.

(b) Immediate Addressing Mode.

In this mode, the operand is contained in the instruction itself, i.e., the operand forms
a part of the instruction itself. The operand can be either 8-bit or 16-bit in length.
Some examples are:
MOV AL, 83 H
ADD AX, 1284 H
In the first example, 83 H is moved to AL register while in the second example,
1284 H is added to the contents of AX register. Here, source of data is within the
instruction.

In a way it is similar to ‘Immediate Addressing Mode’. In Immediate Addressing Mode,

data follows the instruction opcode, while in this case an effective address follows the
same. Thus in this case:
PA = Segment base : Direct address.
By default, the segment base register is DS. Thus,
PA = DS : EA
But if a segment override prefix (SEG) is used in the instruction, then any one of the
four segment registers can be referenced. Hence, in general,

It means, “move the contents of the memory location, which is labelled as ALPHA
in the current data segment, into register CX”.
Thus, if DS = 0300 H, and value assigned to ALPHA is 3216 H, then
PA = 03000 H + 3216 H
= 06216 H
Thus, data contained in address locations 06217 H and 06216 H will be stored in CH
and CL registers respectively.
MOV [0404 H], CX would move the contents of CL to offset address 0404 H (relative
to data segment register DS) and CH to 0405 H. Here, memory address is supplied within
the instruction.

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c) Register Indirect Addressing Mode.

In a way, this mode of addressing is similar to direct addressing mode in the sense that
content of DS is combined with the effective address to get the physical address.
But the difference lies in the manner in which the offset is specified. In direct
addressing mode EA is constant while in this mode EA is a variable.
EA can reside in either base register (BX or BP) or index register (SI or DI). The
default segment register is DS, but again by using a segment override prefix (SEG), any
of the four segment registers can be referenced.
Thus, PA can be computed as:

An instruction of this mode of addressing is:

MOV CX, [SI]

Execution of this instruction entails moving the content of the memory location
having its offset value in SI from the beginning of the current data segment to the CX
register.
If DS = 0300 H and SI = 3216 H, then PA becomes
PA = 03000 H + 3216 H = 06216 H.
Thus data contained in 06217 H and 06216 H will be placed in CH and CL registers
respectively. Here, memory address is supplied in an index or pointer register.

d) Based Addressing Mode.

The physical address in this case is generated as follows:

PA = Segment base: Base + Displacement

An example of this mode of addressing is MOV [BX] + ALPHA, AH

Here, ALPHA denotes displacement (which can be 8 or 16-bits) and BX the base
register. Together, they give EA of the destination operand.

If DS = 3000 H, BX = 1234 H and displacement (16-bit) = 0012 H,

Then, PA = 03000 H + 1234 H + 0012 H = 04246 H

Thus the content of AH (source operand) is placed in the physical address 04246 H
(destination operand memory location).

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In this mode also, the default register i.e., DS can be changed by a segment override
prefix (SEG). Also for accessing data from the stack segment of the memory, BP is to be
used instead of BX.
Here, the memory address is the sum of BX or BP base registers plus an 8 or
16-bit displacement specified in the instruction.

e) Indexed Addressing Mode.

The physical address in this case is generated as follows:

PA = Segment Base : Index + Displacement

An example of this mode of addressing is: MOV [SI] + ALPHA, AH where, ALPHA represents
displacement. Assuming, DS = 3000 H, SI = 1234 H and ALPHA (displacement) = 0012 H.
Thus, PA = 03000 H + 1234 H + 0012 H = 04246 H. Thus, the data value residing in source
operand AH will be moved to the physical address location 04246 H. Here, memory address is
the sum of the index register plus an 8 or 16-bit displacement specified in the instruction.

f) Based Indexed Addressing mode.

The physical address is generated in this case in the following manner:

PA = Segment Base : Base + Index

Here, BX and BP registers are used for data and stack segments respectively.
An example of this mode of addressing is as follows:

MOV AL, [BX] [SI]

If DS = 3000 H, BX = 1000 H and SI = 1234 H, then
PA = 03000 H + 1000 H + 1234 H = 05234 H
On executing this instruction, the value stored in memory location 05234 H will be
stored in AL.
Here, memory address is the sum of an index register and a base register

g) Based Indexed with displacement Addressing Mode.

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It is a combination of based addressing mode and indexed addressing mode along with an 8 or
16-bit displacement. The physical address is generated in the following manner:

PA = Segment base : Base + Index + Displacement

An example of this mode of addressing is as follows:

MOV AL, [BX] [SI] + ALPHA

Thus the offset or effective address can be calculated from the contents of base and
index registers and the fixed displacement as represented by ALPHA.

Assuming: DS = 3000 H, BX = 1000 H, SI = 1234 H and ALPHA (displacement) = 0012 H.

Thus, PA = 03000 H + 1000 H + 1234 H + 0012 H = 05246 H.

On executing this instruction, the value stored in memory location 05246 H (source

operand) will be stored in AL. Here, memory address is the sum of an index register, a
base register and an 8 or 16-bit displacement within the instruction.

Instruction Set of 8086 microprocessor

An instruction set in a microprocessor is a collection of commands or operations that the

processor can execute. These commands dictate the actions the processor should perform, such
as arithmetic operations, data movement, control flow operations, and so on. Here are some
examples of instructions commonly found in microprocessor instruction sets:
1. Arithmetic Instructions:
 ADD (Addition)
 SUB (Subtraction)
 MUL (Multiplication)
 DIV (Division)
 INC (Increment)
 DEC (Decrement)
2. Logical Instructions:
 AND (Bitwise AND)
 OR (Bitwise OR)
 XOR (Bitwise XOR)
 NOT (Bitwise NOT)
 SHIFT (Bitwise Shift)
3. Data Transfer Instructions:
 MOV (Move)
 LOAD (Load from memory)

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  STORE (Store to memory)
4. Control Transfer Instructions:
 JMP (Jump)
 CALL (Call subroutine)
 RET (Return from subroutine)
 JZ, JNZ, JC, JNC, JG, JGE, JL, JLE (Conditional Jump Instructions)
 CMP (Compare)
5. Stack Instructions:
 PUSH (Push onto stack)
 POP (Pop from stack)
6. Input/Output Instructions:
 IN (Input from port)
 OUT (Output to port)
7. Control Instructions:
 NOP (No operation)
 HALT (Halt execution)
 RESET (Reset the processor)

Note:
With the first MOV instruction, data from the source memory is to be moved into an internal
register-normally accumulator.
The second MOV instruction places the accumulator content into the destination memory.

The 8086 microprocessor has a powerful set of registers. The register organization of the 8086
microprocessor is also known as the programmer’s model. These different internal registers are
accessed by the programmers programming the 8086 microprocessor. All the registers are 16-
bit and are grouped into several categories as follows,

 General-purpose registers,
 Segment registers,
 Special purpose registers, and
 Flag register.
Let us see briefly each register in the 8086 microprocessor.

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General Purpose Registers :
The 8086 microprocessor has 8 registers each of 8 bits, AH, AL, BH, BL, CH, CL, DH, DL as
shown below. Each register can store 8 bits. To store more than 8 bits, we have to use two
registers in pairs. There are 4 register pairs AX, BX, CX, DX. Each register pair can store a
maximum of 16-bit data. General-purpose registers are used for holding variables or data. They
can be also used as counters or as temporary storage for intermediate results during any
operation.

These registers perform the following functions,

 Accumulator (AX) Register → When the microprocessor performs any arithmetic or

logical operations, the accumulator provides one of the operands and it also holds the
result of the operation. The user can access this register. It is denoted by A. The
accumulator register AX can collect a total of 16-bit data i.e., 8-bit of data in register AL
(lower byte of AX) and 8-bit of data in register AH (higher byte of AX).
 Base (BX) Register → For reading data from memory or writing data into memory, 8086
microprocessor has to select one memory location, 16-bit effective address of this memory
location can be stored in register BX.
 Counter (CX) Register → In rotate and shift instructions, register CL is used as 8 bit
counter i.e., it used to store 8-bit count. In some instructions like REP (repeat), Loop,
register CX is used as 16-bit implicit counter.
 Data (DX) Register → In multiplication and division instruction, if data or result is of 32-
bits, then register DX is used to store 16 MSB, and register AX is used to store 16 LSB
i.e., register DX is concatenated with register AX to store 32-bit data or result. In 8086,
the input port address is 16-bit and it is stored in register DX. The name of register DX is
given along with IN and OUT instructions as shown in the below example.
 MOV DL, 0001H (port address)
 IN AL, DX
Segment Registers :

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The 8086 microprocessor has a 20-bit wide physical address to access 1MB memory location.
But the registers of the 8086 microprocessor that holds the logical address are only 16-bits
wide. Thus 8086 microprocessor implements memory segmentation for 1MB physical memory
where the memory is divided into sections or segments as shown below. So that each memory
location in the segment can be accessed by the 16-bit logical address.

The 8086 microprocessor allows only four segments to work at a time and are provided by the
bus interface unit (BIU) of the 8086 microprocessor. The four-segment registers and their
functions are,

 Data Segment Register (DS) → It is used to point to the base address of the data segment.
 Code Segment Register (CS) → It is used to point to the base address of the code segment.
 Stack Segment Register (SS) → This register is used to store the base address of the stack
memory segment.
 Extra Segment Register (ES) → This register is used to store the base address of the extra
memory segment.
Special Purpose Registers :
Special purpose registers are pointer and index registers, instruction pointer, and program
counter. These are 16-bit registers used by the CPU for specific purposes. Since they are 16-

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bit, one or more registers are associated with each segment register in order to generate a 20-
bit physical address on the address bus. The special-purpose registers are used as memory
pointers and are belongs to the pointer and index group shown below.

Stack Pointer (SP) :

It is used to hold the address of the stack top. Stack top is the uppermost filled memory location
in stack memory. There is no access to these register directly, the modifications are done
depending on the contents of the stack.

Base Pointer (BP) :

The use of BP as a pointer to a memory location is similar to the use of SI and DI registers. BP
register acts as a memory pointer to the stack segment register. The BP register is mainly used
to access any location directly in the stack.

Source Index (SI) and Destination Index (DI) :

SI and DI act as memory pointers relative to segment register DS. The microprocessor will take
the effective address of the data from SI and store it in DI.

Instruction Pointer (IP) :

The IP gives the offset address of the next instruction to be executed i.e., IP stores the address
of the next instruction to be fetched from the code segment. When reset is activated, the
instruction pointer is set to the address of the first instruction to be fetched.

Flag Register :
The flag register of 8086 is a flip-flop. It is 16-bit wide with a collection of 1-bit values that
indicates the current state of the execution of arithmetic or logical instruction in the processor.
Out of 16 bits, 9 bits are used in the 8086 as shown below.

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The nine active flags are divided into two groups namely status flags and control flags. The
status flags include, carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag
that indicates the status of the instruction. The control flags used to control certain operation
of the processor, it includes the interrupt flag, direction flag, and trap flag.

Default and Specified Segment Registers :

For selecting any memory location, the microprocessor will transfer a 20-bit physical address.
For generating a physical address microprocessor will add the base address and effective
address. The effective address will be present in memory pointers. For each memory pointer,
there are fixed segment registers for the base address. This, fixed segment register of memory
pointers is called default segment registers.

Apart from the actual segment register microprocessor can take the base address from other
segment registers. But, the programmer has to specify the name of these registers in the
instruction. Hence these registers are called specified segment registers. The default and
specified segment registers for each memory pointer are tabulated as shown below.

Memory Pointer (logical Default Specified

Operation of Microprocessor
address) Segment Segment

Microprocessor reading instruction

IP CS None
from memory

Microprocessor storing stack of data

SP, BP SS None
(PUSH/POP)

Source of string data SI DS CS, ES, SS

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 Destination of string data DI ES None

General data access Effective address DS CS, ES, SS

BX used as a pointer Effective address DS CS, ES, SS

BP used as a pointer Effective address SS CS, ES, DS

Example

1. Explain the following two examples:

(a) MOV CX, CS
(b) MOV AX, [ALPHA]

Ans. (a) MOV CX, CS: It stands for, “move the contents of CS into CX”. If CS contains
1234 H, then on execution of this instruction, content of CX would become 1234 H
i.e., content of CH = 12 H and Content CL = 34 H.
(b) MOV AX, [ALPHA]: Let, data segment register DS contains 0300 H and ALPHA
corresponds to a displacement of 1234 H. Then the instruction stands for, “move the
content of the memory location offset by 1234 H from the starting location 0300 H
of the current data segment into accumulator AX”. The physical address is
PA = 03000 H + 1234 H = 04234 H
Thus execution of the instruction results in content of memory location 04234 H
is moved to AL and content of memory location 04235 H is moved to AH.

3. Write an ALP (assembly language programming) for addition of two 8-bit data
BB H and 11 H.
Ans. 0200 MOV AL, BB H : 8-bit data BB H into AL
0202 MOV CL, 11 H : 8-bit data 11 H into CL
0204 ADD AL, CL : Contents of AL and CL added
0206 HLT : Stop.
Comment : Result in AL = CC H.
4. Write an ALP for addition of two 16-bit data BB11 H and 1122 H.
Ans. 0200 MOV AX, BB11 H : 16-bit data BB11 H into AX
0203 MOV CX, 1122 H : 16-bit data 1122 H into CX
0206 ADD AX, CX : Contents of AX and CX added
0208 HLT : Stop

Comment : Result in AX = CC33 H.

5. Write an ALP for addition of two 8-bit data BB H and 11 H. The first data has
an offset address of 0304 H and displacement.
Ans. 0200 MOV BX, 0304 H : Offset address put in BX
0203 MOV AL, 11 H : 8-bit data 11H into AL
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0205 ADD AL, [BX + 07] : 8-bit data from offset + displacement added with AL
0207 HLT : Stop.
Comment : Result in AL = CC H.

Data Transfer and memory interfacing

Memory interfacing can involve various types of memory devices, including RAM, ROM, and
external memory peripherals like cache memory and memory-mapped I/O. Techniques such as
direct memory access (DMA) and memory-mapped I/O are also used for efficient data transfer.

The data transfer schemes are broadly classified into two categories. These are
 Programmed data transfer
 Direct Memory Access (DMA) transfer.

Memory and I/O Interfacing

Several memory chips and I/O devices are connected to a microprocessor.

The following figure shows a schematic diagram to interface memory chips and I/O devices to
a microprocessor.

Memory Interfacing

When we are executing any instruction, the address of memory location or an I/O device is sent
out by the microprocessor. The corresponding memory chip or I/O device is selected by a
decoding circuit.

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Memory requires some signals to read from and write to registers and microprocessor transmits
some signals for reading or writing data.

The interfacing process includes matching the memory requirements with the microprocessor
signals. Therefore, the interfacing circuit should be designed in such a way that it matches the
memory signal requirements with the microprocessor's signals.

I/O interfacing

As we know, keyboard and displays are used as communication channel with outside world.
Therefore, it is necessary that we interface keyboard and displays with the microprocessor.
This is called I/O interfacing. For this type of interfacing, we use latches and buffers for
interfacing the keyboards and displays with the microprocessor.

But the main drawback of this interfacing is that the microprocessor can perform only one
function.

8279 Programmable Keyboard

The Intel 8279 is a programmable keyboard interfacing device. Data input and display are the
integral part of microprocessor kits and microprocessor-based systems.

8279 has been designed for the purpose of 8-bit Intel microprocessors.

8279 has two sections namely keyboard section and display section.

Some important Features are:

o Simultaneous keyboard display operations

o Scanned sensor mode
o Scanned keyboard mode
o 8-character keyboard FIFO
o Strobed input entry mode
o 2-key lock out or N-key roll over with contact debounce
o Single 16-charcter display
o Dual 8 or 16 numerical display
o Interrupt output on key entry
o Programmable scan timing and mode programmable from CPU

8257 DMA Controller

The data transfer from fast I/O devices to the memory or from the memory to I/O devices
through the accumulator is a time consuming process. For this situation, the Direct Memory

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Access (DMA) technique is preferred. In DMA data transfer scheme, data is directly
transferred from an I/O device to RAM or from RAM to an I/O device.

Using a DMA controller, the device requests the CPU to hold its address, data and control bus,
so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.

How DMA operations are performed?

Following are the operations performed by a DMA:

o Initially, the device has to send DMA request (DRQ) to DMA controller for sending
the data between the device and the memory.
o The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU for
the HLDA.
o When CPU gets the HLDA signal then, it leaves the control over the bus and
acknowledges the HOLD request through HLDA signal.
o Now the CPU is in the HOLD state and the DMA controller has to manage the
operations over the buses between the CPU, memory and I/O devices.

Intel 8257

o The Intel 8257 is a programmable DMA controller.

o It is a 4-channel programmable Direct Memory Access (DMA) controller.
o It is a 40 pin I.C. package and requires +5V supply for its operation.
o It can perform three operations, namely read, write, and verify.
o Each channel incorporates two 16-bit registers, namely DMA address register and byte
count register.
o Each channel can transfer data up to 64kb and can be programmed independently.
o It operates in 2 -modes: Master mode and Slave mode.

8257 Architecture

The following diagram is the architecture of Intel 8257:

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8257 Pin Description

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DRQ0 - DRQ3: These are DMA request lines. An I/O device sends the DMA request on one
of these lines. On the line, a HIGH status generates a DMA request.

DACK0 - DACK3 : These are DMA acknowledge lines. The Intel 8257 sends an
acknowledge signal through one of these lines informing an I/O device that it has been
selected for DMA data transfer. On the line, a LOW acknowledges the I/O device.

A0 - A7: These are address lines. A0 - A3 are bidirectional lines. These lines carry 4 LSBs of
16-bit memory address generated by the 8257 in the master mode. In the slave mode, these
lines are all the input lines. The inputs select one from the registers to be read or programmed.
A4 - A7 lines gives tristated outputs in the master mode which carry 4 through 7 of the 16-bit
memory address generated by the Intel 8257.

D0 - D7: These are data lines. These are bidirectional three state lines. While programming the
controller the CPU sends data for the DMA address register, the byte count register and the
mode set register through these data lines.

AEN: Address latch enable.

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ADSTB: A HIGH on this line latches the 8MSBs of the address, which are sent on D-bus, into
Intel 8212 connected for this purpose.

CS: It is chip select.

(I/OR): I/O read. It is a bidirectional line. In output mode it is used to access data from the I/O
device during the DMA write cycle.

(I/OW): I/O write. It is a bidirectional line. In output mode it allows the transfer of data to the
I/O device during the DMA read cycle. Data is transferred from the memory.

MEMR: Memory read

MEMW: Memory write

TC: Byte count (Terminal count).

MARK: Modulo 128 Mark.

CLK: Clock

HRQ: Hold request

HLDA: Hold acknowledge

Programmed data transfer

Programmed data transfer scheme is sub-divided into the following:

 z Synchronous mode of data transfer,

 z Asynchronous mode of data transfer and
 z Interrupt driven mode of data transfer.

In this scheme, data transfer takes place under the control of a program which resides in the
main memory of the system. It is relatively slow and applied for cases when the number of
bytes of data is small. This scheme is suitable for relatively slow peripherals.

The block schematic of a programmed data transfer scheme is shown below

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For an input from or an output to a peripheral device, an I/O instruction is issued to a device
decoder which therefore selects the corresponding multiplexer (for input) or demultiplexer (for
output) respectively.
The peripheral is tested for its readiness by means of a F/F. When the peripheral is ready, data
from the peripheral goes to the accumulator of microprocessor or vice-versa for input or output
peripherals respectively.
Since peripherals are usually slower than microprocessors, data are usually latched from the
bus before actually handed over to the peripheral via the demultiplexer.

functions needed for peripheral interfacing

The important functions are: buffering, address decoding, command decoding and timing and
control.
Buffering is necessary to increase drive and also to synchronise data exchange between the
microprocessor and peripheral.
A particular I/O is selected with the help of address decoding.
Command decoding is needed for some special I/Os that perform jobs other than data
transfers—e.g. rewinding a tape drive. For coordinating the above three, timing and control is
needed.

Categories of interfacing peripherals

The interfacing peripherals are classified into two categories:
z General purpose peripherals.
z Special purpose peripherals.

Examples of some general purpose peripherals are:

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  z Input/output ports
 z Programmable Interrupt Controller (PIC)
 z Programmable interval timer
 z Programmable communication interface
 z Programmable DMA interface
 z Multipurpose programmable device.

 While some of the special purpose peripherals are:

 z Programmable CRT controller

 z Programmable floppy disk controller
 z Programmable keyboard and display interface.

It is relatively easy to interface a memory with a processor because memories are usually
manufactured with the same technology as those of the CPUs and they are compatible
to the CPUs with regard to speed and electrical compatibility.
But when an I/O device is interfaced with a processor, the following incompatibilities
may arrive. These are:
z Speed incompatibility.
z Format incompatibility.
z Electrical characteristic incompatibility.
The first incompatibility arises because in many cases the I/O devices are slower than
the processor so that a situation may arise when the processor is in a position to accept
data but the peripheral, because of its slow nature, is unable to provide valid data.
The second incompatibility may arise if a 12-bit or 16-bit ADC or DAC is tried to be
interfaced with an 8-bit microprocessor like 8085.
The third incompatibility may be due to current or voltage incomparability or both.
Thus if a 12 V relay is to be driven by the SOD pin of 8085—both incompatibilities would
be there. First the voltage (5 V) from the SOD pin is to be boosted to 12 V and also the
current required to drive the relay should be provided. Thus it needs buffering.

synchronous mode of data transfer

Synchronous mode of data transfer is performed for peripherals whose timing characteristics
is precisely known. In this mode the status of the device is not checked before undertaking any
data transfer, that means, the device is assumed to be ready when data transfer takes place.

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(a) corresponds to the case when the peripheral is in speed compatible with the CPU, while
Fig. (b) corresponds to slower peripherals. For both Figs. 7.2(a) and (b), the timing
characteristics of the peripheral should exactly be known

Asynchronous mode of data transfer scheme

In this case the CPU initiates data transfer with the peripheral. The device (peripheral) status
is checked by the CPU before undertaking data transfer. This mode is used when the timing
characteristics of the device is unpredictable.

In this mode, the CPU confirms the readiness of the device status before undertaking data
transfer. This is why this scheme is known by the name “handshaking I/O”.

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Main disadvantage of mode of data transfer asynchronous mode of data transfer, If there is an
appreciable time gap from the instant the microprocessor starts checking the ‘device ready’
signal and its (device) actual readiness, the system loops the loop, as is evident from Fig. above.

This is a time simply wasted by the processor until the device is ready with valid data. In an
unfortunate situation, the system may enter into an infinite loop if the device does not become
ready at all.

interrupt driven mode of data transfer.

Discuss the interrupt driven mode of data transfer.

Ans. Main characteristic of this mode of data transfer is that data exchange between
peripheral and the processor is initiated by the device.
This mode is used for data transfer with slow peripherals and also when the
occurrence of data is unpredictable in nature.

The steps which are followed in this mode are:

 z An interrupt is requested by a peripheral device.

 z An acknowledgement of the request is issued by the processor at the end of the
 execution of the current instruction.
 z The program then branches to Interrupt Service Subroutine (ISS) program at which
 the program corresponding to the interrupting device is already stored. The return
 address (in the PC) is stored in the stack along with other register contents as per
 program needs.
 z Data transfer takes place under ISS.
 z Interrupt system is enabled.
 z The program then returns to the main program after loading the return address from
 stack in program counter (PC).

The flowchart corresponding to this scheme is shown below:

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Whereas in the asynchronous mode of data transfer scheme it is the processor which goes on
checking the device status, in the interrupt driven mode of data transfer scheme it is the device
which interrupts the system.

Interrupt driven mode of data transfer scheme is divided into two categories: Polled interrupt
and vectored interrupt. Again polled interrupt can be of two types: software polling, hardware
polling.

Polled interrupt can be of two types and is used when many devices are connected to the system.
In a polled interrupt scheme (whether hardware or software), each device is tested, using either
hardware or software, until the device which has requested the interrupt, is identified.
Corresponding to the device thus identified, the program is then diverted to the ISS written for
that device.

In polled interrupt scheme (whether hardware/software) the priority of each device is fixed (by
the programmer). It will take time before the interrupting device is identified. On the other
hand, in the vectored interrupt scheme the requesting device causes the program to be branched
to the ISS straightway. Hence vectored interrupt schemes are, in general, faster than polled
interrupt schemes.

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Software polling

. The flowchart for software polling scheme is shown below. It shows four devices whose status
are checked in software one after the other. As per the scheme, device 1 has the highest priority
while the lowest priority device is device 4. The status of each device are ORed and connected
to INTR pin of the processor. On occurrence of an interrupt, the flag of each device is tested
as per the software polling scheme.

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DMA (Direct Memory Access) mode of data transfer.

Instruction set of a processor provides for data transfer between processor registers and
memory or I/O device. Thus when data transfer between memory and a I/O device is needed,
it is done in two steps—from memory to accumulator of processor and then to I/O device or
reverse. This slows down data transfer.
DMA mode is introduced to overcome this.
In DMA mode, straight data exchange takes place between memory and I/O device bypassing
the processor. This is done with the help of a DMA controller. In DMA mode, the DMA
controller acts as a ‘Master’ and the processor as a ‘Slave’.
The processor must have the following features to facilitate DMA mode of data transfer:
 z An input line through which the processor accepts request from DMA controller for
 DMA mode of data transfer (This is the ‘HOLD’ pin for mP 8085).
 z An output line through which the processor tells the DMA controller that it
(processor)
 has accepted the request (This is the ‘HLDA’ pin for mP 8085)

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  z The processor must tristate its AB, DB and necessary control lines before handing
over
 the control to the DMA controller.

 The DMA controller IC must have the following features:

 z An output line through which it requests the processor for DMA mode of data
transfer.
 z An input line through which it accepts the granted DMA request from the processor.
 z Control over the AB, DB and the necessary control lines.

Address space
It is defined as the set of all possible addresses that a microprocessor can generate.

8085 microprocessor has a 16-bit address bus so that it can address 216 or 64 KB of address—
called the address space of 8085. This total address space can be partitioned or allocated to
memory or I/O devices so that they can be addressed properly.

This is called address space partitioning.

The address space can be partitioned in two ways. These are:
z Memory mapped I/O scheme.
z I/O mapped I/O scheme.

Memory mapped I/O scheme.

In this scheme, there is only one address space. This address space is allocated to both
memory and I/O devices. Some addresses are assigned to memories and some to I/O
devices. The address for I/O devices is different from the addresses which have been
assigned to memories. An I/O device is also treated as a memory location. In this scheme
one address is assigned to each memory location and one address is assigned to each
I/O device.
In this scheme, all data transfer instructions of the microprocessor can be used for
transferring data from and to either memory or I/O devices. For example, MOV D,M
instruction would transfer one byte of data from a memory location or an input device
to the register D, depending on whether the address in the H-L register pair is assigned
to a memory location or to an input device. If H-L contains address of a memory location,
data will be transferred from that memory location to register D, while if H-L pair
contains the address of an input device, data will be transferred from that input device
to register D.
This scheme is suitable for small systems. In this scheme, IO/ M signal is not used
to distinguish between memory

I/O mapped I/O scheme.

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Some CPUs provide one or more control lines (for example, IO/ M line for 8085), the
status of which indicates either memory or I/O operation. When the status of IO/ M line is high,
it indicates I/O operation and when low, it points to memory operation. Thus,
in this case, the same address may be assigned to both memory or an I/O device— æ
depending on the status of IO/M line.
The above scheme is referred to as I/O mapped I/O scheme. Here two separate
address spaces exist—one space is meant exclusively for memory operations and the
other for I/O operations. Usually, the space earmarked for I/O is much smaller than
memory space.

The following figure shows, pictorially, both the schemes. Here it is assumed that the system
has a 64 KB of memory and 256 I/O space.

I/O mapped I/O is also known as standard I/O. A maximum of 28 = 256 I/Os can be addressed
in this mode, because in this mode a 1-byte address is specified.

The instructions available in memory mapped I/O scheme are LDA, LDAX, STA, STAX,
MOV M, r etc. while those for I/O mapped I/O scheme are IN and OUT. The CPU sends out
an 8-bit code to identify the particular port address.
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The main advantage of memory mapped I/O scheme is that all memory reference instructions
are available in this scheme.

Total memory capacity: 2 KB RAM and 2 KB ROM = 4 KB. This requires 12 address
lines
(212 = 4 K). Out of 12, 11 address lines (A0 to A10) of microP are connected to 11 memory
address lines. Address line A11 is used as chip select. The RAM chip is selected when A11
is low and ROM gets selected for A11 = 1.
The two address lines are connected to A15 and A14. Thus, the 16-bit address line
would be:

In this scheme, IO/ M signal distinguishes A0 between an I/O and a memory. Memory
addressing is done exactly in the A11 same manner as discussed in above.
In this scheme, the input and output devices are identified by IO/ M along with A0 address
line, while the RAM and ROM are identified by IO/ M signal along with A11 address line.
The scheme of decoding is shown below

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NB/ WAIT states are used to interface slow peripherals to the processor.

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Microprocessor Applications: Interfacing scanned multiplexed displays and Liquid crystal
displays, Interfacing matrix keyboard, Stepper motor interfacing, Case studies of
microprocessor based systems, Standards for bus architecture and ports. Bus structure, and
timing and activities of bus cycles of 8086 microprocessor.

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