IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO.

3, MARCH 2023 1097

A 95.2% Efficiency DC–DC Boost Converter Using

Peak Current Fast Feedback Control (PFFC) for
Improved Load Transient Response
Shashank Alevoor , Member, IEEE, Rakshit Dambe Nayak , Member, IEEE, Bhushan Talele , Member, IEEE,
Abhishek Ray , Student Member, IEEE, Joseph D. Rutkowski, Senior Member, IEEE,
Troy Stockstad , Member, IEEE, and Bertan Bakkaloglu, Fellow, IEEE

Abstract— The load transient response and unity gain

bandwidth of DC-DC boost converters are primarily restricted
by the presence of a right half plane zero (RHPZ). In this
paper, a control scheme termed peak current fast feedback
control (PFFC) is proposed to improve the load transient
response without the need for additional power switches
or passive components. In the proposed PFFC method,
the closed loop output impedance (Z O C L ) is improved by
reducing the DC value and by increasing the bandwidth
of Z O C L as compared to conventional peak current mode
control (CPCM), thus improving the steady state and transient
performance. The fast feedback (FFB) path is implemented
within the error amplifier (EA) with an increase of only
2% in the active area as compared to CPCM. The boost
converter is designed for VOU T = 5V, VI N = 2.5V-4.4V
and IL O A D = 10mA-1A operating at a fixed frequency of 2MHz.
Measurement results show that with PFFC enabled, the settling
time reduces by ∼2.6× and the undershoot reduces by 62%
to 12µs and 41mV respectively when compared to CPCM for
10mA to 1A load step at 2A/µs. The converter achieves a peak
efficiency of 95.2% at 0.5W output power with VI N = 4.4V and
load regulation of 9mV/A at VI N = 2.5V.
Index Terms— Boost converter, peak current fast feedback Fig. 1. (a) Power stage of boost converter, (b) CCM operation waveform.
control (PFFC), fast load transient response, right-half-plane zero
(RHPZ), slew-rate controlled driver.
density while supporting wide range of load currents [7], [8],
[9], [10]. One of the critical challenges in the design of DC-DC
I. I NTRODUCTION boost converters is regulating the output voltage for fast load
transients [11], [12], [13].
D C-DC boost converters are used in various applications
such as display, camera flashlight, memory and haptic
drivers in battery operated devices and energy harvesting
The power stage of a typical DC-DC inductive boost
converter with continuous conduction mode (CCM) operation
systems [1], [2], [3], [4], [5], [6]. The increasing demand for waveforms are shown in Fig. 1. During the magnetizing phase,
high performance operation of these systems drives the need when MN is turned ON and MP is turned OFF, builds energy
for robust power supply with high efficiency and high-power in the inductor and during the demagnetizing phase, when MN
is turned OFF and MP is turned ON, the energy is transferred
Manuscript received 19 May 2022; revised 28 July 2022 and 6 November from the input to the output of the boost converter. Which
2022; accepted 28 November 2022. Date of publication 23 December 2022; results in a discontinuous energy transfer to the output, which
date of current version 27 February 2023. This article was recommended by
Associate Editor M. Hella. (Corresponding author: Shashank Alevoor.) causes an inherent delay in recharging the output capacitor
Shashank Alevoor, Rakshit Dambe Nayak, Abhishek Ray, and during transient events.
Bertan Bakkaloglu are with the Department of Electrical and Computer Unlike the buck converter, the transient performance of
Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail:
[email protected]). a boost converter cannot be improved by increasing the
Bhushan Talele, Joseph D. Rutkowski, and Troy Stockstad are with unity gain bandwidth due to the presence of a right half
Qualcomm Technologies Inc., Chandler, AZ 85226 USA. plane zero (RHPZ) in the duty-cycle (D) to output voltage
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2022.3227901. (VOU T ) transfer function in continuous conduction mode [14],
Digital Object Identifier 10.1109/TCSI.2022.3227901 [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25].
1549-8328 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 1098 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO. 3, MARCH 2023

The location of the RHPZ depends on the value of the load [24] uses output redefinition technique to define a new output
current (I L O AD ), inductor (L) and D and is given by (1) where of boost converter by combining input and output currents
D  = 1 − D. This RHPZ, defined by whose summed characteristics are minimum phase. In this
 technique the output current and the reference current do not
D 2 VOU T
ω Z (R H P) = (1) track properly resulting in tracking error. Reference [25] uses
I L O AD L adaptive voltage position technique to change the reference
limits the maximum achievable UGB of the boost converter voltage to minimize the effect of RHPZ. Due to the limited
at higher load conditions and low input voltage applications, load regulation of this technique this might not be suitable for
this presents a challenge in improving the transient response converters used as regulators.
of the converter. In this paper a control technique termed fixed frequency
Several techniques have been explored in the past to peak current fast feedback control (PFFC) to overcome the
alleviate the effects of RHPZ and improve the transient drawbacks of the previous approaches is presented. The pro-
response of the boost converter. Adaptive compensation posed architecture achieves enhanced transient performance
control (ACC) technique in [11] and [12] is a non-linear without the need for any additional power stage components
approach in which the bandwidth of the error amplifier is or altering the UGB of the system. This also reduces the design
increased by pushing the dominant pole to higher frequency complexity with minimal additional silicon area overhead
due to reduction in compensation capacitance during transient and cost. In the proposed approach, the closed loop output
events. Variable transient event (VTE) technique in [13] is impedance (Z OC L ) of the boost converter is improved by
another non-linear approach in which reference voltage is reducing its DC value and increasing its bandwidth as
modulated during transient events. In both these cases the compared to the conventional peak current mode control
transient performance improves but has the disadvantage of (CPCM) using a fast feedback (FFB) path. The lower DC
loop instability during transient events [11], [12] and glitches value of Z OC L results in an improved load regulation while
occur on the output voltage due to dynamic pole shifting the higher bandwidth of Z OC L results in lower undershoot and
or reference voltage modulation [13]. Adaptive on-time overshoot at the output which aids in faster settling time.
scaling with digitally controlled frequency hopping [14] takes The converter can be configured to operate in 2 modes,
advantage of frequency hopping and adaptive on-time for 1) Continuous feedback mode (PFFC): always on PFFC,
improved load transient. This approach has the drawback 2) Transient enhancement mode (PFFC-TEM): Enter PFFC
of requiring digitally intensive frequency hopping circuits only during a load transient event and remain in CPCM for
to achieve improvement in load transient performance and steady state. The closed loop system is designed to be stable
requiring frequency locked loop (FLL) for frequency locking even during transient enhancement mode and provides glitch
of the converter during steady state. Reference [15] is an free output voltage.
adaptive on time (AOT) control with a drawback of quasi-fixed The rest of the paper is organized as follows. The small
frequency as it does not control the switching frequency using signal stability analysis along with the output impedance for
FFL or phase locked loop to keep the frequency constant. the proposed PFFC approach in comparison to the CPCM
Another approach is to modify the power stage to alleviate is presented in Section II. The circuit implementation of
the effects of RHPZ. References [16] and [17] is a hybrid controller, the slew-rate controlled driver and the supporting
DC-DC converter utilizing two path power delivery to blocks are described in Section III. Measurement results and
effectively reduce average inductor current and push the RHPZ performance metrices are presented in Section IV followed by
to higher frequency at the cost of an external capacitor conclusions in Section V.
and additional power switches resulting in the increase of
the silicon area. Interleaved time multiplexing [18] pushes
II. P ROPOSED A PPROACH / PFFC
the RHPZ to higher frequency equivalent to the number
of interleaved stages by reducing the current through each The block diagram of the proposed PFFC control is shown
inductor and requires complex control for current balance in Fig. 2. In a conventional peak current mode control,
of each stage and an additional external inductor for each there is a fast current loop and a slow voltage loop for the
interleaved stage. Reference [19] is a hybrid boost converter output voltage regulation. The error amplifier (EA) output
which achieves higher conversion ratio and RHPZ dependent (Vc ) and the sensed inductor current with slope compensation
on switching frequency by using additional power switches (Vslope ) drives the pulse width modulation (PWM) comparator
and flyback capacitor resulting in increased silicon area. to generate the desired D. In the proposed PFFC control,
Techniques like tristate control [20] or magnetic coupling an additional pair of differential signals VF F B P and VF F B M
of inductor [21] eliminate RHPZ utilizing an additional derived from the EA are added to the inputs of the PWM
freewheeling stage, inductors and power switch which incur comparator. In steady state operation, the difference between
additional power loss and increase the area of the converter. VF F B P and VF F B M is small since the output feedback
References [22] and [23] takes advantage of output capacitor signal (βVOU T ) is equal to V R E F . Hence, in the steady
effective series resistance (ESR) with leading edge modulation state operation of the proposed scheme, the duty cycle D
to move the RHPZ to left half plane, thereby eliminating the is modulated similarly as was done in CPCM. However,
RHPZ of the converter. But this requires large ESR which in the event of a load transient, the FFB path assists in
leads to higher ripple at the output of the boost converter. steering the inductor current in the desired direction faster.

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1099

Fig. 2. Block diagram of the proposed PFFC boost converter.

and VF F B M (VF F B P − VF F B M ). The positive difference

(VF F B P − VF F B M ) causes an incremental DC shift in the EA
output voltage to VC + (VF F B P − VF F B M ). This increases
the duty cycle of MN and forces the inductor current (I L ) to
increase faster as compared to CPCM. On the other hand,
for a high to low load transient, the overshoot in VOU T
results in a negative differential voltage between VF F B P and
VF F B M (VF F B P − VF F B M ). This negative difference causes
a decremental DC shift in the EA output voltage thereby
reducing the duty cycle of MN and forcing the inductor current
to reduce faster as compared to CPCM. Due to the fast
charging and discharging of the inductor current, the output
settles to the regulated value faster than CPCM controller, with
same UGB.

A. Small Signal Analysis

The small signal linearized block diagram of CPCM as
derived in [28] is shown in Fig. 4(a). The transfer functions for
d̂ to v̂ OU T (G V D ), d̂ to î L (G I D ), the sampling gain (He ), the
feedback gain (K r ) and the modulator gain (Fm ) can be found
in [26], [27], and [28]. R S N S is the current sense resistor and
β is the divider ratio of output voltage, as βVOU T is fed to the
type II compensator as shown in Fig. 2. G M F F B and R F F B
are the transconductance and output resistance of the FFB path
whose circuit implementation is shown in Section III. As FFB
path gains up the change in output voltage and feeds it into
the modulator, it effects only the feedback gain (K r ) from
output voltage to the modulator as shown in Fig. 4(a). The
Fig. 3. Representative waveforms of low to high load transient response and fast path gain of the PFFC is assumed as K F F B . The small
steady state in (a) CPCM control, (b) proposed approach PFFC.
signal linearization of FFB path is given by (2).
VF F B P − VF F B M = 2G M F F B R F F B (V R E F − βVOU T )
The representative waveforms comparing the steady state and  
v̂ F F B P − v̂ F F B M = 2G M F F B R F F B −β v̂ OU T
transient behavior of CPCM with PFFC control are shown in
= −K F F B (v̂ OU T )
Fig. 3. During a low to high load transient, the undershoot in
VOU T results in a positive differential voltage between VF F B P where K F F B = 2βG M F F B R F F B (2)

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 1100 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO. 3, MARCH 2023

Fig. 5. (a) G V C and G L O O P of CPCM control and PFFC, (b) Z OC L of

CPCM control and PFFC.

information regarding the load regulation and transient

performance at the output. To understand the load regulation
and transient performance of the converter, it is imperative to
analyze its closed-loop output impedance (Z OC L ). The block
Fig. 4. (a) Small signal model of PFFC and CPCM (b) small signal model diagram of Z OC L for the CPCM is shown in Fig 4(b). G M
to calculate closed-loop output impedance Z O C L. and R OU T is the transconductance and output resistance of the
error amplifier. R Z and CC is the compensation resistance and
Using the block representation in Fig. 4(a), the control capacitance of the Type II compensator. The Z OC L for CPCM
voltage (v̂ c ) to output voltage (v̂ OU T ) transfer function (G V C ) is given below by (5). The transfer function for open loop
is given by (3) and can be found in [28]. output impedance (Z OU T ) and equivalent inductance (L e ) are
given in [29]. G C is the controller transfer function with type II
v̂ OU T Fm G V D
GV C = = compensation of the voltage loop for the peak current mode
v̂ C 1 + Fm G I D He R S N S − Fm G V D K r control.
v̂ OU T GV D    
GV C = ≈ (3) He R S N S
v̂ C G I D He R S N S v̂ OU T Z OU T G V C 
D s Le + K r + 1
Z OC L = =
The DC gain A V C and dominant pole ω p of G V C for CPCM î L O AD 1 + GLOOP
is given by (4),  
RS N S R S N S 1 + psc
(1 − D) VOU T 2I L O AD ≈  = (5)
AV C = , ωp = D GC β D  AC β
2R S N S I L O AD VOU T C OU T
AC
where G V C =
AV C
(4) where G C = (1+ ω spc )
for low frequency and
(1 + pso )
1
As seen in (4), the A V C and ω p for CPCM is dependent AC = G M R OU T , ω pc = , G L O O P = G V C GC β
on the load current (I L O AD ) and output capacitor (C OU T ). R OU T CC
The loop gain (G L O O P ) of the converter gives the loop gain (5) shows that the closed-loop output impedance Z OC L is
and UGB of the converter but does not contain the complete dependent on the value of current sense resistor R S N S ,

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1101

Fig. 6. Error amplifier and compensation.

Fig. 8. Differential current sense circuit.

The changes in small signal transfer function due to the

FFB path are given by (6). The effective output feedforward
gain (K r ) changes compared to the CPCM control as shown
in Fig. 4(a) and (2).
K r (P F FC) = K r (C PC M) − K F F B
≈ −K F F B (6)
Fig. 7. (a) PWM comparator (b) functional waveform of PFFC-TEM.
The modified equation for G V C , A V C and ω p for PFFC are
given by (7). The ‘K r ’ term of PFFC is not negligible, and
this results in the enhanced transient performance.
DC gain of the controller (AC ) and the controller pole (ω pc ). GV D 1 1
Hence, Z OC L can be decreased without changing the UGB of GV C ≈ , AV C = =
G I D He R S N S − K r G V D −K r KFFB
the boost converter by increasing AC and ω pc of the controller.
K F F B D
Thus, the system can achieve better transient performance. The po = (7)
proposed PFFC control realizes this improvement in AC and 2C OU T
ω pc by only modifying the A V C and ω p of the controller with The boost converter with PFFC and CPCM are modeled in
the help of a FFB path from VOU T . Therefor PFFC achieves MATLAB for a C OU T = 20μF, L = 1μH, FS W = 2MHz,
better transient performance without modulating the loop UGB I L O AD = 1A, VI N = 3.5V and VOU T = 5V. The bode plot
or the location of RHPZ. comparison for G V C , G L O O P and Z OC L of CPCM and PFFC

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 1102 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO. 3, MARCH 2023

Fig. 9. Slew-rate controlled driver.

are shown in Fig. 5. Both PFFC and CPCM have the same peak inductor current for safe operation. During the discon-
UGB of 20kHz and phase margin of 73o . However, the Z OC L tinuous conduction mode (DCM) operation, the zero-current
for PFFC control has lower value at DC and high frequency detector (ZCD) detects the zero-crossing of the inductor
zero compared to CPCM control. current, and tri states the power stage to avoid delivering
The presence of the RHPZ in the system may result in power back to the input of the converter and improve
instability if the FFB path is active for frequencies close to efficiency.
RHPZ. To avoid this, a low pass filter capacitor C F F B is added Active clamps are included to clamp VC during extreme
to the output of FFB path as shown in Fig. 2. This low pass load transient conditions. High side clamp (VC L AM P H ) limits
filter places a limit on maximum value of K F F B which is given VC to limit the peak current and allows for safe operation.
by (8). On the other hand, the low side clamp (VC L AM P L ) clamps
K F F B D ω Z (R H P) VC in the linear region of the error amplifier for a high load
po = < (8) to low load transient and thus achieves faster mode transition
2C OU T 3
from DCM to CCM.
The UGB for the proposed PFFC and CPCM are maintained At very low load currents, the convertor operates in pulse
to be same for a fair and equitable comparison of the skip mode (PSM) during which the converter skips pulses to
approaches. This is achieved by increasing AC and ω pc of improve efficiency by reducing switching losses [30]. As load
PFFC when compared to CPCM. This is done by increasing current increases, the converter exits PSM when the low side
the G M of the error amplifier and the decreasing the value clamp is disabled after which the converter resumes normal
of compensation capacitor (CC ) of the type II compensator in operation.
comparison to the values for CPCM. Minimum ON and OFF time logic is also incorporated to
The circuit implementation of various blocks in the boost reduce the effect of RHPZ during heavy load transients [31].
converter and the integration of PFFC’s FFB path is discussed This logic ensures that some energy is transferred from the
in detail in Section III. inductor to the output in every cycle.

III. C IRCUIT L EVEL I MPLEMENTATION

Peak current mode control in boost converters is achieved A. Error Amplifier and Compensation
by sensing the inductor current across the low side MOSFET The circuit level implementation of the EA is shown in
(MN ). As shown in Fig. 2, the sensed current is then combined Fig. 6. The G M and G M F F B paths comprise of a common-
with the compensation slope for stability. This is then fed input stage and two output stages R OU T and R F F B which
to the PWM comparator to generate the duty cycle D of correspond to the slow and fast paths respectively.
the boost converter. The sensed current information is also The input stage is composed of a common source stage
used by the current limit (ILIM) comparator to limit the (M1 -M2 ) with source degenerated resistor (Rin ) [32], [33].

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1103

Fig. 10. Die micrograph.

A common source amplifier (M3 and M4 ) in feedback reduces

the source impedance of M1 and M2 leading to an increase
in the linearity of the transconductance (gm ). The FFB_EN
signal is used to enable the FFB path of PFFC. As explained in
Section II, a higher G M is required during PFFC. The FFB_EN
signal is thus employed to halve the value of Rin by effectively
changing the gm from 1/(4R I N ) for CPCM control to 1/(2R I N )
for PFFC.
The differential output of the common input stage
(V P − VM ) is then fed to the R OU T and R F F B stages to
generate the two sets of outputs used in the slow and fast Fig. 11. Steady state waveforms (a) V I N = 3.5V, V OU T = 5V for
I L O AD = 1A (b) V I N = 3.5V, V OU T = 5V for I L O AD = 10mA.
paths respectively. VC is the single ended output of the R OU T
stage whereas (VF F B P − VF F B M ) is the differential output of
the R F F B stage. The cascode output structure comprising of The FFB_EN signal is incorporated in the second set of
M5 to M12 is used to generate the high output impedance of differential inputs of the PWM comparator as well to better
R OU T . Similarly, a differential cascode structure comprising compare the benefits of using PFFC over CPCM with minimal
of M13 to M24 is used to generate the high output impedance changes to the EA and the PWM comparator. During CPCM
of R F F B . control, switches S2 and S4 connect the inputs to VC M and
The effective differential gain of the fast path from the FFB path is disabled. During PFFC, switches S1 and S3
its input to output is the ratio of R F F B /R I N , since the connect the inputs to signals VF F B M and VF F B P respectively
resistors are implemented of the same type, the process and the FFB path is enabled.
variation is minimized. Type-II compensation comprising of The controller can also be configured in PFFC-TEM.
CC and Rz is used to stabilize the controller on the slow During this mode, switches S2 and S4 connect the inputs
path. to VC M in steady state and switches S1 and S3 connect
the inputs to signals VF F B M and VF F B P respectively during
the transient event. This is implemented by dynamically
B. Pulse Width Modulation Comparator modulating FBB_EN during the transient event.
The implementation of Pulse Width Modulation (PWM) The functional waveform of this operation is shown in
comparator is shown in Fig. 7(a). The input summing Fig. 7(b). Two hysteretic comparators with outputs COMP1
stage of the PWM comparator is a degenerated common and COMP2 are used to detect the overshoot and undershoot
source amplifier for increased linearity with an effective of VOU T . If VOU T increases above V R E F H or drops below
transconductance equal to 1/R. The linearity of the input V R E F L , PFFC is enabled using the FFB_EN signal. A 50mV
summing stage is critical as the inputs VC , I L∗ R S N S +VS L O P E , hysteresis window is added to the comparators to avoid a false
VF F B P and VF F B M need to be summed differentially to avoid trigger of a transient event and for smooth transition between
erroneous duty cycle modulation. The output impedance of the steady-state CPCM and transient PFFC.
input stage is R, which results in effective differential gain of The additional RFFB stage in EA and the extra summing
2R/R at the outputs V P and VM . The input summing stage is stage in PWM comparator are required for the implementation
followed by a gm -R based pre-amplifier stage and a decision of PFFC along with CPCM. This is implemented with only
stage. 2% increase in active area compared to CPCM.

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 1104 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO. 3, MARCH 2023

Fig. 12. Load transient response at V I N = 3.5V, V OU T = 5V and Fig. 13. Load transient response at V I N = 3.5V, V OU T = 5V and
I L O AD = 10mA→1A (2A/μs) (a) CPCM (b) PFFC (c) Comparison of I L O AD = 1A→10mA (2A/μs) (a) CPCM (b) PFFC (c) Comparison of
CPCM and PFFC. CPCM and PFFC.

C. Current Sense Structure structure is disabled using the VN D RV signal during the
demagnetizing phase. The VN D RV _S N S signal is used to enable
As shown in Fig. 8, IL is sensed across the low-side the sensing structure after MN is enabled and disable it before
power MOSFET MN by sensing the drain-to-source voltage MN is turned OFF. This ensures safe operation of the sensing
using a sense MOSFET MS . The ratio of MN to MS is K, structure. The sensed current I S N S flows through the feedback
resulting in equivalent resistance of K∗ RN . The equivalent transistor M5 and is mirrored using M6 for use in ILIM and
circuit of the current sense architecture is also shown in slope compensation.
Fig. 8, and a sense ratio of ISNS /8 is achieved using this
approach as compared to conventional current mirror FET
based sense architecture. Thus, this architecture maintains D. Slew-Rate Controlled Driver
the same current-sense accuracy as that of conventional A slew-rate controlled (SRC) technique is employed to
approaches and achieves a higher step-down ratio. The current minimize the ringing on the switch node (VS W ) by modulating
sense amplifier is implemented using a common-gate (CG) the resistance of MN and the slew-rate of the gate terminal
amplifier. VN G AT E during switching. The ringing on VS W is primarily
As the controller is based on peak-current control, IL is caused by the parasitic inductance and capacitance during
sensed only during the magnetizing phase. The current sense the turn ON/OFF events of MN for a boost converter.

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1105

Fig. 14. Load transient response at V I N = 3.5V, V OU T = 5V

(a) PFFC-TEM for I L O AD = 10mA→1A (2A/μs) (b) PFFC-TEM for
I L O AD = 1A→10mA (2A/μs).

Fig. 16. (a) V OU T regulation for I L O AD change (b) V OU T regulation for

V I N change (c) Efficiency plot.

Fig. 15. Soft startup.

This ringing results in additional stress and can also lead to

eventual breakdown of MN . To reduce ringing, it is necessary
to have smooth transition of the gate voltage VN G AT E in the
miller plateau region during switching events [34].
The SRC driver implementation for the power MOSFET Fig. 17. Line transient response of CPCM at V OU T = 5V, I L O AD = 700mA
for V I N = 3V ↔ 4V (280μs time period).
MN is shown in Fig. 9. MN is driven by two drivers of low
strength (LSD) and high strength (HSD). A signal HSD_EN
is used to enable the HSD after VN G AT E crosses the miller MN1 pulls the node VL H low when VN G AT E is above two
plateau both during turn ON and turn OFF. During turn ON, times the threshold voltage (2∗ VT ). Similarly, during turn OFF,

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 1106 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 70, NO. 3, MARCH 2023

TABLE I
C OMPARISON OF THE P ROPOSED PFFC B OOST C ONVERTER W ITH P RIOR W ORK

efficiency of the converter as compared to fixed deadtime

approaches.

IV. E XPERIMENTAL R ESULTS

The proposed boost converter was fabricated in a 0.18μm
BCD process. The die micrograph is shown in Fig. 10. The
chip area is 2.6mm × 2.4mm and the active area is 0.6mm2.
Fig. 11 shows the measured steady-state waveforms of the
output voltage (VOU T ), the inductor current (I L ) and switch
node (VS W ) for the boost converter. Fig. 11(a) shows the
steady state waveforms at VOU T = 5V and VI N = 3.5V for an
I L O AD = 1A. At I L O AD = 1A, the converter operates in CCM
with a period of 510ns corresponding to a switching frequency
of ∼2MHz. Fig. 11(b) shows the steady state waveforms
Fig. 18. Line transient response of PFFC at V OU T = 5V, I L O AD = 700mA
for V I N = 3V ↔ 4V (280μs time period). at VOU T = 5V and VI N = 3.5V for I L O AD = 10mA.
At I L O AD = 10mA, the converter operates in pulse skip mode
(PSM) with a period of 17.5μs corresponding to a switching
frequency of ∼57.1KHz. The time period in PSM at 10mA
transistor MN3 pulls node V H L low only when VN G AT E is is 34× the fundamental time period in CCM due to pulse
below VT . HSD_EN signal enables the HSD immediately after skipping. This increases the efficiency by reducing switching
detecting the miller plateau crossing during both the turn ON losses as the power stage is tri-stated for multiple cycles.
and turn OFF events. Fig. 12(a) and Fig. 12(b) show the load transient response
The signals DT_FB_HL and DT_FB_LH are also used for of PFFC and CPCM at VOU T = 5V and VI N = 3.5V
deadtime control since these signals indicates the entry and for an I L O AD = 10mA→1A at a slew rate of 2A/μs. The
exit from the miller plateau. The deadtime can be adaptively measured settling time and undershoot voltage of PFFC are
changed for different inductor currents thus improving 12μs and 41mV respectively, while for CPCM it is 108mV

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1107

and 32μs respectively. The comparison of VOU T in PFFC driver is also implemented to achieve adaptive dead time
and CPCM for this load transient is also shown in Fig. 12(c). control of the boost converter and reduce switching losses.
The PFFC is 2.6× faster and reduces the undershoot by 62% Silicon measurement results are also showcased to validate
when compared to CPCM. Fig. 13(a) and Fig. 13(b) show the proposed architecture. The boost converter is designed
the load transient of PFFC and CPCM at VOU T = 5V and for a VOU T = 5V, VI N = 2.5V to 4.4V and a maximum
VI N = 3.5V for an I L O AD = 1A→10mA at a slew rate I L O AD = 1A. The PFFC approach improves the settling
of 2A/μs. The measured settling time and overshoot voltage time by 12× to 26us and reduces the overshoot by 56%
of PFFC for this load release condition are 26μs and 56mV to 56mV when compared to CPCM for I L O AD = 10mA
respectively, while for CPCM it is 311μs and 128mV. The to 1A (@2A/us). On the other hand, the PFFC approach
transient response comparison of PFFC and CPCM for this improves the settling time by 2.6× to 12us and reduces the
load change is shown in Fig. 13(c). The PFFC is 12× faster undershoot by 62% to 41mV when compared to CPCM for
and reduces the overshoot by 56% when compared to CPCM. I L O AD = 10mA to 1A (@2A/us). The measurement results
Fig. 14(a) shows the load transient response of transient show the effectiveness of the proposed approach to improve
enhancement mode (PFFC-TEM) at VOU T = 5V and VI N = the settling time and reduce the output voltage change for both
3.5V for I L O AD = 10mA→1A at a slew rate of 2A/μs. The the PFFC and the PFFC-TEM approaches. The FFB path is
measured settling time and undershoot voltage of PFFC-TEM implemented within error amplifier with an increase of 2% in
is 16μs and 72mV respectively. PFFC-TEM is 2× faster and the active area compared to CPCM. The improvement in load
reduces the undershoot by 34% when compared to CPCM. transient is achieved without the need for additional power
Fig. 14(b) shows the transient response of PFFC-TEM at switches or passive components. This control technique is not
VOU T = 5V and VI N = 3.5V for I L O AD = 1A→10mA limited to DC-DC boost converter and can also be extended
at a slew rate of 2A/μs. The measured settling time and to other bandwidth limited converters like flyback, buck-boost
overshoot voltage of this mode is 28μs and 68mV respectively. and other converters.
The PFFC-TEM is 11× faster and reduces the overshoot
by 47% when compared to CPCM. This shows that PFFC- ACKNOWLEDGMENT
TEM preserves the transient benefits of PFFC even though it The authors would like to thank Qualcomm Technologies
operates in CPCM during steady state. As shown in Fig. 15, the Inc., Chandler, AZ, USA, for this project.
boost converter completes the soft-startup sequence in 101μs.
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M.S. degree in electrical engineering from Arizona
with dual-ramp modulation scheme and translinear loop-based current
State University, Tempe, AZ, USA, in 2017,
sensor for WiFi IoT applications,” IEEE J. Solid-State Circuits, vol. 56,
where he is currently pursuing the Ph.D. degree.
no. 8, pp. 2388–2401, Aug. 2021.
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Design Intern at Qualcomm, Chandler, AZ, USA, in
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“Time-multiplexing current balance interleaved current-mode boost working as an Analog Design Engineer with Cirrus Logic, Mesa, AZ, USA,
DC–DC converter for alleviating the effects of right-half-plane zero,” where he is involved in the design of fast transient low quiescent current
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1.2-A high driving current and 20% reduction of inductor DC current
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converter using magnetic coupling with forward energy transfer,” IEEE Arizona State University, Tempe, AZ, USA, in 2018,
Trans. Ind. Electron., vol. 66, no. 11, pp. 8454–8462, Nov. 2019. where he is currently pursuing the Ph.D. degree.
[22] V. V. Paduvalli, R. J. Taylor, L. R. Hunt, and P. T. Balsara, “Mitigation From 2014 to 2016, he was a Design Engineer
of positive zero effect on nonminimum phase boost DC–DC converters at Sankalp Semiconductors Pvt. Ltd., Hubli, India,
in CCM,” IEEE Trans. Ind. Electron., vol. 65, no. 5, pp. 4125–4134, where he was involved in design and characterization
May 2018. of standard cell libraries. He was an Analog Design
[23] D. M. Sable, B. H. Cho, and R. B. Ridley, “Use of leading-edge Intern at Kilby Labs, Texas Instruments, Santa Clara,
modulation to transform boost and flyback converters into minimum- CA, USA, in 2021, with NXP Semiconductors,
phase-zero systems,” IEEE Trans. Power Electron., vol. 6, no. 4, Chandler, AZ, USA, in 2019 and 2020; and Dialog
pp. 704–711, Oct. 1991. Semiconductor, Chandler, in 2017, where he worked on the system level
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current in a boost converter using output redefinition,” IEEE Trans. for PMICs, respectively. His current research interests include low-power
Power Electron., vol. 29, no. 9, pp. 5054–5062, Sep. 2014. analog and mixed-signal circuit designs for high efficiency dc–dc power
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supplies,” Texas Instrum., Dallas, TX, USA, Tech. Rep. SLVA061, 2002.
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2nd ed. New York, NY, USA: Springer, 2001. and Ph.D. degrees in electrical engineering from
[28] R. B. Ridley, “A new continuous-time model for current-mode control Arizona State University, Tempe, AZ, USA, in 2017
with constant frequency, constant on-time, and constant off-time, in and 2021, respectively. From 2013 to 2015, he was
CCM and DCM,” in Proc. 21st Annu. IEEE Conf. Power Electron. Spec., an Analog Circuit Designer at Cadence Design
1990, pp. 382–389. Systems, Bengaluru, India, where he was involved in
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output impedances of DC–DC switching converters operating in voltage a Design Intern at Kilby Labs, Texas Instruments,
and current mode control,” in Proc. 36th Annu. Conf. IEEE Ind. Electron. in 2019 and 2018, respectively, and Qualcomm,
Soc. (IECON), Nov. 2010, pp. 2311–2316. San Diego, CA, USA, in 2017, where he was
[30] N. Beohar et al., “A digitally controlled DC–DC buck converter with involved in designing voltage references and class-D
automatic digital PFM to PWM transition scheme,” in Proc. IEEE Appl. audio amplifiers and haptic drivers, respectively. Since 2022, he has been
Power Electron. Conf. Expo. (APEC), Jun. 2021, pp. 517–522. with the Power Management IC Design Group, Qualcomm. His current
[31] A. I. Pressman and T. Morey, Switching Power Supply Design, 3rd ed. research interests include low-power analog design and reliability for power
New York, NY, USA: McGraw-Hill, 2009, ch. 9. management IC design.

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 ALEVOOR et al.: 95.2% EFFICIENCY DC–DC BOOST CONVERTER USING PFFC FOR IMPROVED LOAD TRANSIENT RESPONSE 1109

Abhishek Ray (Student Member, IEEE) received Troy Stockstad (Member, IEEE) received the
the M.S. degree in electrical engineering from The B.S. degree in electrical engineering from North
University of Texas at Dallas, Dallas, TX, USA, Dakota State University in 1989, the M.S. degree in
in 2017. He is currently pursuing the Ph.D. degree in electrical engineering from the University of Hawaii
electrical engineering with Arizona State University. at Manoa in 1991, and the Ph.D. degree in electrical
He was an Analog Design Intern with Dialog engineering from Arizona State University in 1997.
Semiconductor, Chandler, AZ, USA, in 2019 and He joined Qualcomm Technologies Inc., Chandler,
2020, where he was involved in designing switching AZ, USA, in 2007, where he currently holds the title
battery chargers for portable devices. Since 2021, of Senior Director of Technology. He has spent the
he has been working as an Analog Design Engineer last several years working on power management ICs
with Cirrus Logic, Mesa, AZ, USA, where he is (PMICs) for mobile and adjacent market applications
involved in the design of low-dropout regulators and dc–dc switching in the areas of switched mode power supplies, data converters, battery
converters. His current research interests include low-power, mixed signal charging, and references. Prior to Qualcomm, he worked on RFICs with
analog design, and power management IC design. Airgo Networks and RFMD, high-speed linear analog and USB2.0 transceivers
with Standard Microsystems Corporation, and linear analog design and
data converters at Motorola Semiconductor. He has authored or coauthored
58 issued U.S. patents over his career.

Bertan Bakkaloglu (Fellow, IEEE) received the

Ph.D. degree from Oregon State University in
1995. He joined Texas Instruments Inc., Mixed
Joseph D. Rutkowski (Senior Member, IEEE) Signal Wireless Design Group, Dallas, TX, USA,
received the B.S. and M.S. degrees in electrical where he worked on system-on-chip designs with
engineering from Arizona State University, Tempe, integrated battery management and RF, analog
AZ, USA, in 2002 and 2004, respectively. He joined baseband functionality, as a Design Leader. In 2004,
the Interface Products Group, NXP Semiconduc- he joined the Department of Electrical Engineering,
tors/Philips Electronics, Chandler, AZ, USA, where Arizona State University, Tempe, AZ, USA, where
he was involved with analog, mixed-signal, power he is currently the ON Semiconductor Endowed
management circuit design. He development several Professor. His current research interests include
±1◦ C accurate temperature sensor products and mixed signal circuit design for power supply regulators, sensor interface
multiple boost converters for LCD panels and LED circuits, fractional-N frequency synthesizers, high-speed A/D and D/A
photo flash products. In 2010, he joined Qualcomm converters, and built-in-self-diagnostic circuits for high-reliability mixed
Technologies Inc., Chandler, where he helped develop the world’s first mobile signal circuits. He is a member of the National Academy of Inventors.
3G/4G LTE envelope tracking (ET) solution. He is currently a Senior Director He was the General Chair of 2015 IEEE RFIC Symposium and the Founding
of technology leading the User Interface Design Team, Qualcomm’s PMIC Chair of IEEE Solid State Circuits Society Phoenix Chapter. He has been an
Group, where he has led the development of various dc–dc converters, Associate Editor of IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —I:
including boost, buck, (inverting) buck-boost, SIMO, and several hybrid R EGULAR PAPERS and IEEE T RANSACTIONS ON M ICROWAVE T HEORY
converters. He holds 20 U.S. patents. AND T ECHNIQUES .

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