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5 lpc2103 I2C

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9 views

5 lpc2103 I2C

Uploaded by

Khải Nguyễn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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4.4.

Thiết kế các thành phần cơ


bản của bộ xử lý nhúng
(datasheet LPC2103)
+ I2C
I2C bus
• Two-wire, synchronous, serial interface
• Open-drain / open collector logic. External pull-ups
(10kohm typical)
• Slave devices selected via internal address (7-bit,
typical)
I2C. Bit timing
• SDA only changes when SCL is low
I2C. Start, Stop
• SDA edge with SCL high
• Bus idle with SDA and SCL both high
before start and after stop

START STOP
I2C. Byte transfer
• The device who listen to data must left SDAhigh
• Slave devices must assert ACK(SDAlow) after reading a byte
(address or data)
• The master must assert ACKon data read. In this case the last
byte of the frame is followed by NACK instead ofACK
I2C. Frame
• Write frame

• Read frame
Hardware I2C controller. Registers
Register Access Description
I2CONSET R/W Write: Set bits in Control Reg.
I2CONCLR WO Write: Clear bits in Control Reg.
I2STAT RO Status Reg.
I2DAT R/W Data reg.
I2ADR R/W I2C slave address (only used in slave mode)
I2SCLH R/W SCLhigh time (PCLKcycles)
I2SCLL R/W SCLlow time (PCLKcycles)

• Writing zeroes to bits in I2CONSET or I2CONCLR


has no effect
Hardware I2C controller. Control Reg.
• Bit 6: I2EN. I2C Enable bit.
• Bit 5: STA.Start bit. Setting this bit enters master mode and
sends an STARTcondition to the bus. SI is set whendone.
• Bit 4: STO.Stop bit. Setting this bit transmitsa STOP
condition (master mode)
• Bit 3: SI. Interrupt Flag. Set when an action is complete.
When one, the I2STAregister provides a suitable status
code. This bit has to be cleared by program (by writing to
I2CONCLR). Byte transfer is stopped while SI is set,
therefore, I2DAT must have valid data before clearing SI.
• Bit 2: AA.Assert Acknowledge. Enables the assertion of the
ACK bit in receivermodes.
Hardware I2C controller. Address Reg.
• Bit 0: GC. General Call. Enables the acknowledge of General
Call (broadcast) address (slave address = 0)
• Bits 7:1: SlaveAddress.
Hardware I2C controller operation
• Byte oriented controller.
• Master Mode
• First byte after STARTis the slave address plus R/Wbit.
• If R/W was one the controllerenters master receiver
mode. Otherwise it continues operating as master
transmitter.
• In master receiver mode AA must be set except for the
last byte.
Hardware I2C controller.
Status Codes for Master Transmitter

I2STAT Status Next action


0x08 STARTcondition transmitted Load Slave address + R/W=0
0x18 Slave address transmitted. ACKreceived Load data byte
0x20 Slave address transmitted. NACKreceived Transmit STOP
0x28 Data byte transmitted. ACKreceived Load data byte / transmit STOP
0x30 Data byte transmitted. NACKreceived Transmit STOP
Hardware I2C controller.
Status Codes for Master Receiver

I2STAT Status Next action

0x08 STARTcondition transmitted Load Slave address + R/W=1


0x40 Slave address transmitted. ACKreceived Data byte will be received
0x48 Slave address transmitted. NACKreceived Transmit STOP
0x50 Data byte received. ACKtransmitted Data byte will be received
0x58 Data byte received. NACKtransmitted Transmit STOP
Master Transmitter (write) procedure
1. Set I2EN (enable I2C), and load I2SCLH and I2SCLLwith proper values.
2. Clear SI.
3. Set STA.
4. Wait until SI becomes one. I2STATshould be0x08
5. Clear STA
6. Write I2DAT=(address<<1); in order to send theslave address
7. Clear SI
8. Wait until SI becomes one. I2STATshould be 0x18. Set STOotherwise and abort
9. Write I2DAT with data byte
10. Clear SI
11. Wait until SI becomes one. I2STATshould be 0x28. Set STOotherwise and abort
12. Repeat from step #9 until all data bytes aretransmitted
13. Set STO
14. Clear SI
Master Receiver (read) procedure
1. Set I2EN (enable I2C), and load I2SCLH and I2SCLLwith proper values.
2. Clear SI.
3. Set STA.
4. Wait until SI becomes one. I2STATshould be0x08
5. Clear STA
6. Write I2DAT=(address<<1)+1; in order to send theslave address
7. Clear SI
8. Wait until SI becomes one. I2STATshould be 0x40. Set STOotherwise and abort
9. Set AA in order to acknowledge incomingbytes
10.Clear SI
11.Wait until SI becomes one. I2STATshould be 0x50. Set STOotherwise and abort
12. Read the received byte from I2DAT and store it
13.If just one byte is pendingclear AA
14.Repeat from step #10 until all data bytes arereceived
15. Set STO
16.Clear SI
Example

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