3.

2 Memory Modules
In this project, the microcontroller is interfaced with two memory modules. One for
storing the setting details, tariff details and balance amount s etc. and the second memory is
included in the smart card which holds the recharge amount. Once the smart card is detected, the
controller checks the memory for its validity, and if it’s a valid card the amount is read from the
memory location and adds and store into the built in memory’s balance amount location. Once
the amount is read from the smart card memory, the controller will erase the memory part and
make it invalid for further reusing.

The memory modules are built upon the serial eeprom chips AT24Cxx series, and
communicate with the controller with the help of I2C protocol. The AT24C01/02/04/08/16
provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-
only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device
is optimized for use in many industrial and commercial applications where low-power and low-
voltage operation are essential. The AT24C01/02/04/08/16 is available in space-saving 8-lead
PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23
(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed
via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.

3.2.1 Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K
devices may be addressed on a single bus system (device addressing is discussed in detail under
the Device Addressing section). The AT24C04 uses the A2 and A1 inputs for hard wire
addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is
a no connect and can be connected to ground. The AT24C08A only uses the A2 input for
hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The
A0 and A1 pins are no connects and can be connected to ground. The AT24C16A does not use
the device address pins, which limits the number of devices on a single bus to one. The A0, A1
and A2 pins are no connects and can be connected to ground.

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal Read/Write operations
when connected to ground (GND). When the Write Protect pin is connected to VCC, the write
protection feature is enabled.

Pin Name Function

A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
GND Ground
VCC Power Supply

3.2.3 Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods. Data changes
during SCL high periods will indicate a start or stop condition as defined below.
 Figure : Data validity

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command.

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After
a read sequence, the stop command will place the EEPROM in a standby power mode .

Figure : Start & Stop condition

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.

Figure : Acknowledge

STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

3.2.4 Device Addressing

The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation .The device address
word consists of a mandatory one, zero sequence for the first four most significant bits as shown.
This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device
address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hard-
wired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third
bit being a memory page address bit. The two device address bits must compare to their
corresponding hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the
A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must
compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K
does not use any device address bits but instead the 3 bits are used for memory page addressing.
These page addressing bits on the 4K, 8K and 16K devices should be considered the most
significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of
the device address, the EEPROM will output a zero. If a compare is not made, the chip will
return to a standby state.

Figure: Device Addressing

3.2.5 Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete.

Figure : Byte Write

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and
16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte
write, but the microcontroller does not send a stop condition after the first data word is clocked
in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will
respond with a zero after each data word received. The microcontroller must terminate the page
write sequence with a stop condition.

The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
incremented following the receipt of each data word. The higher data word address bits are not
incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same
page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the
EEPROM, the data word address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start
condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.

3.2.6 Read Operations

Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address stays
valid between operations as long as the chip power is maintained. The address “roll over” during
read is from the last byte of the last memory page to the first byte of the first page. The address
“roll over” during write is from the last byte of the current page to the first byte of the same
page. Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condition

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out
the data word. The microcontroller does not respond with a zero but does generate a following
stop condition.

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a
random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition.

Figure : Current Address Read

Figure : Random Read

Figure : Sequential Read

5.3 Memory chip Interfacing

The AT24C08 is a 1024 Byte I2C based serial eeprom memory, integrated in a 8 pin
PDIP package. The main pins for the I2C communication, SDA (serial data line) and SCL (Serial
Clock line) are connected to the microcontroller’s P2.0 and P2.1 respectively. To avoid the
issues due to the in bus capacitance, the SDA and SCL pins are pulled up to the VCC through the
10K resistors. The hardware addressing pins of the I2C memory chip, A0, A1 and A2 are
connected to the GND line, so that the hardware address will remain A0. The write protection
feature is disabled by connecting the WP pin to the GND. To avoid the transient nose influences
on the power supply, a .1uF bypass capacitor is connected near to the VCC pin.