2013 International Conference on Communication Systems and Network Technologies

Low Power VLSI Circuit Design with Efficient

HDL Coding
Bishwajeet Pandey, Manisha Pattanaik
VLSI Design Lab, Atal Bihari Vajpayee-Indian Institute of Information Technology, Gwalior
Gwalior, India
[email protected], [email protected]

Abstract— in this paper, four-bit unsigned up counter with an of Low Power design. Therefore, we use synthesis attributes to
asynchronous clear and a clock enable is designed in Xilinx ISE control the use of control signals at the signal or module level
14.2 and implemented on high performance Virtex-6 FPGA, for low power design. Or, we may use alternative coding
XC6VLX240T device, -1 speed grade, FFG1156 package and methods for low fanout CE to reduce dynamic power
ML605 board. User constraints file (ucf) and net list constraints
design (ncd) file are taken into consideration with XPower 14.2
consumption.
for power consumption analysis. We take two codes. Our first II. RELATED WORK
code maps the clock enable signal to LUTs then the power
consumption is 3.423 Watt. Our second code maps the clock Ref [1] focuses on the necessity of Intellectual Properties (IP)
enable signal to control ports then the power consumption is reuse to shorten the design time and the power consumption of
3.625 Watt. By changing mapping style, we reduce 6% power design. An efficient bus protocol for the core communication
reduction and also reduce number of LUT and D flip-flop used in between IP block is OCP. Open Core Protocol (OCP) defines
implementation leads to area efficient design. By efficiently the only non-proprietary, openly licensed, core centric
mapping, we reduce power consumption in multiple of power
protocol with high-performance, bus-independent interface
reduction with single statements. The experimental result shows
the power analysis of both HDL mapping code. between IP cores that reduces design time, design risk, and
manufacturing costs and promote IP core reusability for SOC
Keywords— Clock Enable, LUTs, VLSI, Dynamic Power, Leakage designs. In the paper[2], a new tool CHESS, is designed and
Power, Control Port, Native Generic Circuit, Low Power, Power developed for control and data-flow graph (CDFG) extraction
Analyser and the high level synthesis of low power designs from
behavioral level VHDL descriptions. The tool optimizes
I. INTRODUCTION latency, area and power during the different phases of
Energy efficient computing and similar green computing synthesis and provides several solutions to evaluate the trade-
accelerates the demands of low power VLSI circuit design. offs during design. Reference paper [3] provides a detailed
Peoples are ready to give secondary preferences to performance analysis of low power and high speed Look up
performance when power saving for durable battery life is Table (LUT) by using a circuit technique. In Ref [5] we got
required for mobile and portable application and human the idea of low power design that is applicable on available
obligation of environment friendly appliances. Counter is a virtex-6 FPGA.
fundamental digital circuit that performs counting and use as III. METHODOLOGY
sub circuit in implementation of VLSI circuit design. Low
power design is possible with HDL because mapping the Low fanout CE is necessary for low power design. There are
Clock Enable always affect the power consumption of ALU two methods for low fanout CEs. First to use synthesis
because it also changes the Primitive and Black Box usage of attributes to control the use of control signals at the signal or
native generic circuit (ngc) file. Here, mapping means module level for low power design. Second is coding
optimizing one line code from behavioral to data flow HDL (behavioral HDL or dataflow HDL) for low-fanout CE. In this
coding style. If we map the CE to LUTs (i.e. behavioral paper, we use coding in place of synthesized attribute to
coding) it uses 1 inverter, 2 Flip-Flops, 3 LUTs as per reduce power consumption.
technology schematic and power consumption is 3.625W as
calculated by Xilinx XPower 14.2. If we map the CE(i.e. A Map the clock enable to the control port
dataflow coding) to Control port then it uses 1 GND, 1 Flip- Verilog coding to map the clock enable to the control port of
Flop, 1 LUT as per technology schematic and power counter are as following:
consumption is 3.423W as calculated by XPower14.2. if (ce) tmp <= tmp + 1’b1;
Therefore, we see significant power reduction as compare to Its equivalent VHDL coding is:
quantity of work we done to optimize code. If (ce) Then tmp <= tmp + 1’b1; End If
A Statement of the problem: Indeed, it is behavioral architecture coding in term of VHDL.
For low power design, low fanout CE is necessary. Using B Map the clock enable to the LUTs
global switches to turn off every CEs don’t serve our purpose Coding to map the clock enable to the control port of counter
are as following:

978-0-7695-4958-3/13 $26.00 © 2013 IEEE 698

DOI 10.1109/CSNT.2013.149
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 tmp <= ((tmp + 1’b1)&ce) j (tmp&~ce);
It’s equivalent VHDL coding is:
If(ce) Then tmp <= ((tmp+’1’) and ce) or (tmp and (not ce));
End If . Indeed, it is dataflow architecture coding in term of
VHDL.

C. Environment provided during implementation

We take 1.000V Vccint, 50.0 C ambient temperature, 250
LFM airflow, 2 Speed Grade, Virtex-6 FPGA, ML605 Board,
Commercial Temperature Grade and Typical Process
Variation. The simulation tool is Xilinx ISE 14.2. The power Figure 2: RTL Schematic of Counter
analyzer tool is XPower 14.2; Default Activity Rate is as Xilinx software display a register-transfer-level schematic
following: representation of the Optimized design by ISE in terms of
FF Toggle Rate (%): 12.5, I/O Toggle Rate (%): 12.5, Output basic elementary symbols that are not related to the targeted
Load (pF): 5.0, I/O Enable Rate (%): 100.0, BRAM Write Xilinx device in form of adders, sub-tractor, multipliers,
Rate (%): 50.0, BRAM Enable Rate (%): 50.0, DSP Toggle counters, and logical gates.
Rate (%): 12.5 V. RESULTS
IV. LOW POWER COUNTER By changing one line statement in HDL coding, we reduce 6%
Counter is a basic circuit in digital design. It is used as a power reduction. By efficiently coding, we can reduce power
building component in many VLSI circuits. A 4-bit unsigned consumption in multiple of power reduction with single
up counter (shown in Figure.1) with an asynchronous clear statements.
and a clock enable is design.
A. Map the clock enable to the control port
Power Consumption if we map the CE to control port are as
following:
1) Clock Power Consumption=0.036 Watt
2) Signal Power Consumption=0.002 Watt
3) IOs Power Consumption=0.159 Watt
4) Leakage Power Consumption=0.428 Watt
5) Total Power Consumption=3.625 Watt

If map the CE to control port, Primitive and Black Box Usage

is as following:
1) It requires 4 basic elements (one Inverter, one LUT2, one
LUT3 and one LUT4).
2) It requires 4 D Flip-Flops with clock enable.
3) 1 Clock Buffer
4) 6 IO Buffers (two input buffer, 4 output buffer).

1) Technology Schematic of Counter in Case A:

Technology Schematic of counter saves with name of
counter.ngc. NGC is Native Generic Circuit File.
Figure 1: Four-Bit Unsigned Up Counter with an
Asynchronous Clear and Clock Enable

It requires 3 inputs clk, clr and ce and one four-bit output q.

We take temp as intermediate signal. When reset is high then
temp is set to”0000” otherwise temp will be incremented. It
can count 16 times when clock edge is rising.

A RTL Schematic of Counter

Xilinx Synthesis Technology generates RTL Schematic as
Counter.ngr. Madd_tmp are four registers and fdce are four D
flip-flop in this RTL schematic of counter.

Figure 3: Technology Schematic of Counter in Case A

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 It displays Primitive and Black Box Usage. This technology whereas in case B we are using one LUT, 1 D flip-flop. This
schematic has four basic elements (one Inverter, one LUT2, reduction in number of basic element in netlist translated to
one LUT2 and one LUT4), four D Flip-Flops with clock reduction in power consumption from 3.625W (in case A) to
enable, 1 Clock Buffer and six IO Buffers (2-input, 4-output). 3.483W (in case B).
All these elements contribute to leakage power 3.428 Watt at
VII. FUTURE SCOPE
1000MHz
From the current synthesis on 40-nm based Virtex-6 FPGA,
B Map the clock enable to the LUTs there is scope to synthesize this code on latest 28-nm FPGA
Power Consumption if we map the CE to LUTs is as like Virtex-7, Kintex-7, Stratix V and Artix-7 FPGA Devices
following: and verify the low power design efficiency on the latest FPGA
1) Clock Power Consumption=0.036 Watt of deeper sub micron level.
2) Signal Power Consumption=0.001 Watt
3) IOs Power Consumption=0.022 Watt ACKNOWLEDGMENT
4) Leakage Power Consumption=0.423 Watt We are grateful to our director Prof. S.G Deshmukh for his
5) Total Power Consumption=3.483 Watt motivation for research oriented works. Thanks and
appreciation to the helpful people at ABV-IIITM, and CDAC
If we map the CE to control port, Primitive and Black Box Noida for their support.
Usage is as following:
1) It requires two basic elements (one GND, one LUT2). REFERENCES
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we change the mapping of clock enable from control port to 24 Fabruary 2013. (In Press)
LUTs input. In case A, we are using three LUT, 4 D flip-flops

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