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Microprocessor: Memory Banking

The document discusses the concept of memory banking in the 8086 microprocessor. It has four memory locations that allow the 8086 to access two bytes of data from separate memory banks in a single clock cycle using its 16-bit data bus. It explains how the 8086 uses address lines and control signals to read from or write to the two memory banks.

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222 views

Microprocessor: Memory Banking

The document discusses the concept of memory banking in the 8086 microprocessor. It has four memory locations that allow the 8086 to access two bytes of data from separate memory banks in a single clock cycle using its 16-bit data bus. It explains how the 8086 uses address lines and control signals to read from or write to the two memory banks.

Uploaded by

221nicole0006
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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MICROPROCESSOR

Lecturer: Sejal M Chopra

Physical hardware organization of memory space (Memory Banking)


1. Concept of memory banking in 8086:
 Each memory location can store only one byte of data.
 But the data bus of 8086 processor has 16 data lines. In-order to utilize the data bus
optimally the processor should access two consecutive memory locations ie 2 bytes of
data in one cycle.
 However, if both these memory locations are in the same memory chip then they
cannot be accessed at the same time. This is because the address bus cannot carry
two addresses simultaneously.
 Thus the 8086 processor memory is divided into two banks where in each bank
provides 8-bit data.(Note: banking concept is not there in 8085 and 8088 processor as
their external data bus is 8 bits only)
 This concept is implemented by placing two consecutive locations on two memory
chips.
 Physically, memory is implemented as two independent 512Kbyte banks: the low
(even) bank and the high (odd) bank.
 Data bytes associated with an even address (00000H-FFFFEH) reside in the low bank,
and those with odd addresses (000001H-FFFFFH) reside in the high bank.
 Address bits A1 through A19 select the storage location that is to be accessed.These
are applied to both banks in parallel. A0 and bank high enable (BHE^) are used as
bank- select signals.
 Each of the memory banks provides half of the 8086's 16-bit data bus. The lower bank
transfers bytes of data over data lines D0 through D7, while data transfers for a high
bank use D8 through D15.
MICROPROCESSOR
Lecturer: Sejal M Chopra

2. How 8086 microprocessor accesses memory locations from both the banks?
 8086 uses BHE^ and A0 to select the banks in the following way:

BHE^ A0 Operation
0 0 R/W 16 bit from both the banks(Aligned or Misaligned word)
0 1 R/W 8 bit from higher bank(Odd address byte transfer)
1 0 R/W 8 bit from lower bank(Even address byte transfer)
1 1 No operation (idle)

• (a)Even address byte transfer by 8086:


Fig. (a) shows how a byte-memory operation is performed to address X,
an even-addressed storage location. A0 is set to logic 0 to enable the low bank of
memory and BHE to logic 1 to disable the high bank. Data are transferred to or
from the lower bank over data bus lines D0 through D7.

• (b)Odd address byte transfer by 8086:


Fig. (b) shows how a byte-memory operation is performed to an odd addressed
storage location such as X + 1. A0 is set to logic 1 and BHE to logic 0.
This enables the high bank of memory and disables the low bank. Data are
transferred over bus lines D8 through D15. D8 represents the LSB.
MICROPROCESSOR
Lecturer: Sejal M Chopra

•(c)Even address word transfer by 8086:


Fig. (c) illustrates how an aligned word (at even address X) is accessed.
Both the high and low banks are accessed at the same time. Both A0 and BHE
are set to 0. This 16-bit word is transferred over the complete data bus D0
through D15 in just one bus cycle.

• (d)Odd address word transfer by 8086:


Fig. (d) illustrates how a misaligned word (at address X + 1) is accessed.
Two bus cycles are needed. During the first bus cycle, the byte of the word
located at address X + 1 in the high bank is accessed over D8 through D15. Even
though the data transfer uses data lines D8 through D15, to the processor it is the
low byte of the addressed data word.
MICROPROCESSOR
Lecturer: Sejal M Chopra

In the second memory bus cycle, the even byte located at X + 2 in the low bank is accessed
over bus lines D0 through D7.

Viva Questions:
How to avoid an odd address word transfer in 8086?
To avoid this, a programmer should specify an even memory location in the instruction or an
“EVEN” assembler directive should be used which informs the assembler to align the lower
byte at even addresses.

Why is banking not supported by 8085 and 8088 processors?


8085 and 8088 processor has data bus of 8-bits only, so there is no need of memory banking.

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