COURSE: HDL PROGRAMMING

Course Code: 23EC3PLHDL

Radha R C, Dept.of ECE,BMSCE

 Typical Design Flow

Radha R C, Dept.of ECE,BMSCE

 Typical Design Flow
Design Specifications
• It is a high level representation of the system.

• The process includes performance, functionality,

and physical dimensions (size of the chip).

• The fabrication technology and design

techniques are also considered.

• The end results are specifications for the size,

cost, speed, power, and functionality of the VLSI
system.

Radha R C, Dept.of ECE,BMSCE

 Typical Design Flow
Behavioral Description

• The key idea is to specify behavior, in terms of input,

output and timing of each unit, without specifying
its internal structure.

• The main functional units and interconnections

between the units of the system are identified

• Ex:Multiplication:-Different methods to perform

multiplication
Radha R C, Dept.of ECE,BMSCE
 Typical Design Flow
RTL Description(HDL)
• The behavioral description is manually
converted to an RTL description
• Register-transfer level (RTL) is a design
abstraction which models a synchronous digital
circuit in terms of the flow of digital signals
(data) between hardware registers and the
logical operations performed on those signals.
• Ex: assign mux_out = (sel) ? din_1 : din_0;

Radha R C, Dept.of ECE,BMSCE

 Typical Design Flow
Functional Verification and Testing

• A test bench is an environment used to check the

correctness of the design

• If errors are present, corrections can be done.

Radha R C, Dept.of ECE,BMSCE

 Typical Design Flow
Logic Synthesis/Timing Verification

• Logic synthesis is the process of deriving a list

of physical components and their
interconnections-Gate level netlist

• Timing verification confirms that the fabricated

circuit will operate at a specified
speed(propagation delays)
Radha R C, Dept.of ECE,BMSCE
 Typical Design Flow
Floor planning/Automatic Place and Route
• The chip dimensions and area of the design is
defined.
• Power and clock planning
• Once the floor-planning is complete, IO ports and
cells need to be placed in the allotted rows.
• Connect the cells together and to the I/O pins by
routing the circuit nets.
• Fabrication
Radha R C, Dept.of ECE,BMSCE
 Typical Design Flow
Physical Layout/Layout verification-Physical
Design
• Layout is created by converting each logic
component into a geometric representation (specific
shapes in multiple layers)
• Connections between different components are also
expressed as geometric patterns typically lines in
multiple layers.

Radha R C, Dept.of ECE,BMSCE

 Importance of HDLs
Advantages of HDLs
▫ Designers can write their RTL description without
choosing a specific fabrication technology
▫ Logic synthesis tools can automatically convert the
design to any fabrication technology
▫ functional verification of the design can be done early
in the design cycle, at the RTL level.
▫ functional bug at a later time in the gate-level netlist or
physical layout is minimized
▫ Verilog HDL allows different levels of abstraction to be
mixed in the same model.
▫ Thus, a designer can define a hardware model in terms
of switches, gates, RTL, or behavioral code.
▫ All fabrication vendors provide Verilog HDL libraries
for post-logic synthesis simulation.
Radha R C, Dept.of ECE,BMSCE
 VHDL Vs Verilog HDL
▫ Market divided between Verilog & VHDL
🞄 VHDL mostly in Europe
🞄 Verilog dominant in US
▫ VHDL
🞄 language like ADA
🞄 Not all constructs are synthesizable
▫ Verilog:
🞄 Like C programming
🞄 Similar in syntax to C
🞄 Most constructs are synthesizable
🞄 Easy to learn, easy to use
🞄 Allows different levels of abstraction and mixing them
Radha R C, Dept.of ECE,BMSCE
 Emergence of Verilog HDLs
• 1983: Verilog language was developed by
Gateway Automation.
• 1989: Cadence Design System purchased
Gateway Automation.
• 1990: Open Verilog International formed.
• 1995: IEEE standard 1364 adopted.
• Logic synthesis emerged in the late 1980s
• The details of gates and their interconnections to
implement the circuit were automatically
extracted by logic synthesis tools
• Today, Verilog HDL is an accepted IEEE
standard

Radha R C, Dept.of ECE,BMSCE

 FOUR TYPES OF MODELING

• Behavioral Modeling

• Data Flow Modeling

• Gate level Modeling (Structural Modeling)

• Switch Level Modeling

Radha R C, Dept.of ECE,BMSCE

 EXAMPLE
• 2x1 Multiplexer

Radha R C, Dept.of ECE,BMSCE

 Behavioral Modeling
• This is the highest level of abstraction provided
by Verilog HDL.
• A module can be implemented in terms of the
desired design algorithm without concern for the
hardware implementation details.
• It specifies the circuit in terms of its expected
behavior.
• It is the closest to a natural language description
of the circuit functionality, but also the most
difficult to synthesize.
Radha R C, Dept.of ECE,BMSCE
 Behavioral Modeling

module mux(
input s, a, b,
output reg y
);
always@(a,b,s) //behavioral statement
if (s == 0)
y = a;
else
y = b;
endmodule
Radha R C, Dept.of ECE,BMSCE
 Data Flow modelling
• At this level, the module is designed by specifying
the data flow.
• Shows that how the data / signal flows from input to
ouput
• works on Concurrent Execution
• The modelling uses logical equations
module mux(
input s, a, b,
output y
);
assign y = ((~s & a) | (s & b));
endmodule
Radha R C, Dept.of ECE,BMSCE
 Gate Level(Structural) Modelling
• The module is implemented in terms of logic
gates and interconnections between these gates.
• A change in the value of any input signal of a
component activates the component. If two or
more components are activated concurrently,
they will perform their actions concurrently as
well.
• Since logic gate is most popular component,
Verilog has a predefined set of logic gates known
as primitives.
Radha R C, Dept.of ECE,BMSCE
 Gate Level(Structural) Modelling

module mux(
input s, a, b,
output y
);
wire sbar, o1, o2; //internal connections
not N1(sbar, s);
and A1(o1, a, sbar);
and A2(o2, b, s);
or O1( y, o1, o2);
endmodule
Radha R C, Dept.of ECE,BMSCE
 Switch Level Modelling

• A module can be implemented in terms of

transistors, switches, storage nodes, and the
interconnections between them.

• Design at this level requires knowledge of

switch-level implementation details.

Radha R C, Dept.of ECE,BMSCE

 TEST BENCH
• 2x1 Multiplexer

module mux_tb; //no ports declared

reg a, b, s; //inputs declared as register type
wire y; // output declared as wire
mux m1(a,b,s,y); //instantiate the mux module
initial // behavioral statement
begin
a=1; b=0; s=0;
#10 a=0; b=1; s=1;
#10 $finish;
end
endmodule

Radha R C, Dept.of ECE,BMSCE

 Design Methodologies
Two basic types of digital design methodologies:
• top-down design methodology
▫ The top-level block is defined and sub-blocks necessary to
build the top-level block are identified.
▫ sub-blocks are further subdivided up to leaf cells, which are
the cells that cannot further be divided.
• bottom-up design methodology
▫ In a bottom-up design methodology, the building blocks
that are available are identified.
▫ using these building blocks, bigger cells are built.
▫ These cells are then used for higher-level blocks until the
top-level block in the design is built

Radha R C, Dept.of ECE,BMSCE

 Top-Down Design
• Start design from overall description and end
design with smallest detail

– specification
– architecture
– logic design
– circuit design
– physical layout
• Verify at each level of abstraction

Radha R C, Dept.of ECE,BMSCE

 Top-down design methodology

Radha R C, Dept.of ECE,BMSCE

 Bottom-Up Design
Start with smallest detail and build up to
highest abstraction
– Design individual transistors
– Combine transistors into gates
– Defining our own cell library
• Schematic
• Symbol
• Layout
– Build larger circuits with our cell
libraries
Radha R C, Dept.of ECE,BMSCE
 Bottom-up Design Methodology

Radha R C, Dept.of ECE,BMSCE

 4-bit Ripple Carry Counter
• negative edge-triggered toggle flipflops (T_FF)
• T_FFs made from negative edge-triggered D-flipflops
(D_FF) and inverters

Radha R C, Dept.of ECE,BMSCE

Radha R C, Dept.of ECE,BMSCE
 • In a top-down design methodology,
▫ first the functionality of the ripple carry counter is
specified, which is the top-level block.
▫ Then, the counter with T_FFs is implemented.
▫ In the end, T_FFs are built from the D_FF and inverter
gate.
▫ Thus, bigger blocks are broken into smaller building sub-
blocks until it cannot be broken up further.
• In a bottom-up methodology,
▫ Small building blocks are combined to build bigger blocks
▫ D_FF is built from logic gates
▫ T_FF is built from d_ff and inverter,
▫ Finally the counter is built using T_FFs

Radha R C, Dept.of ECE,BMSCE

 Ripple carry counter module
module ripple_carry_counter(q, clk, reset);
output [3:0] q; //q is a vector of length 4bits.
input clk, reset;
//Four instances of the module T_FF are created.
//each instance is a copy of the module T_FF.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule

Radha R C, Dept.of ECE,BMSCE

 module T_FF
• Define the module T_FF.

▫ module T_FF(q, clk, reset);

▫ output q;
▫ input clk, reset;
▫ wire d;
▫ D_FF dff0(q, d, clk, reset); // Instantiate D_FF
▫ not n1(d, q);
▫ endmodule

Radha R C, Dept.of ECE,BMSCE

 module D_FF
module D_FF with asynchronous reset

module D_FF(q, d, clk, reset);

output q;
input d, clk, reset;
reg q; //memory-to store data
always @(posedge reset or negedge clk) //behavioral statement
if (reset) //asynchronous reset
q <= 1'b0; //non-blocking assignment
else
q <= d;
endmodule

Radha R C, Dept.of ECE,BMSCE

 module Stimulus
module stimulus;
reg clk;
reg reset;
wire [3:0] q;
ripple_carry_counter r1(q, clk, reset); // instantiate the
design block
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units

initial
begin
..contd…
Radha R C, Dept.of ECE,BMSCE
 module Stimulus contd..
…
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1; //at time 15+180 = 195ns
#10 reset = 1'b0; //at time 205 ns
#20 $finish;
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q); //Monitors q
endmodule

Radha R C, Dept.of ECE,BMSCE

Output of the Simulation
0 Output q = 0 120 Output q = 11
20 Output q = 1 130 Output q = 12
30 Output q = 2 140 Output q = 13
40 Output q = 3 150 Output q = 14
50 Output q = 4 160 Output q = 15
60 Output q = 5 170 Output q = 0
70 Output q = 6 180 Output q = 1
80 Output q = 7 190 Output q = 2
90 Output q = 8 195 Output q = 0
100 Output q = 9 210 Output q = 1
110 Output q = 10 220 Output q = 2
….

Radha R C, Dept.of ECE,BMSCE

 Output Waveforms

Radha R C, Dept.of ECE,BMSCE

 FOUR BIT ADDER

Radha R C, Dept.of ECE,BMSCE

 4 BIT ADDER MODULE
module four_bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries
//Instantiate the full adder
fulladder FA0 (S[0],C1,A[0],B[0],C0);
fulladder FA1 (S[1],C2,A[1],B[1],C1);
fulladder FA2 (S[2],C3,A[2],B[2],C2);
fulladder FA3 (S[3],C4,A[3],B[3],C3);
endmodule
Radha R C, Dept.of ECE,BMSCE
 FULL ADDER MODULE
module fulladder (S,C,x,y,z);
input x,y,z;
output S,C;
wire S1,D1,D2; /*Outputs of first XOR and two
AND gates */
//Instantiate the half adders
halfadder HA1(S1,D1,x,y);
halfadder HA2(S,D2,S1,z);
or g1(C,D2,D1);
endmodule

Radha R C, Dept.of ECE,BMSCE

 HALF ADDER
module halfadder (S,C,x,y);
input x, y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
Endmodule

Radha R C, Dept.of ECE,BMSCE

 Modules
• Verilog provides the concept of a module. A module
is the basic building block in Verilog.
• A module can be an element or a collection of lower-
level design blocks.
• Typically, elements are grouped into modules to
provide common functionality that is used at many
places in the design.
• A module provides the necessary functionality to
the higher-level block through its port interface
(inputs and outputs), but hides the internal
implementation.
• This allows the designer to modify module internals
without affecting the rest of the design.
Radha R C, Dept.of ECE,BMSCE
 In Verilog, a module is declared by the keyword module.
A corresponding keyword endmodule must appear at the
end of the module definition.
Each module must have a module_name,which is the
identifier for the module, and a module_terminal_list,
which describes the input and output terminals of the
module.
module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule
Radha R C, Dept.of ECE,BMSCE
 Instances
• A module provides a template from which you can create
actual objects.
• When a module is invoked, Verilog creates a unique
object from the template.
• Each object has its own name, variables, parameters,
and I/O interface.
• The process of creating objects from a module template
is called instantiation, and the objects are called
instances.
• In Example Parallel adder implementation the top-level
block creates four instances from the Fulladder (FA)
template.
• Each FA instantiates a HA and an OR gate.
• Each instance must be given a unique name.
Radha R C, Dept.of ECE,BMSCE
 • In Verilog, it is illegal to nest modules. One module
definition cannot contain another
• module definition within the module and endmodule
statements. Instead, a module
• definition can incorporate copies of other modules by
instantiating them.

Radha R C, Dept.of ECE,BMSCE

 Components of a Simulation:
• Once a design block is completed, it must be tested.
The functionality of the design block can be tested
by applying stimulus and checking results. such a
block is called as stimulus block.

• It is good practice to keep the stimulus and design

blocks separate.

• The stimulus block can be written in Verilog.

• The stimulus block is commonly called a test bench

Radha R C, Dept.of ECE,BMSCE
 Two styles of stimulus application are possible.
• In the first style, the stimulus block instantiates
the design block and directly drives the signals
in the design block
• The stimulus block becomes the top-level block
Stimulus Block Instantiates Design Block

Radha R C, Dept.of ECE,BMSCE

 • The second style of applying stimulus is to
instantiate both the stimulus and design blocks in a
top-level dummy module.
• The stimulus block interacts with the design block
only through the interface
Stimulus and Design Blocks Instantiated in a
Dummy Top-Level Module

Radha R C, Dept.of ECE,BMSCE

 TEST BENCH

Radha R C, Dept.of ECE,BMSCE

 TEST BENCH PROGRAM
module tb_4bitadder;
reg [3:0] ta, tb;
reg tc; //initialize test vector
wire [3:0] tsum,;
wire tcr;
four_bit_adder fa4 (.S(tsum), .C4(tcr),.A(ta), .B(tb), .CO(tc));
initial
begin
ta=4’b0000; tb=4’b0000; tc=1’b0;
#10 ta=4’b0100; tb=4’b0011; tc=1’b1;
#20 ta=4’b0011; tb=4’b0111; tc=1’b1;
#30 ta=4’b1000; tb=4’b0100; tc=1’b0;
#40 ta=4’b1101; tb=4’b1101; tc=1’b1;
//(or we can also write : #10 ta=4’d5; tb=4’d6; tc=1’d1;)
#10 $finish;
end
endmodule
Radha R C, Dept.of ECE,BMSCE
 Basic Concepts:
Lexical Conventions
• The basic lexical conventions used by Verilog HDL are similar to
those in the C programming language. Verilog contains a stream of
tokens such as comments, numbers, strings, identifiers, and
keywords.
• Verilog HDL is a case-sensitive language. All keywords are in
lowercase.
• Whitespace :
▫ Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the
whitespace.
▫ Whitespace is ignored by Verilog. But used with strings.
• Comments
▫ // This is a one-line comment
▫ /* This is a multiple line comment */
• Operators
▫ = ~ b; // ~ is a unary operator.
▫ a = b && c; // && is a binary operator.
▫ a = b ? c : d; // ?: is a ternary operator.

Radha R C, Dept.of ECE,BMSCE

 Number Specifications
Sized numbers
Sized numbers are represented as
<size> '<base format> <number>.
• <size> is written only in decimal and specifies the number of
bits in the number.
• base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary
('b or 'B) and octal ('o or 'O)
• 4'b1111 // This is a 4-bit binary number
• 12'habc // This is a 12-bit hexadecimal number
• 16'd255 // This is a 16-bit decimal number.

Radha R C, Dept.of ECE,BMSCE

 Number Specifications contd..
• Default – Decimal number
• Default number of bits - simulator- and machine-specific
(must be at least 32).

• 23456 // 32-bit decimal number by default

• 'hc3 // 32-bit hexadecimal number
• 'o21 // 32-bit octal number

• X- unknown
• Z- high impedance

• 12'b1111_0000_1010 // Underscore- for readability

• 4'b10?? // Equivalent of a 4'b10zz
Radha R C, Dept.of ECE,BMSCE
 Strings
• A string is a sequence of characters that are enclosed by
double quotes.
• restriction - it must be contained on a single line
• Strings are treated as a sequence of one-byte ASCII
values.

• "Hello Verilog World"

• "a / b"

• \n – newline
• \t - tab

Radha R C, Dept.of ECE,BMSCE

 Identifiers
• User defined names for modules, instances etc.
• Made up of alphanumeric characters, ( _ ), ( $ )
• Identifiers are case sensitive.
• Identifiers start with an alphabetic character or an
underscore.
• They cannot start with a digit or a $sign

• Mux$12 //valid
• _clk1 //valid

• 1x2_mux //invalid
• $reg1 //invalid

Radha R C, Dept.of ECE,BMSCE

 Data Types
Nets

• Nets represent connections between hardware elements.

• Nets are declared primarily with the keyword wire
• net is not a keyword but represents a class of data types
• It supports four values: 0,1,z,x
• The default value of a net is z.
• Nets have values that change continuously by the circuits that are
driving them.

Registers

• Registers represent data storage elements

• Like a variable that can hold a value
• Keyword reg
• It supports four values: 0,1,z,x
• The default value of a register is x.
• Registers store values until they are updated

Radha R C, Dept.of ECE,BMSCE

 Data Types contd..
• Vectors
• reg or wire datatype with multiple bit widths

• wire a; // scalar net variable, default

• wire [7:0] bus; // 8-bit bus (Little endian notation)
• reg [0:40] addr; // address 41 bits (Big endian notation)

• Vector Part Select

• bus [2:0]; //lsb 3 bits
• Bus = reg[31-:8]; //=> data[31:24]
• Bus = reg[24+:8]; //=> data[31:24]

Radha R C, Dept.of ECE,BMSCE

 Data Types contd..
• Integer
• Integers are declared by the keyword integer
• default width at least 32 bits.
• integers store values as signed quantities.
• Real
• Real number constants are declared with the keyword real
• decimal notation : 3.14
• Time
• used in Verilog to store simulation time.
• A time variable is declared with the keyword time
• sim_time = $time; // Save the current simulation time

Radha R C, Dept.of ECE,BMSCE

 Data Types contd..
Arrays
• Arrays are allowed in Verilog for reg, integer, time, real and vector
datatypes.
• Multi-dimensional arrays can also be declared

• reg [4:0] portid[0:7]; // Array of 8 portids; each portid is 5

bits wide

• A vector is a single element that is n-bits wide.

• Arrays are multiple elements that are 1-bit or n-bits wide.

Radha R C, Dept.of ECE,BMSCE

 Data Types contd..
Parameters:
• Verilog allows constants to be defined in a module by the
keyword parameter.
• Parameters cannot be used as variables.
Example:
• parameter port_id = 5; // Defines a constant port_id
• parameter cache_line_width = 256; // Constant defines width
of cache line

Radha R C, Dept.of ECE,BMSCE

 System Tasks
• Verilog provides standard system tasks for certain routine
operations.
• All system tasks appear in the form $<keyword>.
• Operations such as displaying on the screen, monitoring
• values of nets, stopping, and finishing are done by system tasks.

Displaying information
• $display -system task for displaying values of variables, strings or
expressions.
• $display(p1, p2, p3,....., pn);
▫ p1, p2, p3,..., pn can be quoted strings or variables or expressions
• %d-decimal, %b- binary, %s-string, %h-hex values
• $display("Bus value is %b", bus);
• A $display inserts a newline at the end of the string by default.
• A $display without any arguments produces a newline.
Radha R C, Dept.of ECE,BMSCE
 System Tasks contd..
Monitoring information
• $monitor - mechanism to monitor a signal when its value
changes
• $monitor(p1,p2,p3,....,pn);
▫ The parameters p1, p2, ... , pn can be variables, signal names, or
quoted strings
• Only one monitoring list can be active at a time

• $monitor($time, " Value of signals clock = %b, reset = %b",

clock,reset);

Radha R C, Dept.of ECE,BMSCE

 System Tasks contd..
Difference between monitor and display Statement:
• $monitor continuously monitors the values of the variables
or signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable
or signal changes.
• Unlike $display, $monitor needs to be invoked only once
• $display: display the values of the variables or signals
specified in the parameter list only at the time where the
display statement is invoked.

Radha R C, Dept.of ECE,BMSCE

 System Tasks contd..
Stopping and finishing in a simulation
• $stop - The task is provided to stop during a simulation.
• used whenever the user wants to suspend the simulation and
examine the values of signals in the design

• $finish- this task terminates the simulation.

initial
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end
Radha R C, Dept.of ECE,BMSCE
 Compiler Directives
• All compiler directives are defined by using the
`<keyword> construct.

• `define - used to define text macros in Verilog

▫ Verilog compiler substitutes the text of the macro wherever it
encounters a`<macro_name>.

• 'define WORD_SIZE 32

• `include - used to include entire contents of a Verilog source

file in another Verilog file during compilation.

• 'include header.v

Radha R C, Dept.of ECE,BMSCE

 MODULES & PORTS:
Components of a Verilog Module

Radha R C, Dept.of ECE,BMSCE

 Ports
• Ports provide the interface by which a module
can communicate with its environment.
• Ports are the input/output pins

• Port Declaration
• module fulladd4(sum, c_out, a, b, c_in);
• //Begin port declarations section
• output [3:0] sum;
• output c_out;
• input [3:0] a, b;
• input c_in;
• //all port declarations are implicitly declared as wire

Radha R C, Dept.of ECE,BMSCE

 Ports contd..
• module DFF(q, d, clk, reset);
• output q;
• reg q; // Output port q holds value; therefore it is
declared as reg.
• input d, clk, reset; //wires

• In the D-type flip flop we want the output to

hold on to its value until the next clock edge so it
has to be a register.
• input and inout ports cannot be declared as reg
• input ports should not store values but simply
reflect the changes in the external signals they
are connected to.
Radha R C, Dept.of ECE,BMSCE
 Ports contd..
• ANSI C Style Port Declaration Syntax
The port direction and data type of the signal can be included
module fulladd4(
output reg [3:0] sum,
output reg c_out,
input [3:0] a, b,
input c_in);

Radha R C, Dept.of ECE,BMSCE

 Port Connection Rules
• module fulladd4(sum, c_out, a, b, c_in); //Module
with a list of ports
• module Top; // No list of ports, top-level module in
simulation

Radha R C, Dept.of ECE,BMSCE

 Port Connection Rules contd..
• Internally, input ports must always be of the type net.
• Externally, the inputs can be connected to a variable which is
a reg or a net.
• Internally, outputs ports can be of the type reg or net.
• Externally, outputs must always be connected to a net. They
cannot be connected to a reg.

Radha R C, Dept.of ECE,BMSCE

 Port Connection Rules contd..
• Internal to the module Port Declaration
• module fulladd4(sum, c_out, a, b, c_in);
• //Begin port declarations section
• output [3:0] sum;
• output c_out;
• input [3:0] a, b;
• input c_in;
• //all port declarations are implicitly declared as wire

• External to the module Port Declaration

• module Top;
• //Declare connection variables
• reg [3:0]A,B;
• reg C_IN;
• wire [3:0] SUM;
• wire C_OUT;
Radha R C, Dept.of ECE,BMSCE
 Port Connection Rules contd..
Illegal Port Connection
• module Top;
• //Declare connection variables
• reg [3:0]A,B;
• reg C_IN;
• reg [3:0] SUM;
• wire C_OUT;
• fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
• //Illegal connection because output port sum in module
//fulladd4 is connected to a register variable SUM in module
//Top.

Radha R C, Dept.of ECE,BMSCE

 Connecting Ports to External Signals
Connecting by ordered list
• The signals to be connected must appear in the module
instantiation in the same order as the ports in the port
list in the module definition.
• module Top;
• //Declare connection variables
• reg [3:0]A,B;
• reg C_IN;
• wire [3:0] SUM;
• wire C_OUT;
• //Instantiate fulladd4, call it fa_ordered.
• //Signals are connected to ports in order (by position)
• fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
Radha R C, Dept.of ECE,BMSCE
 Connecting Ports to External Signals
• Connecting ports by name
• For large number of ports, remembering the order of the
ports is impractical and error-prone.
• We can connect the ports by name instead of position

• // Instantiate module fa_byname and connect signals to

ports by name
• fulladd4 fa_byname(.c_out(C_OUT), .sum(SUM),
.b(B), .c_in(C_IN), .a(A));

• Unconnected ports can be dropped

• fulladd4 fa_byname(.sum(SUM), .b(B),
.c_in(C_IN), .a(A));

Radha R C, Dept.of ECE,BMSCE