ICICDT 2018, Otranto, Italy Session A – Low Power

Evaluation of Compensation Techniques for CMOS

Operational Amplifier Design
Muhaned Zaidi Ian Grout Abu Khari A'ain
Dep. Electronic and Computer Dep. Electronic and Computer Institute of Integrated Engineering
Engineering Engineering Universiti Tun Hussein Onn Johor
University of Limerick University of Limerick [email protected]
Dep. Electrical Engineering [email protected]
Wasit University
[email protected]

Abstract—This paper presents and compares two CMOS (usually an output stage pole) to a higher frequency. This
(complementary metal oxide semiconductor) operational amplifier pole splitting increases the closed-loop stability of the op-
(op-amp) designs. Each op-amp is based on a two-stage rail-to- amp but at the cost of decreased speed [3]. Miller
rail output where the first stage is a differential input with folded compensation reduces the UGF as the Miller capacitance is
cascode and the second stage forms a class-AB amplifier. Each op- dominant. The UGF is given by:
amp design incorporates different compensation techniques. The
first op-amp uses negative Miller compensation around the first (1)
stage and conventional Miller compensation is used around the =
2 ( + )
second stage. The second op-amp also utilizes negative Miller
around the first stage, but with indirect Miller between the output
node of the second stage and cascode node of the first stage. The where gm is the transconductance of the input stage
purpose of this work was to evaluate the DC gain, unity gain transistor, CM is Miller capacitance and C’ is input
frequency (UGF) and phase margin (PM) achieved using the capacitance (parasitic capacitance). Note that the parasitic
different compensation techniques in simulation and test results capacitance also contributes to reducing the UGF.
from physical prototype devices using a 0.35 µm CMOS Therefore, the proposition is to use negative Miller
technology when operating on a single rail +2.5V and +1.8 V compensation around the first stage in order to reduce the
power supply. effect of the input capacitance and extend the UGF towards
a higher frequency (Fig.1). The last compensation technique
considered is indirect Miller compensation and is also based
Keywords—negative Miller, CMOS amplifier, indirect Miller, on Miller theory. However, the feedback capacitance is
Miller compensation, Rail-to-rail output. connected between the output node of the second stage and
the cascode node of the first stage. An advantage of indirect
I. INTRODUCTION
Miller compensation is to increase the speed of operation of
The op-amp is one of the circuit blocks used in analog the op-amp circuit with the use of less layout area. The op-
and mixed-signal CMOS integrated circuit (IC) designs. amps were designed for low-voltage, low-power operation
Op-amps typically require a high UGF and large DC gain, and the gm/ID technique [4] was employed in determing
with stable operation in closed-loop and are increasingly transistor sizing. The gm/ID technique was used to size the
operated at a low voltage power supply. To achieve transistors when operating in saturation and in weak,
sufficient performance, there must be a balance (trade-off) moderate or strong inversion.
between the different open-loop performance
characteristics. In this work, the two-stage CMOS op-amp
has been considered where the first stage provides a high
gain and high output impedance, whilst the second stage
exhibits a moderate gain.
In order to design a high DC gain op-amp, the folded
cascode topology is commonly used [1] with the differential
input stage. The overall DC gain of the two-stage op-amp is
created by the folded cascode DC gain and the DC gain of
the second stage (class-AB amplifier). A disadvantage of
this topology is that the bandwidth frequency is reduced
especially when op-amp design is operated at low-voltage
and low power. Improving the closed-loop stability Fig.1. Two-stage op-amp block diagram and compensation techniques
(negative Miller (CNM), indirect Miller (CIMC) and (dotted line)
characteristics of the op-amp (in particular phase margin conventional Miller (CM))
(PM)), Miller compensation is used by incorporating a
capacitor between the input and output nodes of the second This paper considers and evaluates two op-amp
stage. The aim of this is to move the position of the lowest topologies using compensation feedback paths that combine
frequency pole (typically an input stage pole) to lower conventional Miller, indirect Miller and negative Miller
frequencies, and to move the second higher frequency pole (Fig.2) and is structured as follows. The compensation

978-1-5386-2550-7/18/$31.00 ©2018 IEEE

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Paper A2 ICICDT 2018, Otranto, Italy
feedback paths are discussed in section II. The op-amp B. Indirect Miller compensation
differential input with folded cascode stage and class-AB A second type of compensation is indirect Miller (CIMC)
output stage are presented in section III. The proposed compensation (Fig. 2). The indirect Miller capacitance is
compensation schemes are analyzed and discussed used a capacitor connected between the output node (node
in Section IV. Finally, section V provides conclusions to the C) of the second stage and a cascode node (nodes A and B)
paper. of the folded cascode stage as given in [10]. The advantage
of this compensation is improved stability without creating
a positive zero. Since this zero is in the LHP (left hand
plane), it will add to the phase response and enhance the
speed of the op-amp [11]. Indirect Miller compensation uses
the same technique as Miller compensation. It moves the
position of the low frequency pole to a lower frequency and
the position of the high frequency pole to a higher
frequency, but using a lower value of compensation
capacitance (CIMC) and a lower value of second-stage
transconductance. This achieves a higher op-amp UGF with
lower power consumption and a smaller layout, as
compared to conventional Miller compensation [11, 12].
C. Negative Miller compensation
Fig.2. Two-stage op-amp schematic and compensation techniques
(negative Miller (CNM), indirect Miller (CIMC) and (dotted line) Negative Miller capacitance (CNM) is based on Miller
conventional Miller (CM)) theory. In Fig.1, the capacitances are connected between the
input node (IN+ and IN-) and the output of the first stage
II. STABILITY AND COMPENSATION TECHNIQUES (node D and E) (see Fig. 2). When negative Miller
compensation is applied in a circuit design, it has two clear
A. Conventional Miller compensation advantages. Firstly, is simply reduces or removes an
A two-stage CMOS op-amp is normally considered to undesired capacitance at the input node. Secondly, is that
have two poles [5]. The simplest compensation technique is when node capacitance is reduced or removed, the
to connect a capacitor across the high gain output stage as associated bandwidth of the circuit is increased. Negative
identified in [6]. The Miller compensation technique is used Miller compensation can be achieved by using a non-
to transfer the low-frequency pole (p1) towards the origin inverting amplifier as identified in [9]. The negative Miller
(towards a lower frequency) and the high-frequency pole effect is shown in Fig. 4, where A is the gain of the amplifier.
(p2) away from the origin (towards a higher frequency), With a gain greater than one (unity), the Miller effect
allowing a much higher bandwidth than that obtained by produces a negative value of capacitance at the input node
merely connecting the compensation capacitor from one of the amplification stage.
node to ground [7]. Miller compensation expresses that the
impedance viewed in parallel with a gain stage (op-amp
second stage) can be exhibited as an impedance tied from
the input of that gain stage to ground, and an impedance tied
from the output of the gain stage to ground [8], as shown in
Fig. 3. To present Miller compensation, the impedance is
purely capacitive that connects around an inverting
amplifier. The capacitance will show an effect on the input
and output. The input capacitance effect is (CMC,I) = CMC
(1+|A|). The output capacitance effect is closer to the
compensation capacitor (CMC) [9] and is given by (CMC,O)=
CMC (1+1/|A|). Therefore, compensation creates a return Fig. 4 (a) Non-inverting amplifier with negative Miller capacitor, and
path of the signal from the output to the input of the (b) Negative Miller equivalent circuit
amplifier typically through a feedback capacitance, but this
produces a positive zero is in the RHP (right hand plane) III. OP-AMP DESIGN
which will reduce speed of operation. A. Input stage
In the previous section, negative Miller compensation
was included around an input amplification stage (as shown
in Fig. 2). The input stage comprises of two transistors (M1
and M2) and IN- and IN+ are gates of the input stage
transistors at the inverting and non-inverting nodes,
respectively. The differential input transistor sizes were
identified using the gm/ID design technique in order to
enhance the UGF and DC gain as well as PM. In this work,
the weak and moderate inversion regions of transistor
operation were considered. The outputs of the input stage
Fig. 3 (a) Inverting amplifier with Miller capacitor and (b) Miller were connected to the folded cascode block. In order to
theory equivalent circuit achieve a high output voltage gain using CMOS technology,

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 ICICDT 2018, Otranto, Italy Session A – Low Power
a folded cascode circuit was used. The input differential on both +2.5 V and +1.8 V power supply levels. For +2.5 V
stage and the folded cascode are transistors M1-M18. power supply voltage operation, the DC gain of the op-amp
Transistor M3 is the tail current source. In addition, as the varies between 72.39 dB and 87.25 dB. The cut-off
differential-pair current is reduced, the PM of the amplifier frequency (-3 dB frequency) is between 0.525 kHz and
will increase [13]. 1.656 kHz. The phase margin (PM) varies between 31.32°
and 60.45° whilst the UGF varies between 1.288 MHz and
B. Output stage 343 MHz. Table II shows the simulation results for the
The conventional Miller and indirect Miller capacitors second op-amp design (indirect Miller with negative Miller
were designed into the second stage. The class-AB output compensation) operating on both power supply voltage
stage forms the second stage that was planned as a levels. At +2.5 V operation, the DC gain of the op-amp
feedforward class-AB control, achieved by operating varies between 52.40 dB and 85.49 dB, while the -3 dB is
transistors M20 and M26 biasing using two-phase signal between 0.577 kHz and 1.841 kHz. The PM varies between
currents. These signals come from the transistors M14 and 11.31° and 63.01° whilst the UGF varies between 1.961
M16. The voltages at the gates of the transistors M20 and MHz and 533.2 MHz. Fig. 5 shows the frequency response
M26 are required to be constant and this is achieved by (gain (top) and phase (bottom)).
using stacked diode connected transistors (M23-M24 and
Table I. Summary of the simulated open-loop frequency response for
M29-M30). M21 and M27 provide the floating current the first op-amp (Negative Miller and conventional Miller compensation)
source circuit, and these transistors are tied to the stacked-
diode with feed-forward class-AB control. Considering the Gain 3dB
+2.5 V
PM UGF Gain 3dB
+1.8 V
PM UGF
transistors in the output stage, feedforward class-AB control (dB) (kHz) (Deg.) (MHz) (dB) (kHz) (Deg) (kHz)
TM
and floating current source circuits are suitable for 79.70 1.656 55.34 18.12 76.67 32.65 64.07 224.0
WP 72.39 106.1 31.32 343.0 34.90 103.6 36.00 5,696
producing a compact and power efficient op-amp design WS 87.25 0.525 60.45 1.288 78.40 0.170 65.67 12.18
[14]. The class-AB amplification and floating current
source control circuits are used in the cascode circuit in Table II. Summary of the simulated open-loop frequency response for
the second op-amp (Negative Miller and indirect Miller compensation)
order to decrease the noise and offset [15]. In addition, the
offset and noise of the op-amp are mostly controlled by the +2.5 V +1.8 V
Gain 3dB PM UGF Gain 3dB PM UGF
input transistor stage and the folded cascode [16]. (dB) (kHz) (Deg.) (MHz) (dB) (kHz) (Deg) (kHz)
Moreover, the class-AB output stage is suitable for lowest TM 79.09 1.841 53.62 26.29 76.70 0.371 68.27 309.6
WP
supply voltage operation when the transistor voltages are 52.40 124.0 11.31 533.2 34.90 140.4 42.98 8,5.0
WS 85.49 0.577 63.01 1.961 78.94 0.176 71.40 17.91
equal to Vdd(min) = Vgs(M20) + Vgs(M26) + Vsat where Vsat
is the summation of the saturation voltages for M20 and
M26. If M20 and M26 are operated in the weak inversion
region, the Vdd(min) of the class-AB transistor stage is often
the value for the minimum op-amp power supply voltage.
The class-AB output stage therefore controls the lowest
possible power supply voltage that the op-amp circuit can
be designed to operate on [17].
IV. SIMULATION AND RESULTS COMPARISON
Fig. 2 shows the first and second op-amp circuits that
use conventional Miller/indirect Miller capacitances
merged with the negative Miller capacitances respectively.
The technique for creating the negative Miller capacitance Fig. 5. Simulated open-loop frequency response for +2.5 V and +1.8
is to connect a capacitor around the input transistor stage. V power supply voltage levels
CNM1 is connected between the negative input node (IN-)
and the output node of the input transistor stage, whilst CNM2 Physical op-amp prototypes were tested using a
is connected between the positive input transistor (IN+) and frequency response analyzer (Analog Arts model SF880)
the output node of the input transistor stage. These [18]. The closed-loop gain was measured by using inverting
capacitors must be matched values, as must be the op-amp circuit with a gain magnitude of 20 dB (gain of -
conventional Miller and indirect Miller capacitors. The op- 10).
amp design was created using the Austria Mikro Systems
(AMS) 0.35 µm CMOS technology and simulated utilising
the Cadence Spectre simulator with process variations
(typical model (TM), worst-case power (WP) and worst-
case speed (WS)). In addition, the design was simulated
with layout parasitic component extraction for both op-amp
designs, I/O and power supply pads. The threshold voltage
of both nMOS and pMOS transistors were 0.5 V and 0.7 V
respectively. For this fabrication process, the supply voltage
(Vdd) operation is typically +3.3 V, but in this work the Fig. 6. Op-amp inverting circuit (open loop)
power supply was reduced to +2.5 V and +1.8 V.
Table III shows the test results from the physical op-
Table I shows the simulation results of the first op-amp amps tested. The results show the op-amp performance in
design (conventional Miller with negative Miller open-loop circuit and closed-loop. With this
compensation) with different process models and operating

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Paper A2 ICICDT 2018, Otranto, Italy
implementation, for +2.5 V power supply operation, both Miller capacitor and negative Miller compensation. The
op-amps are not stable in closed-loop. However, the op- second op-amp was compensated using indirect Miller and
amps are closed-loop stable at +1.8 V operation. At +2.5 V negative Miller compensation. Simulation results were
power supply voltage, the input differential tail current has obtained using Cadence Spectre and showed that the second
increased. This increment has resulted in an increased UGF, op-amp design had a significant improvement in UGF and
but with a reduced margin of stability. For +1.8 V operation, PM. In addition, physical op-amp prototypes were tested
the UGF reduces, but the margin of stability has increased. and analyzed using the Analog Arts model SF880. These
Fig. 7 shows the frequency response for the first op-amp at also showed an improvement in the UGF and PM for the
+1.8 V operation identifying the open-loop gain (red) and second op-amp design.
closed-loop gain (green). Fig. 8 shows the frequency
response at +1.8 V for the second op-amp. ACKNOWLEDGEMENT
Table III. Summary of the physical op-amp prototype open- and The authors would like to thank the Iraqi Ministry of
closed-loop frequency response Higher Education and Scientific Research (MOHESR) for
funding this project.
Open-loop
Op- 2.5 V 1.8 V
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The first op-amp was compensated using conventional