INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

INDEX

SR.NO TOPIC PAGENO

1 DATA COPY / TRANSFER INSTRUCTIONS 2

2 FLAG TRANSFER INSTRUCTIONS: 5

3 6
ARITHMETIC INSTRUCTIONS:

4 LOGICAL INSTRUCTIONS: 10

5 BRANCH INSTRUCTIONS: 13

6 CONDITIONAL BRANCH 16
INSTRUCTIONS:

7 CONDITIONAL LOOP INSTRUCTIONS: 17

8 17
STRING MANIPULATION
INSTRUCTIONS:

9 FLAG MANIPULATION AND A 19

PROCESSOR CONTROL INSTRUCTIONS:

10 CONCLUSION 21

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

Instruction Set of 8086 Microprocessor

The 8086 instructions are categorized into the following main types.
i. Data Copy / Transfer Instructions
ii. Arithmetic and Logical Instructions
iii. Branch Instructions
iv. Loop Instructions
v. Machine Control Instructions
vi. Flag Manipulation Instructions
vii. Shift and Rotate Instructions
viii. String Instructions

DATA COPY / TRANSFER INSTRUCTIONS:

MOV:

This instruction copies a word or a byte of data from some source to a destination. The
destination can be a register or a memory location. The source can be a register, a
memory location, or an immediate number.

MOV AX,BX
MOV AX,5000H
MOV AX,[SI]
MOV AX,[2000H]
MOV AX,50H[BX]

MOV [734AH],BX
MOV DS,CX
MOV CL,[357AH]

PUSH: Push To Stack

This instruction pushes the contents of the specified register/memory location on to the
stack. The stack pointer is decremented by 2, after each execution of the instruction.

E.g. PUSH AX
• PUSH DS
• PUSH [5000H]

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

POP : Pop from Stack:

This instruction when executed, loads the specified register/memory location with the
contents of the memory location of which the address is formed using the current stack segment and
stack pointer.
The stack pointer is incremented by
2 Eg. POP AX
POP DS
POP [5000H]

XCHG : Exchange byte or word

This instruction exchange the contents of the specified source and destination operands
Eg. XCHG [5000H], AX
XCHG BX, AX

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

XLAT :
Translate byte using look-up table
Eg. LEA BX, TABLE1
MOV AL, 04H
XLAT

IN:
Copy a byte or word from specified port to accumulator.
Eg. IN AL,03H
IN AX,DX

OUT:
Copy a byte or word from accumulator specified port.
Eg. OUT 03H, AL
OUT DX, AX

LEA :
Load effective address of operand in specified register.
[reg] offset portion of address in DS
Eg. LEA reg, offset

LDS:
Load DS register and other specified register from memory.
[reg] [mem]
[DS] [mem + 2]
Eg. LDS reg, mem

LES:
Load ES register and other specified register from memory.
[reg] [mem] [ES] [mem + 2]
Eg. LES reg, mem

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

FLAG TRANSFER INSTRUCTIONS:

LAHF:
Load (copy to) AH with the low byte the flag register.
[AH] -----------[ Flags low byte]
Eg. LAHF

SAHF:
Store (copy) AH register to low byte of flag register.
[Flags low byte] [-------[AH]
Eg. SAHF

PUSHF:
Copy flag register to top of stack.
[SP]  [SP] – 2
[[SP]]  [Flags]
Eg. PUSHF

POPF :
Copy word at top of stack to flag register.
[Flags] [[SP]]
[SP] [SP] + 2

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

ARITHMETIC INSTRUCTIONS:
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication and
comparing two values.

ADD :
The add instruction adds the contents of the source operand to the destination, operand.
ADD AX, 0100H
ADD AX, BX
ADD AX, [SI]
ADD AX, [5000H]
ADD [5000H], 0100H
ADD 0100H

ADC : Add with Carry

This instruction performs the same operation as ADD instruction, but adds the carry flag to the result.
Eg ADC 01000H AX,
ADC BX,AX
ADC [SI], AX
ADC [5000H]
ADC [5000],[0100H]

SUB : Subtract
The subtract instruction subtracts the source operand from the destination operand and the result is left
in the destination operand.
Eg SUB AX, 0100H
SUB AX, BX
SUB AX, [5000H]
SUB [5000H], 0100H

SBB : Subtract with Borrow

The subtract with borrow instruction subtracts the source operand and the borrow flag (CF) which
may reflect the result of the previous calculations, from the destination operand .

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

Eg.
SBB AX, 0100H
SBB AX, BX
SBB AX, [5000H]

INC : Increment
This instruction increases the contents of the specified Register or memory location by 1. Immediate
data cannot be operand of this instruction.
Eg. INC AX INC [BX]
INC [5000H

DEC : Decrement
The decrement instruction subtracts 1 from the contents of the specified register or memory location.
Eg. DEC AX DEC
[5000H]

NEG : Negate
The negate instruction forms 2‟s complement of the specified destination in the instruction. The
destination can be a register or a memory location. This instruction can be implemented by inverting
each bit and adding 1 to it.
Eg. NEG AL
AL = 0011 0101 35H Replace number in AL with its 2‟s complement
AL = 1100 1011 = CBH

CMP : Compare
This instruction compares the source operand, which may be a register or an immediate data or a
memory location, with a destination operand that may be a 6 SBB AX, 0100H SBB AX, BX SBB AX,
[5000H] SBB [5000H], 0100H register or a memory location
Eg. CMP BX, 0100H
CMP AX, 0100H
CMP [5000H], 0100H
CMP BX, [SI]
CMP BX, C

MUL: :Unsigned Multiplication Byte or Word

This instruction multiplies an unsigned byte or word by the contents of AL.
Eg. MUL BH
MUL CX

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

MUL WORD PTR [SI]

IMUL :Signed Multiplication

This instruction multiplies a signed byte in source operand by a signed byte in AL or
a signed word in source operand by a signed word in AX.
Eg. IMUL BH
IMUL CX
IMUL [SI]

CBW : Convert Signed Byte to Word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said
to be sign extension of AL.
Eg. CBW
AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX.
Result in AX = 1111 1111 1001 1000

CWD : Convert Signed Word to Double Word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said
to be sign extension of AL.
Eg. CWD
Convert signed word in AX to signed double word in DX : AX
DX= 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

AAS : ASCII Adjust AL after Subtraction

This instruction corrects the result in AL register after subtracting two unpacked
ASCII operands. The result is in unpacked decimal format. The procedure is similar to
AAA instruction except for the subtraction of 06 from AL.

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

DAA : Decimal Adjust Accumulator

This instruction is used to convert the result of the addition of two packed BCD
numbers to a valid BCD number. The result has to be only in AL.
Eg. AL = 53CL = 29
ADD AL, CL ; AL (AL) + (CL)
; AL 53 + 29
; AL 7C
DAA ; AL 7C + 06 (as C>9)
; AL 82

DAS : Decimal Adjust after Subtraction

This instruction converts the result of the subtraction of two packed BCD numbers to
a valid BCD number. The subtraction has to be in AL only.
Eg. AL = 75, BH = 46
SUB AL, BH ; AL 2 F = (AL) - (BH)
; AF = 1
DAS ; AL 2 9 (as F>9, F - 6 = 9)

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

LOGICAL INSTRUCTIONS:
AND : Logical AND
This instruction bit by bit ANDs the source operand that may be an immediate
register or a memory location to the destination operand that may a register or a memory
location. The result is stored in the destination operand.
Eg. AND AX, 0008H
AND AX, BX
OR : Logical OR
This instruction bit by bit ORs the source operand that may be an immediate ,
register or a memory location to the destination operand that may a register or a memory
location. The result is stored in the destination operand.
Eg. OR AX, 0008H
OR AX, BX
NOT : Logical Invert
This instruction complements the contents of an operand register or a memory
location, bit by bit.
Eg. NOT AX
NOT [5000H]
XOR : Logical Exclusive OR
This instruction bit by bit XORs the source operand that may be an immediate ,
register or a memory location to the destination operand that may a register or a memory
location. The result is stored in the destination operand.
Eg. XOR AX, 0098H
XOR AX, BX

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

TEST : Logical Compare Instruction

The TEST instruction performs a bit by bit logical AND operation on the two
operands. The result of this ANDing operation is not available for further use, but flags
are affected.
Eg.TEST AX, BX
TEST [0500], 06H

SAL/SHL : SAL / SHL destination, count.

SAL and SHL are two mnemonics for the same instruction. This instruction shifts
each bit in the specified destination to the left and 0 is stored at LSB position. The MSB
is shifted into the carry flag. The destination can be a byte or a word

SHR : SHR destination, count

This instruction shifts each bit in the specified destination to the right and 0 is
stored at MSB position. The LSB is shifted into the carry flag. The destination can be a
byte or a word.
It can be a register or in a memory location. The number of shifts is indicated by
count.
Eg. SHR CX, 1
MOV CL, 05H
SHR AX, CL
SAR : SAR destination, count
This instruction shifts each bit in the specified destination some number of bit
positions to the right. As a bit is shifted out of the MSB position, a copy of the old MSB
is put in the MSB position. The LSB will be shifted into CF.
Eg. SAR BL, 1
MOV CL, 04H
SAR DX, CL

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

ROL Instruction : ROL destination, count

This instruction rotates all bits in a specified byte or word to the left some number
of bit positions. MSB is placed as a new LSB and a new CF.
Eg. ROL CX, 1
MOV CL, 03H
ROL BL, CL
ROR Instruction : ROR destination, count
This instruction rotates all bits in a specified byte or word to the right some
number of bit positions. LSB is placed as a new MSB and a new CF.
Eg. ROR CX, 1
MOV CL, 03H
ROR BL, CL

RCL Instruction : RCL destination, count

This instruction rotates all bits in a specified byte or word some number of bit
positions to the left along with the carry flag. MSB is placed as a new carry and previous
carry is place as new LSB.
Eg. RCL CX, 1
MOV CL, 04H
RCL AL, CL
RCR Instruction : RCR destination, count
This instruction rotates all bits in a specified byte or word some number of bit
positions to the right along with the carry flag. LSB is placed as a new carry and previous
carry is place as new MSB.
Eg. RCR CX, 1
MOV CL, 04H
RCR AL, CL

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

ROR Instruction : ROR destination, count

This instruction rotates all bits in a specified byte or word to the right some
number of bit positions. LSB is placed as a new MSB and a new CF.
Eg. ROR CX, 1
MOV CL, 03H
ROR BL, CL
RCL Instruction : RCL destination, count
This instruction rotates all bits in a specified byte or word some number of bit
positions to the left along with the carry flag. MSB is placed as a new carry and previous
carry is place as new LSB.
Eg. RCL CX, 1
MOV CL, 04H
RCL AL, CL
RCR Instruction : RCR destination, count
This instruction rotates all bits in a specified byte or word some number of bit
positions to the right along with the carry flag. LSB is placed as a new carry and previous
carry is place as new MSB.
Eg. RCR CX, 1
MOV CL, 04H
RCR AL, CL

BRANCH INSTRUCTIONS :
Branch Instructions transfers the flow of execution of the program to a new
address specified in the instruction directly or indirectly. When this type of instruction is
executed, the CS and IP registers get loaded with new values of CS and IP corresponding
to the location to be transferred.
The Branch Instructions are classified into two types
i. Unconditional Branch Instructions.
ii. Conditional Branch Instructions.

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

Unconditional Branch Instructions :

In Unconditional control transfer instructions, the execution control is transferred to the specified
location independent of any status or condition. The CS and IP are unconditionally modified to the
new CS and IP.

CALL : Unconditional Call

This instruction is used to call a Subroutine (Procedure) from a main program.
Address of procedure may be specified directly or indirectly.
There are two types of procedure depending upon whether it is available in the
same segment or in another segment.
i. Near CALL i.e., ±32K displacement.
ii. For CALL i.e., anywhere outside the segment.
On execution this instruction stores the incremented IP & CS onto the stack and
loads the CS & IP registers with segment and offset addresses of the procedure to be
called.

RET: Return from the Procedure.

At the end of the procedure, the RET instruction must be executed. When it is
executed, the previously stored content of IP and CS along with Flags are retrieved into
the CS, IP and Flag
registers from the stack and execution of the main program continues further

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

INT N: Interrupt Type N.

In the interrupt structure of 8086, 256 interrupts are defined corresponding to the
types from 00H to FFH. When INT N instruction is executed, the type byte N is
multiplied by 4 and the contents of IP and CS of the interrupt service routine will be
taken from memory block in 0000 segment.
INTO: Interrupt on Overflow
This instruction is executed, when the overflow flag OF is set. This is equivalent to a
Type 4 Interrupt instruction.
JMP: Unconditional Jump
This instruction unconditionally transfers the control of execution to the specified
address using an 8-bit or 16-bit displacement. No Flags are affected by this instruction.
IRET: Return from ISR
When it is executed, the values of IP, CS and Flags are retrieved from the stack
to continue the execution of the main program.
LOOP : LOOP Unconditionally
This instruction executes the part of the program from the Label or address
specified in the instruction upto the LOOP instruction CX number of times. At each
iteration, CX is decremented automatically and JUMP IF NOT ZERO structure.
Example: MOV CX, 0004H
MOV BX, 7526H
Label 1 MOV AX, CODE
OR BX, AX
LOOP Label 1

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

CONDITIONAL BRANCH INSTRUCTIONS:

When this instruction is executed, execution control is transferred to the address specified relatively in
the instruction, provided the condition implicit in the Opcode is satisfied. Otherwise execution
continues sequentially

JZ/JE Label
Transfer execution control to address „Label‟, if ZF=1.
JNZ/JNE Label
Transfer execution control to address „Label‟, if ZF=0
JS Label
Transfer execution control to address „Label‟, if SF=1.
JNS Label
Transfer execution control to address „Label‟, if SF=0.
JO Label
Transfer execution control to address „Label‟, if OF=1.
13
JNO Label
Transfer execution control to address „Label‟, if OF=0.
JNP Label
Transfer execution control to address „Label‟, if PF=0.
JP Label
Transfer execution control to address „Label‟, if PF=1.
JB Label
Transfer execution control to address „Label‟, if CF=1.
JNB Label
Transfer execution control to address „Label‟, if CF=0.
JCXZ Label
Transfer execution control to address „Label‟, if CX=0

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

CONDITIONAL LOOP INSTRUCTIONS:

LOOPZ / LOOPE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
LOOPNZ / LOOPENE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0

STRING MANIPULATION INSTRUCTIONS:

A series of data byte or word available in memory at consecutive locations, to be
referred as Byte String or Word String. A String of characters may be located in
consecutive memory locations, where each character may be represented by its ASCII
equivalent.
The 8086 supports a set of more powerful instructions for string manipulations for
referring to a string, two parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
The length of the string is usually stored as count in the CX register.The
incrementing or decrementing of the pointer, in string instructions, depends upon the
Direction Flag (DF) Status. If it is a Byte string operation, the index registers are updated
14
by one. On the other hand, if it is a word string operation, the index registers are updated
by two.
REP : Repeat Instruction Prefix
This instruction is used as a prefix to other instructions, the instruction to which
the REP prefix is provided, is executed repeatedly until the CX register becomes zero (at
each iteration CX is automatically decremented by one).
i. REPE / REPZ- repeat operation while equal / zero.
ii. REPNE / REPNZ - repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

MOVSB / MOVSW :Move String Byte or String Word

Suppose a string of bytes stored in a set of consecutive memory locations is to be
moved to another set of destination locations.The starting byte of source string is located
in the memory location whose address may be computed using SI (Source Index) and DS
(Data Segment) contents.
The starting address of the destination locations where this string has to be
relocated is given by DI (Destination Index) and ES (Extra Segment) contents.
CMPS : Compare String Byte or String Word
The CMPS instruction can be used to compare two strings of byte or words. The
length of the string must be stored in the register CX. If both the byte or word strings are
equal, zero Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter)
becomes zero or the condition specified by the REP Prefix is False.
SCAN : Scan String Byte or String Word
This instruction scans a string of bytes or words for an operand byte or word
specified in the register AL or AX. The String is pointed to by ES:DI register pair. The
length of the string s stored in CX. The DF controls the mode for scanning of the string.
Whenever a match to the specified operand, is found in the string, execution stops and the
zero Flag is set. If no match is found, the zero flag is reset.
LODS : Load String Byte or String Word
The LODS instruction loads the AL / AX register by the content of a string
pointed to by DS : SI register pair. The SI is modified automatically depending upon DF,
If it is a byte transfer (LODSB), the SI is modified by one and if it is a word transfer
(LODSW), the SI is modified by two. No other Flags are affected by this instruction.
15

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

STOS : Store String Byte or String Word

The STOS instruction Stores the AL / AX register contents to a location in the
string pointer by ES : DI register pair. The DI is modified accordingly, No Flags are
affected by this instruction.
The direction Flag controls the String instruction execution, The source index SI
and Destination Index DI are modified after each iteration automatically. If DF=1, then
the execution follows autodecrement mode, SI and DI are decremented automatically
after each iteration. If DF=0, then the execution follows autoincrement mode. In this
mode, SI and DI are incremented automatically after each iteration.

FLAG MANIPULATION AND A PROCESSOR CONTROL

INSTRUCTIONS:
These instructions control the functioning of the available hardware inside the
processor chip. These instructions are categorized into two types:
1. Flag Manipulation instructions.
2. Machine Control instructions.

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

Flag Manipulation instructions

The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
Machine Control instructions
The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix.

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 INSTRUCTION SET OF 8086 MICROPROCESSOR [ MIC ]

CONCLUSION:
We learn the instruction set of 8086 microprocessors like data transfer instruction, logical instruction,
arithmetic instruction and branching instruction. Addressing mode tells us what is the type of the
operand and the way they are accessed from the memory for execution of an instruction and how to
fetch particular instruction from the memory.

REFERENCE:
1. Microprocessor and Interfacing: Douglas Hall, Tata McGraw Hill.
2. Microcomputer Systems: 8086/8088 family Architecture, Programming and Design: Liu
& Gibson, PHI Publication

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