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1.6 Scaling Principles

The document discusses the syllabus for the EC18601-VLSI Design course including scaling principles and fundamental limits of CMOS VLSI design. It covers topics like MOS transistor characteristics, fabrication processes, CMOS inverter characteristics, scaling of device parameters, and limitations of scaling.

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23 views

1.6 Scaling Principles

The document discusses the syllabus for the EC18601-VLSI Design course including scaling principles and fundamental limits of CMOS VLSI design. It covers topics like MOS transistor characteristics, fabrication processes, CMOS inverter characteristics, scaling of device parameters, and limitations of scaling.

Uploaded by

sreemurarik756
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EC18601-VLSI Design

- Scaling principles and fundamental limits

CMOS VLSI Design 4th Ed. 1


UNIT I
MOS TRANSISTOR PRINCIPLE 9
NMOS, PMOS -Enhancement and depletion MOSFET; MOS
transistor-Ideal I-V characteristics; Fabrication Process - MOSFET,
CMOS- n-well, p-well, Twin tub, SOI; Scaling principles and
fundamental limits; CMOS inverter characteristics; Stick diagram;
Layout diagrams ; Design rules; Layer Representation

UNIT II
COMBINATIONAL LOGIC CIRCUITS 9
Static CMOS Design: Examples of Combinational Logic Design;
Complementary CMOS concept and properties; Ratioed Logic -
DCVSL logic gate; Pass Transistor Logic - Concept, Complementary
PTL and Differential PTL; CMOS transmission gate; Elmores
constant; Dynamic CMOS design: Dynamic Logic - Basic Principles;
Issues in Dynamic Design; Cascading Dynamic Gates
UNIT III
SEQUENTIAL LOGIC CIRCUITS 9
Timing Metrics for Sequential Circuits; Static Latches and Registers;
Bi-stability Principle; Multiplexer Based Latches; Master-Slave based
Edge Triggered Register; Non-ideal clock signals; Dynamic Latches
and Registers; Transmission-Gate Edge-triggered Registers; C2MOS
Register; Dual-Edge Registers; True Single-Phase Clocked Register
(TSPCR) Timing issues; Pipelines; Clock Strategies; Synchronous
and Asynchronous design- Low power design principles

UNIT IV
DESIGNING ARITHMETIC BUILDING BLOCKS 9
Data path circuits; Architectures for Ripple Carry Adders; Carry Look
Ahead Adders; Carry Select Adder; Carry Bypass Adder; High speed
adders - Brunt Kung adder, Kogge Stone; Multipliers - Wallace Tree
multiplier, Booth Multiplier; Barrel shifters; Speed and Area Trade-
off for all above Arithmetic Building Blocks
UNIT V
IMPLEMENTATION STRATEGIES 9
Full custom and Semi-custom design; Standard cell design and
cell libraries; FPGA building block architecture - FPGA
interconnect routing procedures; Design for Testability: Ad Hoc
Testing, Scan Design, BIST
TEXTBOOKS:
1. Jan M Rabaey, Anantha Chandrakasan, B. Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Second Edition,
Prentice Hall of India, 2003. (Unit-1 to Unit-4)

2. M.J. Smith, “Application Specific Integrated Circuits”, Addisson


Wesley, 1997 (Unit-5)

REFERENCES:
3. N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”,
Second Edition, Addision Wesley 1993 (Unit-1 to Unit-4)

4. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit


Design, Layout and Simulation”, Prentice Hall of India 2005

5. A.Pucknell, Kamran Eshraghian, “BASIC VLSI Design”, Third


Edition, Prentice Hall of India, 2007.
UNIT I MOS TRANSISTOR PRINCIPLE
Syllabus
- NMOS, PMOS, Enhancement and depletion
MOSFET
- MOS transistor-Ideal I-V characteristics
- Fabrication Process - MOSFET, CMOS
- n-well, p-well, Twin tub, SOI,
- CMOS inverter characteristics,
- Stick diagram, Layout diagrams,
- Scaling principles and fundamental limits

CMOS VLSI Design 4th Ed. 6


SCALING PRINCIPLES
Microelectronic technology may be characterized in terms
of several indicators or figure of merit. Commonly the
following are used.
➢ Minimum feature (aspect) size
➢ Number of gates on one chip
➢ Power dissipation
➢ Maximum operational frequency
➢ Die size
➢ Production cost.

Many of these figure of merit can be improved by


shrinking the dimensions of Transistors, interconnections
and by adjusting the doping levels, supply voltages.
SCALING PRINCIPLES
Two scaling factors 1/α and 1/β are used.

1/β is chosen as the scaling factor for supply voltage VDD


and gate oxide thickness D

1/α is used for all other dimensions, both vertical and


horizontal to the chip surface.

For the constant field scaling model and the constant


voltage scaling model β = α and β = 1 respectively are
applied.
SCALING PRINCIPLES
SCALING FACTORS FOR DEVICE PARAMETERS:

1. Gate Area (Ag) :


Ag =L.W
Where L and W are channel length and width respectively.
Both are scaled by 1 / α. Thus Ag is scaled by 1/α2 .

2. Gate Capacitance per unit Area (Co or Cox) :


Co = εox / D
Where εox is the permittivity of the gate oxide and
D is the gate oxide thickness which is scaled by 1/β.

Thus Co is scaled by 1/(1/ β) = β.


SCALING PRINCIPLES
SCALING FACTORS FOR DEVICE PARAMETERS:

3. Gate Capacitance (Cg):


Cg = Co L W
Thus Cg is scaled by β 1/α2 = β/ α2 .

4. Parasitic Capacitance (Cx):


Cx is proportional to Ax / d
Where d is the depletion width around source or drain which is
scaled by 1/α and Ax is the area of the depletion around
source or drain which is scaled by 1/α2 .
Thus Cx is scaled by (1/α2) . 1/(1/α) = 1/α .
SCALING PRINCIPLES
5. Carrier Density in Channel (Qon) :
Qon = CoVgs
Where Qon is the average charge per unit area in the channel
in the ON state. Co is scaled by β and Vgs is scaled by 1/ β , thus
Qon is scaled by 1.

6. Channel Resistance (Ron) :


Ron = L/W . 1/ Qonµ
Where µ is the mobility in the channel and is assumed
constant.
Thus Ron is scaled by (1/α )/(1/α) . 1 =1.
SCALING PRINCIPLES

7. Gate Delay (Td):


Td = Ron Cg

Thus Td is scaled by 1.β/α2 = β/ α2 .

8. Maximum Operating Frequency (fo):


fo = (W/L) . (µ CoVDD/Cg )
Cg = Co L W
Or fo is inversely proportional to delay Td Ron = L/W . 1/ Qonµ
Thus fo is scaled by 1/(β/α2) = α2/ β.
SCALING PRINCIPLES
9. Saturation Current (Idss) :
Idss = (Co µ/2).(W/L).(Vgs - Vt)2

Where both Vgs and Vt are scaled by 1/ β ,


then Idss is scaled by β (1/ β)2 = 1/ β .

10. Current Density (J) :


J = Idss /A
Where A is the cross sectional area of the channel in the
on state which is scaled by 1/α2 , so J is scaled by α2 / β .
SCALING PRINCIPLES
11. Switching Energy Per Gate (Eg):
Eg = Cg / 2 . (VDD)2
Thus Eg is scaled by β/α2 . 1/ β2 = 1/α2 β .

12. Power Dissipation Per Gate (Pg):


Pg = Pgs + Pgd
Pgs = (VDD)2 / Ron - the static component
Pgd = Eg fo - the dynamic component
Pgs = (VDD)2 / Ron is scaled by (1/ β2 )(1) = 1/ β2
Pgd = Eg fo is scaled by (1/α2 β)(α2/ β) = 1/ β2

Both Pgs and Pgd are scaled by 1/β 2;


So Pg is scaled by 1/β 2
SCALING PRINCIPLES

13. Power Dissipation Per Unit Area (Pa):


Pa = Pg / Ag

Where Pa is scaled by (1/β 2) / (1/α2 ) = α2 / β2 .

14.Power Speed Product (PT) :


PT = Pg Td

Where PT is scaled (1/β 2) . (β/ α2 ) = 1/α2β .


SCALING PRINCIPLES
LIMITATIONS OF SCALING:
1. Substrate doping scaling factors:
As the channel length of a MOS transistor is reduced, the
depletion region widths must also be scaled down to prevent
the S and D depletion regions from meeting.

2. Depletion Width:
Doping level of substrate is increased to reduce the depletion
width, but this also Increases the threshold voltage.

3. Limits of Miniaturization:
The minimum size of a transistor depends mainly on the
resolution of Photolithographic technology. The limit of feature
size is now at 0.3µm.
SCALING PRINCIPLES
4. Limits of interconnect and contact resistance:
➢ The width, thickness and spacing of interconnects are each
scaled by 1/α, cross section areas must scale by 1/α2 .
➢ For short distance interconnections the conductor is also
scaled by 1/α, so that Resistance is increased by α.
➢ For constant field scaling, current I is also scaled by 1/α so
that IR drop remains constant.

5. Limits due to sub threshold currents:


One of the major concerns in the scaling of devices is the effect
on sub threshold Current Isub which is directly proportional to
exp(Vgs-Vt)q/kT.
SCALING PRINCIPLES
6. Limits on logic levels and supply voltage due to noise:
Major advantages in the scaling of devices are smaller gate
delay time, that is, higher operating frequencies and lower
power dissipation.

7. Limits due to current density:


High purity aluminum is most widely used material for forming
interconnections In VLSI chips. However the scaling down of
dimensions also increases the current density in interconnects
by the same factor if constant field scaling is applied.

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