4Gb: x16 gDDR3 SDRAM Graphics Addendum

Features

gDDR3 SDRAM Graphics Addendum

MT41J256M16 – 32 Meg x 16 x 8 Banks

Features • Self refresh temperature (SRT)

• Automatic self refresh (ASR)
• VDD = V DDQ = +1.5V (1.425–1.575V) • Write leveling
• VDD = V DDQ = +1.35V (1.283–1.45V) capable at down • Multipurpose register
clocked speeds • Output driver calibration
• Differential bidirectional data strobe
• 8n-bit prefetch architecture Options Marking
• Differential clock inputs (CK, CK#) • Configuration
• 8 internal banks – 256 Meg x 16 256M16
• Nominal and dynamic on-die termination (ODT) • FBGA package (Pb-free) – x16
for data, strobe, and mask signals – 96-ball (7.5mm x 13.5mm) LY
• Programmable CAS READ latency (CL) • Timing – cycle time
• Posted CAS additive latency (AL): 0, CL - 1, CL - 2 – 1.0ns @ CL = 14 (gDDR3-2000) -091G
• Programmable CAS WRITE latency (CWL) • Operating temperature
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 – Commercial (0°C ≤ T C ≤ 115°C) None
(via the mode register set [MRS]) • Revision :N
• Selectable BC4 or BL8 on-the-fly (OTF) Note: 1. For complete device functionality and speci-
• Self refresh mode fications, refer to the standard 4Gb DDR3
• TC of 0°C to 115°C SDRAM data sheet found at www.mi-
– 64ms, 8192 cycle refresh at 0°C to 85°C cron.com. The information in this data
– 32ms at 85°C to 115°C sheet supersedes the standard data sheet.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
2200 1 15-15-15 13.65 13.65 13.65
2000 2 14-14-14 14 14 14
-091G
1800 2 13-13-13 14.3 14.3 14.3
1600 2 11-11-11 13.75 13.75 13.75

Notes: 1. Requires VDD = VDDQ = +1.5VNOM

2. VDD = VDDQ = +1.35VNOM capable

Table 2: Addressing

Parameter 256 Meg x 16

Configuration 32 Meg x 16 x 8 banks
Refresh count 8K
Row addressing 32K (A[14:0])
Bank addressing 8 (BA[2:0])
Column addressing 1K (A[9:0])

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Products and specifications discussed herein are subject to change by Micron without notice.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Features

Table 3: Part Number Cross Reference

Micron Part Number FBGA Code

MT41J256M16LY-091G:N D9SMP

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Ball Assignments

Ball Assignments
Figure 1: 96-Ball FBGA – x16 (Top View)

1 2 3 4 5 6 7 8 9

A
VDDQ DQ13 DQ15 DQ12 VDDQ VSS

B
VSSQ VDD VSS UDQS# DQ14 VSSQ

C
VDDQ DQ11 DQ9 UDQS DQ10 VDDQ

D
VSSQ VDDQ UDM DQ8 VSSQ VDD

E
VSS VSSQ DQ0 LDM VSSQ VDDQ

F
VDDQ DQ2 LDQS DQ1 DQ3 VSSQ

G
VSSQ DQ6 LDQS# VDD VSS VSSQ

H
VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ

J
NC VSS RAS# CK VSS NC

K
ODT VDD CAS# CK# VDD CKE

L
NC CS# WE# A10/AP ZQ NC

M
VSS BA0 BA2 NC VREFCA VSS

N
VDD A3 A0 A12/BC# BA1 VDD

P
VSS A5 A2 A1 A4 VSS

R
VDD A7 A9 A11 A6 VDD

T
VSS RESET# NC NC A8 VSS

Notes: 1. Ball descriptions are listed in the main 4Gb DDR3 data sheet.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS# is selectable between NF or TDQS# via MRS.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Package Dimensions

Package Dimensions

Figure 2: 96-Ball FBGA – x16 (LY)

0.155

Seating plane

A 0.12 A

1.8 CTR
Nonconductive
overmold

96X Ø0.47
Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on Ø0.42 (covered by SR)
SMD ball pads.
9 8 7 3 2 1

A
B
C
D
E
F
13.5 ±0.1 G
H
12 CTR J
K
L
M
N
P
R
0.8 TYP T

0.8 TYP 1.1 ±0.1

6.4 CTR 0.34 ±0.05

7.5 ±0.1
Note: 1. All dimensions are in millimeters.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Specifications

Electrical Specifications

Table 4: DC Electrical Characteristics and Operating Conditions

All voltages are referenced to VSS
Parameter/Condition Symbol Min Nom Max Unit Notes
Supply voltage VDD 1.425 1.5 1.575 V 1, 2, 3
I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2, 3
Supply voltage VDD 1.283 1.35 1.45 V 1, 2, 4
I/O supply voltage VDDQ 1.283 1.35 1.45 V 1, 2, 4

Notes: 1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. Valid with all speed bins.
4. Not for use with -093 speed bin.

Table 5: Input/Output Capacitance

Note 1 applies to the entire table
Capacitance gDDR3-1600 gDDR3-1800 gDDR3-2000 gDDR3-2200 Note
Parameters Symbol Min Max Min Max Min Max Min Max Unit s
CK and CK# CCK 0.8 1.4 0.8 1.3 0.8 1.3 0.8 1.3 pF
ΔC: CK to CK# CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF
Single-end I/O: DQ, DM CIO 1.5 2.3 1.5 2.2 1.5 2.1 1.5 2.1 pF 2
Differential I/O: DQS, DQS#, CIO 1.5 2.3 1.5 2.2 1.5 2.1 1.5 2.1 pF 3
TDQS, TDQS#
ΔC: DQS to DQS#, TDQS, CDDQS 0 0.15 0 0.15 0 0.15 0 0.15 pF 3
TDQS#
ΔC: DQ to DQS CDIO –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 pF 4
Inputs (CTRL, CMD, ADDR) CI 0.75 1.3 0.75 1.2 0.75 1.2 0.75 1.2 pF 5
ΔC: CTRL to CK CDI_CTRL –0.4 0.2 –0.4 0.2 –0.4 0.2 –0.4 0.2 pF 6
ΔC: CMD_ADDR to CK CDI_CMD_AD –0.4 0.4 –0.4 0.4 –0.4 0.4 –0.4 0.4 pF 7
DR
ZQ pin capacitance CZO – 3.0 – 3.0 – 3.0 – 3.0 pF
Reset pin capacitance CRE – 3.0 – 3.0 – 3.0 – 3.0 pF

Notes: 1. VDD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×
VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics – IDD Specifications

Electrical Characteristics – IDD Specifications

IDD values are for full operating range of voltage and temperature unless otherwise no-
ted.

Table 6: IDD Maximum Limits - Die Rev. N

Speed Bin
IDD gDDR3-1600 gDDR3-1800 gDDR3-2000 gDDR3-2200 Units Notes
IDD0 66 73 82 82 mA 1, 2
IDD1 87 91 96 96 mA 1, 2
IDD2P0 (slow) 18 18 18 18 mA 1, 2
IDD2P1 (fast) 32 35 43 43 mA 1, 2
IDD2Q 32 30 37 37 mA 1, 2
IDD2N 32 35 37 37 mA 1, 2
IDD2NT 42 45 49 49 mA 1, 2
IDD3P 38 41 44 44 mA 1, 2
IDD3N 47 49 52 52 mA 1, 2
IDD4R 235 252 285 285 mA 1, 2
IDD4W 171 190 200 200 mA 1, 2
IDD5B 235 242 250 250 mA 1, 2
IDD6 20 20 20 20 mA 1, 2, 3
IDD6ET 25 25 25 25 mA 2, 4
IDD7 243 274 305 305 mA 1, 2
IDD8 IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2

Notes: 1. TC = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase IDDx by up to an additional 2mA.
3. Restricted to TC (MAX) = 85°C.
4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.
5. The IDD values must be derated (increased) on IT-option devices when operated outside
of the range 0°C ≤ TC ≤ 85°C:
• When TC < 0°C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derat-
ed by 2%; and IDD6 and IDD7 must be derated by 7%.
• When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must
be derated by 2%; IDD2Px must be derated by 30%.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Speed Bin Tables

Speed Bin Tables

Table 7: gDDR3-1600 Speed Bins

gDDR3-1600 Speed Bin -125G

CL-tRCD-tRP 11-11-11
Parameter Symbol Min Max Unit Notes
ACTIVATE to internal READ or WRITE delay time tRCD 13.75 – ns
PRECHARGE command period tRP 13.75 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.75 – ns
ACTIVATE-to-PRECHARGE command period tRAS 35 9x tREF ns 1
CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 2
CWL = 6, 7, 8 tCK (AVG) Reserved ns 3
CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 2
CWL = 6, 7, 8 tCK (AVG) Reserved ns 3
CL = 7 CWL = 5 tCK (AVG) Reserved ns 3
CWL = 6 tCK (AVG) 1.875 <2.5 ns 2
CWL = 7, 8 tCK (AVG) Reserved ns 3
CL = 8 CWL = 5 tCK (AVG) Reserved ns 3
CWL = 6 tCK (AVG) 1.875 <2.5 ns 2
CWL = 7, 8 tCK (AVG) Reserved ns 3
CL = 9 CWL = 5, 6 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.5 <1.875 ns 2
CWL = 8 tCK (AVG) Reserved ns 3
CL = 10 CWL = 5, 6 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.5 <1.875 ns 2
CWL = 8 tCK (AVG) Reserved ns 3
CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 3
CWL = 8 tCK (AVG) 1.25 <1.5 ns 2
Supported CL settings 5, 6, 7, 8, 9, 10, 11 CK
Supported CWL settings 5, 6, 7, 8 CK

Notes: 1. tREFI depends on TOPER.

2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Speed Bin Tables

Table 8: gDDR3-1800 Speed Bins

gDDR3-1800 Speed Bin -107G

CL-tRCD-tRP 13-13-13
Parameter Symbol Min Max Unit Notes
ACTIVATE to internal READ or WRITE delay time tRCD 14.3 – ns
PRECHARGE command period tRP 14.3 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.91 – ns
ACTIVATE-to-PRECHARGE command period tRAS 35 9x tREFI ns 1
CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 2
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) 2.5 3.3 ns 2
CWL = 6 tCK (AVG) Reserved ns 3
CL = 8 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 3
CWL = 6 tCK (AVG) 1.875 <2.5 ns 2
CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.875 <2.5 ns 3
CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.5 <1.875 ns 2
CWL = 8 tCK (AVG) Reserved ns 3
CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 3
CWL = 8 tCK (AVG) 1.5 <1.875 ns 2
CWL = 9 tCK (AVG) Reserved ns 3
CL - 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) Reserved ns 3
CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) 1.1 <1.25 ns 2
Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13 CK
Supported CWL settings 5, 6, 7, 8, 9 CK

Notes: 1. tREFI depends on TOPER.

2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Speed Bin Tables

Table 9: gDDR3-2000 Speed Bins

gDDR3-2000 Speed Bin -093G

CL-tRCD-tRP 14-14-14
Parameter Symbol Min Max Unit Notes
ACTIVATE to internal READ or WRITE delay time tRCD 14 – ns
PRECHARGE command period tRP 14 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50 – ns
ACTIVATE-to-PRECHARGE command period tRAS 36 9x tREFI ns 1
CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 2
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 2
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) 2.5 3.3 ns 3
CWL = 6 tCK (AVG) Reserved ns 3
CL = 8 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 3
CWL = 6 tCK (AVG) 1.875 <2.5 ns 2
CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.875 <2.5 ns 3
CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.5 <1.875 ns 2
CWL = 8 tCK (AVG) Reserved ns 3
CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 3
CWL = 8 tCK (AVG) 1.5 <1.875 ns 3
CWL = 9 tCK (AVG) Reserved ns 3
CL - 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) Reserved ns 3
CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) 1.1 <1.25 ns 2
CL = 14 CWL = 5, 6, 7, 8, 9 tCK (AVG) 1 <1.1 ns 2
CWL = 10
Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13, 14 CK
Supported CWL settings 5, 6, 7, 8, 9, 10 CK

Notes: 1. tREFI depends on TOPER.

2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Speed Bin Tables

Table 10: gDDR3-2200 Speed Bins

gDDR3-2200 Speed Bin -091G

CL-tRCD-tRP 15-15-15
Parameter Symbol Min Max Unit Notes
ACTIVATE to internal READ or WRITE delay time tRCD 13.65 – ns
PRECHARGE command period tRP 13.65 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.13 – ns
ACTIVATE-to-PRECHARGE command period tRAS 33 9x tREFI ns 1
CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 2
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 2
CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 3
CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) 2.5 3.3 ns 2
CWL = 6 tCK (AVG) Reserved ns 3
CL = 8 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 3
CWL = 6 tCK (AVG) 1.875 <2.5 ns 2
CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.875 <2.5 ns 2
CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 3
CWL = 7 tCK (AVG) 1.5 <1.875 ns 2
CWL = 8 tCK (AVG) Reserved ns 3
CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 3
CWL = 8 tCK (AVG) 1.5 <1.875 ns 2
CWL = 9 tCK (AVG) Reserved ns 3
CL - 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) Reserved ns 3
CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 3
CWL = 9 tCK (AVG) 1.1 <1.25 ns 2
CL = 14 CWL = 5, 6, 7, 8, 9 tCK (AVG) 1 <1.1 ns 2
CWL = 10
CL=15 CWL = 5, 6, 7, 8, 9, 10 tCK (AVG) .091 <1 ns 2
CWL = 11
Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13, 14, CK
15
Supported CWL settings 5, 6, 7, 8, 9, 10, 11 CK

Notes: 1. tREFI depends on TOPER.

2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
Clock Timing
Clock period average: TC = 0°C to 85°C tCK (DLL_DIS) 8 7800 8 7800 ns 9, 42
DLL disable mode TC = >85°C to 115°C 8 3900 8 3900 ns 42
Clock period average: DLL enable mode tCK (AVG) See corresponding speed bin table for ns 10, 11
tCK

range allowed
High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 CK 12
Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 CK 12
Clock period jitter DLL locked tJIT –60 60 –60 60 ps 13
PER
DLL locking tJIT
PER,lck –50 50 –50 50 ps 13
Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITPER MIN; ps
MAX = tCK (AVG) MAX + tJITPER MAX
Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – tCK 14
(AVG)
Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – tCK 15
(AVG)
Cycle-to-cycle jitter DLL locked tJIT 120 120 ps 16
CC
DLL locking tJIT
CC,lck 100 100 ps 16
Cumulative error across 2 cycles tERR2 –88 88 –88 88 ps 17
PER
3 cycles tERR3 –105 105 –105 105 ps 17
PER
4 cycles tERR4 –117 117 –117 117 ps 17
PER
5 cycles tERR5 –126 126 –126 126 ps 17
PER
6 cycles tERR6 –133 133 –133 133 ps 17
PER
7 cycles tERR7 –139 139 –139 139 ps 17
PER
8 cycles tERR8 –145 145 –145 145 ps 17
PER
9 cycles tERR9 –150 150 –150 150 ps 17
PER
10 cycles tERR10 –154 154 –154 154 ps 17
PER
11 cycles tERR11 –158 158 –158 158 ps 17
PER
12 cycles tERR12 –161 161 –161 161 ps 17
PER
n = 13, 14 . . .49, 50 tERRnper tERRn t
PER MIN = (1 + 0.68in[n]) × JITPER ps 17
cycles MIN
tERRn
PER MAX = (1 + 0.68in[n]) ×
tJIT
PER MAX
DQ Input Timing
Data setup time to DQS, Base (specification) tDS – – – – ps 18, 19
DQS# VREF @ 1 V/ns (AC175) – – – – ps 19, 20

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
Data setup time to DQS, Base (specification) tDS – – 10 – ps 18, 19
DQS# VREF @ 1 V/ns (AC150) – – 160 – ps 19, 20
Data setup time to DQS, Base (specification)@ tDS 68 – – – ps 19, 20
DQS# 2 V/ns (AC135)
VREF @ 2 V/ns 135 – – – 19, 20
Data hold time from Base (specification) tDH 70 – 70 – ps 18, 19
DQS, DQS# VREF @ 1 V/ns (DC100) 120 – 120 – ps 19, 20
Minimum data pulse width tDIPW 320 – 320 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access tDQSQ – 85 – 85 ps
DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – tCK 21
(AVG)
DQ Low-Z time from CK, CK# tLZ (DQ) –390 195 –390 195 ps 22, 23
DQ High-Z time from CK, CK# tHZ (DQ) – 195 – 195 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising tDQSS –0.27 0.27 –0.27 0.27 CK 25
DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 CK
DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising tDSS 0.18 – 0.18 – CK 25
DQS, DQS# falling hold from CK, CK# rising tDSH 0.18 – 0.18 – CK 25
DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – CK
DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK# tDQSCK –195 195 –195 195 ps 23
DQS, DQS# rising to/from rising CK, CK# when tDQSCK 1 10 1 10 ns 26
DLL is disabled (DLL_DIS)
DQS, DQS# differential output high time tQSH 0.40 – 0.40 – CK 21
DQS, DQS# differential output low time tQSL 0.40 – 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) –390 195 –391 195 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2) tHZ (DQS) – 195 – 195 ps 22, 23
DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time tDLLK 512 – 512 – CK 28
CTRL, CMD, ADDR Base (specification) tIS – – 45 – ps 29, 30
setup to CK,CK# VREF @ 1 V/ns (AC175) – – 220 – ps 20, 30

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
CTRL, CMD, ADDR Base (specification) tIS – – 170 – ps 29, 30
setup to CK,CK# VREF @ 1 V/ns (AC150) – – 320 – ps 20, 30
CTRL, CMD, ADDR Base (specification) tIS 65 – – – ps
setup to CK,CK# VREF @ 1 V/ns (AC135) 200 – – – ps
CTRL, CMD, ADDR Base (specification) tIS 150 – – – ps
setup to CK,CK# VREF @ 1 V/ns (AC125) 275 – – – ps
CTRL, CMD, ADDR hold Base (specification) tIH 100 – 120 – ps 29, 30
from CK,CK# VREF @ 1 V/ns (DC100) 200 – 220 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width tIPW 620 – 560 – ps 41
ACTIVATE to internal READ or WRITE delay tRCD See corresponding speed bin table for ns 31
tRCD

PRECHARGE command period tRP See corresponding speed bin table for ns 31
tRP

ACTIVATE-to-PRECHARGE command period tRAS See corresponding speed bin table for ns 31, 32
tRAS

ACTIVATE-to-ACTIVATE command period tRC See corresponding speed bin table for ns 31
tRC

ACTIVATE-to-ACTIVATE tRRD MIN = greater of MIN = greater of CK 31

minimum command period 4CK or 7.5ns 4CK or 6ns
Four ACTIVATE tFAW 35 – 35 – ns 31
windows
Write recovery time tWR 15 N/A 15 N/A ns 31, 32,
33,34
Delay from start of internal WRITE transaction tWTR MIN = greater of 4CK or 7.5ns; MAX = CK 31, 34
to internal READ command N/A
READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = CK 31, 32
N/A
CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = N/A CK
Auto precharge write recovery + precharge tDAL MIN = WR + tRP/tCK (AVG); MAX = N/A CK
time
MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = N/A CK
MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = CK
N/A
MULTIPURPOSE REGISTER READ burst end to tMPRR MIN = 1CK; MAX = N/A CK
mode register set for multipurpose register exit
Calibration Timing
ZQCL command: Long POWER-UP and RE- tZQ 512 – 512 – CK
INIT
calibration time SET operation
Normal operation tZQ 256 – 256 – CK
OPER

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
ZQCS command: Short calibration time tZQCS 64 – 64 – CK
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; CK
MAX = N/A
Begin power supply ramp to power supplies tVDDPR MIN = N/A; MAX = 200 ms
stable
RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms
RESET# LOW to I/O and RTT High-Z tIOZ MIN = N/A; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH tRFC MIN = 260; MAX = 70,200 ns
command period
Maximum refresh TC ≤ 85°C – 64 (1X) ms 36
period TC > 85°C 32 (2X) ms 36
Maximum average TC ≤ 85°C tREFI 7.8 (64ms/8192) µs 36
periodic refresh TC > 85°C 3.9 (32ms/8192) µs 36
Self Refresh Timing
Exit self refresh to commands not requiring a tXS MIN = greater of 5CK or tRFC + 10ns; CK
locked DLL MAX = N/A
Exit self refresh to commands requiring a tXSDLL MIN = tDLLK (MIN); MAX = N/A CK 28
locked DLL
Minimum CKE low pulse width for self refresh tCKESR MIN = tCKE (MIN) + CK; MAX = N/A CK
entry to self refresh exit timing
Valid clocks after self refresh entry or power- tCKSRE MIN = greater of 5CK or 10ns; MAX = CK
down entry N/A
Valid clocks before self refresh exit, tCKSRX MIN = greater of 5CK or 10ns; MAX = CK
power-down exit, or reset exit N/A
Power-Down Timing
CKE MIN pulse width tCKE (MIN) Greater of 3CK or Greater of 3CK or CK
5.625ns 5ns
Command pass disable delay tCPDED MIN = 2; MIN = 1; CK
MAX = N/A MAX = N/A
Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 × tREFI CK
Begin power-down period prior to CKE regis- tANPD WL - 1CK CK
tered HIGH
Power-down entry period: ODT either synchro- PDE Greater of tANPD or tRFC - REFRESH CK
nous or asynchronous command to CKE LOW time
Power-down exit period: ODT either PDX tANPD + tXPDLL CK
synchronous or asynchronous
Power-Down Entry Minimum Timing

CCMTD-1005363231-10344
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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
ACTIVATE command to power-down entry tACTPDEN MIN = 2 MIN = 1 CK
PRECHARGE/PRECHARGE ALL command to tPRPDEN MIN = 2 MIN = 1 CK
power-down entry
REFRESH command to power-down entry tREFPDEN MIN = 2 MIN = 1 CK 37
MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK
READ/READ with auto precharge command to tRDPDEN MIN = RL + 4 + 1 CK
power-down entry
WRITE command to BL8 (OTF, MRS) tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK
power-down entry BC4OTF
BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK
WRITE with auto pre- BL8 (OTF, MRS) tWRAPDEN MIN = WL + 4 + WR + 1 CK
charge command to BC4OTF
power-down entry BC4MRS tWRAPDEN MIN = WL + 2 + WR + 1 CK
Power-Down Exit Timing
DLL on, any valid command, or DLL off to com- tXP MIN = greater of 3CK or 6ns; MAX = CK
mands not requiring locked DLL N/A
Precharge power-down with DLL off to com- tXPDLL MIN = greater of 10CK or 24ns; MAX = CK 28
mands requiring a locked DLL N/A
ODT Timing
RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38
RTT synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40
RTT turn-on from ODTL on reference tAON –195 195 –195 195 ps 23, 38
RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 CK 39, 40
Asynchronous RTT turn-on delay tAONPD MIN = 2; MAX = 8.5 ns 38
(power-down with DLL off)
Asynchronous RTT turn-off delay tAOFPD MIN = 2; MAX = 8.5 ns 40
(power-down with DLL off)
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = N/A CK
ODT HIGH time without WRITE command or ODTH4 MIN = 4; MAX = N/A CK
with WRITE command and BC4
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK
RTT(WR)-to-RTT,nom change skew - BC4 ODTLcnw4 4CK + ODTLoff CK
RTT(WR)-to-RTT,nom change skew - BL8 ODTLcnw8 6CK + ODTLoff CK
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge tWLMRD 40 – 40 – CK
DQS, DQS# delay tWLDQSEN 25 – 25 – CK

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
gDDR3-2000 gDDR3-2200
Parameter Symbol Min Max Min Max Unit Notes
Write leveling setup from rising CK, CK# cross- tWLS 140 – 140 – ps
ing to rising DQS, DQS# crossing
Write leveling hold from rising DQS, DQS# tWLH 140 – 140 – ps
crossing to rising CK, CK# crossing
Write leveling output delay tWLO 0 7.5 0 7.5 ns
Write leveling output error tWLOE 0 2 0 2 ns
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
Clock Timing
Clock period average: TC = 0°C to 85°C tCK (DLL_DIS) 8 7800 8 7800 ns 9, 42
DLL disable mode TC = >85°C to 115°C 8 3900 8 3900 ns 42
Clock period average: DLL enable mode tCK (AVG) See corresponding speed bin table for ns 10, 11
tCK

range allowed
High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 CK 12
Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 CK 12
Clock period jitter DLL locked tJIT –80 80 –70 70 ps 13
PER
DLL locking tJIT
PER,lck –70 70 –60 60 ps 13
Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITPER MIN; ps
MAX = tCK (AVG) MAX + tJITPER MAX
Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – tCK 14
(AVG)
Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – tCK 15
(AVG)
Cycle-to-cycle jitter DLL locked tJIT 160 140 ps 16
CC
DLL locking tJIT
CC,lck 140 120 ps 16

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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
Cumulative error across 2 cycles tERR2 –118 118 –103 103 ps 17
PER
3 cycles tERR3 –140 140 –122 122 ps 17
PER
4 cycles tERR4 –155 155 –136 136 ps 17
PER
5 cycles tERR5 –168 168 –147 147 ps 17
PER
6 cycles tERR6 –177 177 –155 155 ps 17
PER
7 cycles tERR7 –186 186 –163 163 ps 17
PER
8 cycles tERR8 –193 193 –169 169 ps 17
PER
9 cycles tERR9 –200 200 –175 175 ps 17
PER
10 cycles tERR10 –205 205 –180 180 ps 17
PER
11 cycles tERR11 –210 210 –184 184 ps 17
PER
12 cycles tERR12 –215 215 –188 188 ps 17
PER
n = 13, 14 . . .49, 50 tERRnper tERRn MIN = (1 + 0.68in[n]) × tJIT ps 17
PER PER
cycles MIN
tERRn
PER MAX = (1 + 0.68in[n]) ×
tJIT
PER MAX
DQ Input Timing
Data setup time to DQS, Base (specification) tDS – – – – ps 18, 19
DQS# VREF @ 1 V/ns (AC175) – – – – ps 19, 20
Data setup time to DQS, Base (specification) tDS 30 – 10 – ps 18, 19
DQS# VREF @ 1 V/ns (AC150) 180 – 160 – ps 19, 20
Data setup time to DQS, Base (specification)@ tDS – – – – ps 19, 20
DQS# 2 V/ns (AC135)
VREF @ 2 V/ns – – – – 19, 20
Data hold time from Base (specification) tDH 65 – 45 – ps 18, 19
DQS, DQS# VREF @ 1 V/ns (DC100) 165 – 145 – ps 19, 20
Minimum data pulse width tDIPW 400 – 360 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access tDQSQ – 125 – 100 ps
DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – tCK 21
(AVG)
DQ Low-Z time from CK, CK# tLZ (DQ) –500 250 –450 225 ps 22, 23
DQ High-Z time from CK, CK# tHZ (DQ) – 250 – 225 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising tDQSS –0.25 0.25 –0.27 0.27 CK 25
DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 CK
DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 – 0.18 – CK 25

CCMTD-1005363231-10344
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© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 – 0.18 – CK 25
DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – CK
DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK# tDQSCK –255 255 –225 225 ps 23
DQS, DQS# rising to/from rising CK, CK# when tDQSCK 1 10 1 10 ns 26
DLL is disabled (DLL_DIS)
DQS, DQS# differential output high time tQSH 0.40 – 0.40 – CK 21
DQS, DQS# differential output low time tQSL 0.40 – 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) –500 250 –450 225 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2) tHZ (DQS) – 250 – 225 ps 22, 23
DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time tDLLK 512 – 512 – CK 28
CTRL, CMD, ADDR Base (specification) tIS 65 – 45 – ps 29, 30
setup to CK,CK# VREF @ 1 V/ns (AC175) 240 – 220 – ps 20, 30
CTRL, CMD, ADDR Base (specification) tIS 190 – 170 – ps 29, 30
setup to CK,CK# VREF @ 1 V/ns (AC150) 340 – 320 – ps 20, 30
CTRL, CMD, ADDR Base (specification) tIS – – – – ps
setup to CK,CK# VREF @ 1 V/ns (AC135) – – – – ps
CTRL, CMD, ADDR Base (specification) tIS – – – – ps
setup to CK,CK# VREF @ 1 V/ns (AC125) – – – – ps
CTRL, CMD, ADDR hold Base (specification) tIH 140 – 120 – ps 29, 30
from CK,CK# VREF @ 1 V/ns (DC100) 240 – 220 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width tIPW 620 – 560 – ps 41
ACTIVATE to internal READ or WRITE delay tRCD See corresponding speed bin table for ns 31
tRCD

PRECHARGE command period tRP See corresponding speed bin table for ns 31
tRP

ACTIVATE-to-PRECHARGE command period tRAS See corresponding speed bin table for ns 31, 32
tRAS

ACTIVATE-to-ACTIVATE command period tRC See corresponding speed bin table for ns 31
tRC

ACTIVATE-to-ACTIVATE tRRD MIN = greater of MIN = greater of CK 31

minimum command period 4CK or 7.5ns 4CK or 7.5ns
Four ACTIVATE tFAW 45 – 40 – ns 31
windows

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© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
Write recovery time tWR 15 N/A 15 N/A ns 31, 32,
33
Delay from start of internal WRITE transaction tWTR MIN = greater of 4CK or 7.5ns; MAX = CK 31, 34
to internal READ command N/A
READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = CK 31, 32
N/A
CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = N/A CK
Auto precharge write recovery + precharge tDAL MIN = WR + tRP/tCK (AVG); MAX = N/A CK
time
MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = N/A CK
MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = CK
N/A
MULTIPURPOSE REGISTER READ burst end to tMPRR MIN = 1CK; MAX = N/A CK
mode register set for multipurpose register exit
Calibration Timing
ZQCL command: Long POWER-UP and RE- tZQ 512 – 512 – CK
INIT
calibration time SET operation
Normal operation tZQ 256 – 256 – CK
OPER
ZQCS command: Short calibration time tZQCS 64 – 64 – CK
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; CK
MAX = N/A
Begin power supply ramp to power supplies tVDDPR MIN = N/A; MAX = 200 ms
stable
RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms
RESET# LOW to I/O and RTT High-Z tIOZ MIN = N/A; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH tRFC MIN = 260; MAX = 70,200 ns
command period
Maximum refresh TC ≤ 85°C – 64 (1X) ms 36
period TC > 85°C 32 (2X) ms 36
Maximum average TC ≤ 85°C tREFI 7.8 (64ms/8192) µs 36
periodic refresh TC > 85°C 3.9 (32ms/8192) µs 36
Self Refresh Timing
Exit self refresh to commands not requiring a tXS MIN = greater of 5CK or tRFC + 10ns; CK
locked DLL MAX = N/A
Exit self refresh to commands requiring a tXSDLL MIN = tDLLK (MIN); MAX = N/A CK 28
locked DLL

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© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
Minimum CKE low pulse width for self refresh tCKESR MIN = tCKE (MIN) + CK; MAX = N/A CK
entry to self refresh exit timing
Valid clocks after self refresh entry or power- tCKSRE MIN = greater of 5CK or 10ns; MAX = CK
down entry N/A
Valid clocks before self refresh exit, tCKSRX MIN = greater of 5CK or 10ns; MAX = CK
power-down exit, or reset exit N/A
Power-Down Timing
CKE MIN pulse width tCKE (MIN) Greater of 3CK or Greater of 3CK or CK
5.625ns 5ns
Command pass disable delay tCPDED MIN = 1; CK
MAX = N/A
Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 × tREFI CK
Begin power-down period prior to CKE regis- tANPD WL - 1CK CK
tered HIGH
Power-down entry period: ODT either synchro- PDE Greater of tANPD or tRFC - REFRESH CK
nous or asynchronous command to CKE LOW time
Power-down exit period: ODT either PDX tANPD + tXPDLL CK
synchronous or asynchronous
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK
PRECHARGE/PRECHARGE ALL command to tPRPDEN MIN = 1 CK
power-down entry
REFRESH command to power-down entry tREFPDEN MIN = 1 CK 37
MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK
READ/READ with auto precharge command to tRDPDEN MIN = RL + 4 + 1 CK
power-down entry
WRITE command to BL8 (OTF, MRS) tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK
power-down entry BC4OTF
BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK
WRITE with auto pre- BL8 (OTF, MRS) tWRAPDEN MIN = WL + 4 + WR + 1 CK
charge command to BC4OTF
power-down entry BC4MRS tWRAPDEN MIN = WL + 2 + WR + 1 CK
Power-Down Exit Timing
DLL on, any valid command, or DLL off to com- tXP MIN = greater of 3CK or 6ns; MAX = CK
mands not requiring locked DLL N/A
Precharge power-down with DLL off to com- tXPDLL MIN = greater of 10CK or 24ns; MAX = CK 28
mands requiring a locked DLL N/A
ODT Timing
RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38

CCMTD-1005363231-10344
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© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3-1600 gDDR3-1800
Parameter Symbol Min Max Min Max Unit Notes
RTT synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40
RTT turn-on from ODTL on reference tAON –250 250 –225 225 ps 23, 38
RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 CK 39, 40
Asynchronous RTT turn-on delay tAONPD MIN = 2; MAX = 8.5 ns 38
(power-down with DLL off)
Asynchronous RTT turn-off delay tAOFPD MIN = 2; MAX = 8.5 ns 40
(power-down with DLL off)
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = N/A CK
ODT HIGH time without WRITE command or ODTH4 MIN = 4; MAX = N/A CK
with WRITE command and BC4
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK
RTT(WR)-to-RTT,nom change skew - BC4 ODTLcnw4 4CK + ODTLoff CK
RTT(WR)-to-RTT,nom change skew - BL8 ODTLcnw8 6CK + ODTLoff CK
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge tWLMRD 40 – 40 – CK
DQS, DQS# delay tWLDQSEN 25 – 25 – CK
Write leveling setup from rising CK, CK# cross- tWLS 195 – 165 – ps
ing to rising DQS, DQS# crossing
Write leveling hold from rising DQS, DQS# tWLH 195 – 165 – ps
crossing to rising CK, CK# crossing
Write leveling output delay tWLO 0 9 0 7.5 ns
Write leveling output error tWLOE 0 2 0 2 ns

Notes: 1. Parameters are applicable with 0°C ≤ TC ≤ 115°C and VDD/VDDQ = 1.5V ±0.075V.
2. All voltages are referenced to VSS.
3. Output timings are only valid for RON34 output buffer selection.
4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environ-
ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points, and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).
6. All timings that use time-based values (ns, µs, ms) should use tCK (AVG) to determine the
correct number of clocks (this table uses CK or tCK [AVG] interchangeably). In the case of
noninteger results, all minimum limits are to be rounded up to the nearest whole inte-
ger, and all maximum limits are to be rounded down to the nearest whole integer.

CCMTD-1005363231-10344
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 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

7. Strobe or DQS diff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals.
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con-
secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
13. The period jitter (tJITPER) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
ing edge to the following rising edge.
16. The cycle-to-cycle jitter tJITCC is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error tERRnPER, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-
rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK
(MIN), tLZ(DQS) MIN, tLZ(DQ) MIN, and tAON (MIN). The following parameters are re-
quired to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ
(DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by
subtracting tJITPER (MAX), while tRPRE (MAX) is derated by subtracting tJITPER (MIN).
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-
spective clock signal (CK, CK#) crossing. The specification values are not affected by the

CCMTD-1005363231-10344
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© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions

amount of clock jitter applied because these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are READ (and RDAP) and synchronous ODT com-
mands. In addition, after any change of latency tXPDLL, timing must be met.
29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM
[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
ple, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifi-
cations are met. This means that for DDR3-800 6-6-6, of which tRP = 15ns, the device will
support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-
ternal PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
• For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
36. The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an aver-
age refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When TC is greater than 85°C, the refresh period is 32ms.
37. Although CKE is allowed to be registered LOW after a REFRESH command when
tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)

is required.
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on.
39. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when
input clock jitter is present. This results in each parameter becoming larger. The parame-
ters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR t t t
10PER (MAX) and JITDTY (MAX). The parameters ADC (MAX) and AOF (MAX) are re-
t t
quired to be derated by subtracting both ERR10PER (MAX) and JITDTY (MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z.
41. Pulse width of an input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by an AUTO PRECHARGE command.

CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Command and Address Setup, Hold, and Derating

Command and Address Setup, Hold, and Derating

The total tIS (setup time) and tIH (hold time) required is calculated by adding the data
sheet tIS (base) and tIH (base) values to the ΔtIS and ΔtIH derating values, respectively.
Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input signal
has to remain above/below V IH(AC)/VIL(AC) for some time tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach
VIH(AC)/VIL(AC).
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and
the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew
rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derat-
ing value. If the actual signal is later than the nominal slew rate line anywhere between
the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal
from the AC level to the DC level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and
the first crossing of V REF(DC). If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derat-
ing value. If the actual signal is earlier than the nominal slew rate line anywhere be-
tween the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual sig-
nal from the DC level to the V REF(DC) level is used for derating value.

Table 12: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based

Symbol gDDR3-1600 gDDR3-1800 gDDR3-2000 gDDR3-2200 Unit Reference

tIS (base) AC175 65 45 – – ps VIH(AC)/VIL(AC)
tIS (base) AC150 190 170 – – ps VIH(AC)/VIL(AC)
tIS (base) AC135 – – 65 65 ps VIH(AC)/VIL(AC)
tIS (base) AC125 – – 150 150 ps VIH(AC)/VIL(AC)
tIH (base) DC100 140 120 100 100 ps VIH(DC)/VIL(DC)

CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
 4Gb: x16 gDDR3 SDRAM Graphics Addendum
Data Setup, Hold, and Derating

Data Setup, Hold, and Derating

The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values to the ΔtDS and ΔtDH derating values, respec-
tively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the in-
put signal has to remain above/below V IH(AC)/VIL(AC) for some time tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC)) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC).
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC)
and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere be-
tween the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual sig-
nal from the AC level to the DC level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min
and the first crossing of V REF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere
between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual
signal from the DC-to-VREF(DC) region is used for derating value.

Table 13: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based

Symbol gDDR3-1600 gDDR3-1800 gDDR3-2000 gDDR3-2200 Unit Reference

tDS (base) AC175 – – – – ps VIH(AC)/VIL(AC)
tDS (base) AC150 30 10 – – ps VIH(AC)/VIL(AC)
tDS (base) AC135 60 40 68 68 ps VIH(AC)/VIL(AC)
tDH (base) DC100 65 45 70 70 ps VIH(DC)/VIL(DC)

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Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.