Memory

Systems
CH7 Overview of
DRAMs
Prof. Ren-Shuo Liu
Outline
• DRAM basic
• Organization
• Commands
• Transactions
• Timing

2
DRAM
• A small printed circuit board (PCB) that has a
handful of chips attached to it
• Usually an external device

3
DRAM Basics
• Storage cell is dynamic because each cell must be
periodically refreshed to retain the information

4
DRAM Basics
• ×N DRAM
• Each bank contains N arrays
• The part contains N data pins
• N arrays each reads 1 data bit in unison
• The part sends out N bits of data each time the memory
controller makes a column read request

5
 Common DRAM System Organization
• Channel, DIMM, rank, & bank

Row dec.
8 chips in a rank work in lockstep Bank #0

Col. dec.
8 banks

Rank #1
DIMM
Rank #0
8 8
Data bus
(Address and command
buses are omitted) 64 Channel #0 Channel #1
64

Memory Controller 6
 Simplified View
• Channel, DIMM, rank, & bank

Row dec.
8 devices in a rank work in lockstep Logical Bank #0

Col. dec.
8 banks

Rank #1

Rank #0

(Address and command

buses are omitted) 64 Channel #0 Channel #1
64

Memory Controller 7
Bank-Level Parallelism
• Each bank is independent in that, with only a few
restrictions, it can be operated at the same time
that other banks are being operated
• The use of multiple independent banks of memory
ahs been a common practice in computer design
since DRAMs were invented
• Interleaving multiple memory banks has been a
popular method used to achieve high-bandwidth
memory busses using low-bandwidth devices

8
DIMM, Ranks, Banks, and Arrays

Each rank is a set of DRAM devices that operate in unison

9
Address, Command, Data, & Chip
Select

• Data bus: typically 64 bits

• Address bus: grows with the physical storage on a
DRAM device
• Chip select: every rank has one chip select
10
11
Key DRAM Command
• Data-related
• ACTIVATE
• READ
• WRITE
• PRECHARGE
• REFRESH

• Power-related
• POWER UP
• POWER DOWN

12
ACTIVATE Command

• “The ACTIVATE
command is used to 8 KB row

Row dec.
Bank #0
open (or activate) a
row in a particular Col. dec.
bank for a 64 8 banks
subsequent access” Activate:
Bank and row
addresses

13
READ Command

• “The READ command

is used to initiate a 64B line

Row dec.
Bank #0
burst read access to
an active row” Col. dec.
64 8 banks
Read:
Col address
Burst:
64bits x 8 transfers

14
WRITE Command

• “The WRITE command

is used to initiate a 64B line

Row dec.
Bank #0
burst write access to
an active row” Col. dec.
64 8 banks
Write:
Col address
Burst:
64bits x 8 transfers

15
PRECHARGE Command
• “The PRECHARGE
command is used to

Row dec.
de-activate the open Bank #0
row in a particular
bank or in all banks” Col. dec.
• 64 8 banks
Precharge:
• Functionalities Bank address
• Make the bank(s)
ready for activating
another row
• Reduce power
consumption by the
bank(s)

16
READ/WRITE with Auto PRECHARGE
• READ/WRITE commands have an option feature:
auto precharge
• “If auto PRECHARGE is selected, the row being
accessed will be PRECHARGE at the end of the
READ/WRITE burst”

17
REFRESH Command
• “The REFRESH command
is used during normal

Row dec.
operation of the DRAM” Bank #0

• “This command must be Col. dec.

issued each time a refresh 64 8 banks
is required” Refresh
• Refresh is issued to DRAM controller
per 7.8 us
• Refresh ensures data in Refresh
the refreshed rows are
reliable

18
DRAM Accessing Transactions

• Basic transaction
• Activate  Read  Recharge
• Activate  Write  Recharge

• Auto precharge
• Activate  ReadAuto Precharge
• Activate  WriteAuto Precharge

19
Combined Transactions
• Row hit
• Once a row is activated, 64B line

Row dec.
the row can be read or Bank #0
written multiple times
without a need of the Col. dec.
precharge and activation 64 8 banks
commands

ACT Read PRE ACT Read PRE

time

ACT Read Read PRE

time 20
Combined Transactions
• Parallelized transactions
• One can activate multiple

Row dec.
rows residing in different
banks Bank #0
• This overlaps DRAM
accessing transactions Col. dec.
• One can keep multiple rows 8 banks
activated 64
• Improve row-hit rate
• One can operate different
banks almost
independently

ACT Read PRE

ACT Read PRE
time 21
DRAM Timing

22
DRAM Timing
• Minimum time interval between commands are specified by
DRAM vendors, e.g.,
• ACTIVE  READ
• READ  WRITE
• READ  PRECHARGE
• … (about 15 of them)

• Controller/scheduler needs to respect the timing strictly

• DRAM chips are totally slave and are not responsible for checking
the timing
• Violation can result in data corruption

23
DRAM Timing List
• Key timing parameters
Name Description
tRRD Row activation to Row activation Delay. The minimum time
interval between two row activation commands to the same
DRAM device. Limits peak current profile.
tRCD Row to Column command Delay. The time interval between row
access and data ready at sense amplifiers.
tFAW Four (row) bank Activation Window. A rolling time-frame in
which a maximum of four-bank activation can be engaged.
Limits peak current profile in DDR2 and DDR3 devices with more
than 4 banks.
tCAS Column Access Strobe latency. The time interval between
column access command and the start of data return by the
DRAM device(s).
tCCD Column-to-Column Delay. The minimum column command
timing. 24
DRAM Timing List (cont’d)
Name Description
tCWD Column Write Delay. The time interval between issuance of the
column-write command and placement of data on the data bus
by the DRAM controller.
tWTR Write To Read delay time. The minimum time interval between
the end of a write data burst and the start of a column-read
command. Allows I/O gating to overdrive sense amplifiers
before read command starts.
tRAS Row Access Strobe. The time interval between row access
command and data restoration in a DRAM array. A DRAM bank
cannot be precharged until at least tRAS time after the previous
bank activation.
tRTP Read to Precharge. The time interval between a read and a
precharge command.
tRP Row Precharge. The time interval that it takes for a DRAM array
to be precharged for another row access.
25
DRAM Timing List (cont’d)
Name Description
tWR Write Recovery time. The minimum time interval between the
end of a write data burst and the start of a precharge command.
Allows sense amplifiers to restore data to cells.
tRTRS Rank-to-rank switching time. Used in DDR and DDR2 SDRAM
memory systems; not used in SDRAM or Direct RDRAM memory
systems. One full cycle in DDR SDRAM.
tDATA_ Data burst duration. The time period that data burst occupies
TRANS on the data bus. Also referred to as tBL.

26
ACTIVATE

tRRD Row activation to Row activation Delay. The minimum time interval
between two row activation commands to the same DRAM device. Limits
peak current profile.
tRCD Row to Column command Delay. The time interval between row access
and data ready at sense amplifiers.
27
ACTIVATE

tFAW Four (row) bank Activation Window. A rolling time-frame in which a

maximum of four-bank activation can be engaged. Limits peak current
profile in DDR2 and DDR3 devices with more than 4 banks.

28
READ

tCAS

tCAS Column Access Strobe latency. The time interval between column access
command and the start of data return by the DRAM device(s). Also known
as tCL.

29
Consecutive READs

tCAS
tCAS

tCCD Column-to-Column Delay. The minimum column command timing.

30
WRITE

tCWD

tCWD Column Write Delay. The time interval between issuance of the column-
write command and placement of data on the data bus by the DRAM
controller.

31
Consecutive WRITEs

tCWD
tCWD

32
READ to WRITE

tCAS + tBL + tRTRS - tCWD

tCAS tCWD
tBL tRTRS

33
WRITE to READ

tCWD

tWTR Write To Read delay time. The minimum time interval between the end of
a write data burst and the start of a column-read command. Allows I/O
gating to overdrive sense amplifiers
before read command starts.

34
READ to PRECHARGE

tRAS Row Access Strobe. The time interval between row access command and
data restoration in a DRAM array. A DRAM bank cannot be precharged
until at least tRAS time after the previous
bank activation.
tRTP Read to Precharge. The time interval between a read and a precharge
command.
tRP Row Precharge. The time interval that it takes for a DRAM array to be
precharged for another row access. 35
WRITE to PRECHARGER

tCWD

tWR Write Recovery time. The minimum time interval between the end of a
write data burst and the start of a precharge command. Allows sense
amplifiers to restore data to cells.

36
DRAM Protocol Table
Commands Rank Bank
ACT s s tRAS + tRP
ACT s d tRRD (* maximum of four ACTs in a tFAW period)
ACT RD s s tRCD
WR s s tRCD
PRE s s tRAS
RD s a tCCD
RD d a tBL + tRTRS
RD
WR a a tCAS + tBL + tRTRS - tCWD
PRE s s tRTP

ACT=ACTIVATION; PRE=PRECHARGE; REF=REFRESH; RD=READ; WR=WRITE;

s=same; d=different; a=any 37
DRAM Protocol Table (cont’d)
Commands Rank Bank
RD s a tCWD + tBL + tWTR
RD d a tCWD + tBL + tRTRS - tCAS
WR WR s a tCCD
WR d a tBL + tRTRS
PRE s s tCWD + tBL + tWR
ACT s d tRP
PRE
RF s a tRP
ACT s s tRFC
RF
RF s a tRFC

ACT=ACTIVATION; PRE=PRECHARGE; RF=REFRESH; RD=READ; WR=WRITE;

s=same; d=different; a=any 38
Quick Summary
• DRAM organization
• Channel
• DIMM
• Rank
• Chip
• Bank
• Array
• DRAM command
• Activation
• Read
• Write
• Precharge
• Refresh
• DRAM transaction
• Activation  Read  Precharge
• Activation  Write  Precharge
• DRAM timing 39