1420 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO.

4, APRIL 2020

ReRAM: History, Status, and Future

Yangyin Chen , Member, IEEE
(Invited Paper)

Abstract — This article reviews the resistive

random-access memory (ReRAM) technology initialization
back in the 1960s and its heavily focused research and
development from the early 2000s. This review goes
through various oxygen/oxygen vacancy and metal-ion-
based ReRAM devices and their operation mechanisms.
This review also benchmarks the performance of various
oxygen/oxygen vacancy and metal-ion-based ReRAM
devices with general trend drawn. Being a semiconductor
memory and storage technology, the commercialization
attempts for both stand-alone mass storage/storage-class
memory and embedded nonvolatile memory are also Fig. 1. General category of resistive switching memory technologies
reviewed. Looking toward the coming era, the potential with ReRAM highlighted as the review focus.
of using ReRAM technology to improve machine learning
efficiency is discussed.
reported back in the early 1960s [1]–[4]. With that said,
Index Terms — Conductive bridge ReRAM (CBRAM), fila-
the history of the ReRAM device is as long as that of the
ment, machine learning, NAND, nonvolatile memory (NVM),
OxRAM, ReRAM, storage-class memory (SCM), self-rectify metal–oxide–semiconductor field-effect transistor (MOSFET)
cell, storage. (1960) [5], [6], and longer than both dynamic random access
I. I NTRODUCTION memory (DRAM) (1966) [7] and floating gate (FG) memory
(1967) [8]. However, the research on the resistive switch-

R ESISTIVE random-access memory (ReRAM), as a resis-

tive switching memory, covers a broad range of memory
and storage types of semiconductor devices. Generally speak-
ing phenomena in a dielectric material did not point to a
clear application at that time. More importantly, the main-
stream storage technology from the 1950s till the early 2000s
ing, resistive switching memory includes any devices with is either magnetic based (tapes, hard drives, etc.) or light
resistance change under external stress. For the technology based (CD, DVD, etc.). Therefore, the study of ionic switch-
that is reviewed in this article, the focus is on the insulator- ing in a solid-state device is largely confined to academic
based material stacks with defect-based nature as switching exploration.
species. Fig. 1 highlights the review focus among the various
resistive memory devices. The defects used as switching B. From the 2000s
media are either generated from the insulating layer internally
(i.e., oxygen vacancy in oxide dielectrics by electrical soft The explosion of portable electronic devices, particularly
breakdown) or introduced from the electrode layer externally smartphones, drives the demand of NAND flash memory as
(i.e., Cu ions into electrolytes by electrical stress). storage media from the mid-2000s. With the aggressive scaling
Using defects in a memory device is not unusual. For of 2-D NAND flash memory [9], what would be the technology
example, 3-D NAND flash memory uses SiN as a charge trap to extend the semiconductor storage scaling toward even
layer for electrons. However, moving defects back and forth, higher density, even faster speed, and even lower cost was put
as in ReRAM, is still unique. The defect-based nature brings onto the discussion among industry and academy. ReRAM
ReRAM lots of unique properties for memory application. as one of the proposals to continue the scaling trend of
NAND flash memory as mass storage has started to attract
II. H ISTORY OF ReRAM attention again. Though over the past 20 years of development,
A. Back in the 1960s the application of ReRAM is diversified into several other
domains, i.e., embedded nonvolatile memory (eNVM) and
Studies of the ReRAM device on various oxide materials,
storage class memory (SCM), the original intention of ReRAM
i.e., Al2 O3 , NiO, SiO2 , Ta2 O5 , ZrO2 , TiO2 , and Nb2 O5 , were
research and development is meant for NAND flash extension.
Manuscript received October 14, 2019; revised November 26, 2019; Section VI will discuss this point further.
accepted December 18, 2019. Date of publication January 16, 2020; The decade between 2005 and 2015 was the golden
date of current version March 24, 2020. The review of this article was
arranged by Editor C. Monzio Compagnoni. era of ReRAM research and development. Fig. 2 lists
The author is with Western Digital Corporation, Milpitas, CA the major milestones of ReRAM development: the first
95035 USA, and also with imec, 3001 Leuven, Belgium (e-mail: NiOx -based ReRAM with promising device characteristics
[email protected]). and reliability [10], the first integrated conductive bridge
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. ReRAM (CBRAM) [12], the first HfO2 /Ti device with fully
Digital Object Identifier 10.1109/TED.2019.2961505 conventional fab materials [13], the first published proposal

0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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CHEN: ReRAM: HISTORY, STATUS, AND FUTURE 1421

Fig. 3. ReRAM cell switching current (HfO2 based OxRAM) versus cell
physical size (from 1 µm × 1 µm down to 10 nm × 10 nm) [17].

Fig. 2. All ReRAM technology publications in IEDM, VLSI (VLSI

Technology Symposium) and [Nonvolatile Semiconductor Memory Work- Both of them typically show switching current independence
shop/IMW (NVSMW/IMW)] between 2004 and 2015, with major demon- of device size. This is a highly desired property of a mem-
stration milestones highlighted [10]–[25].
ory device with physical scaling demand. From the early
work of the integrated transition metal oxide (TMO)-based
of 3-D vertical ReRAM [14], the first scaled 10 nm × 10 nm ReRAM [10] to the 10 nm × 10 nm extremely scaled cell [17],
ReRAM integrated in 12-in fab [17], the first 16-Gb CBRAM the switching current independence of the cell size has been
integrated chip [22], the first 40-nm node embedded ReRAM demonstrated. Once the switching current limit is determined
product [24], etc. by the load resistance, selector transistor, or other external
parts, the ReRAM switches at this predetermined current level
C. Future of NAND Is NAND. What Can ReRAM Do? without clear physical cell-size-scaling impact.
Based on this simple electrical characteristic, a localized
With the aggressive logic-state scaling from a single-level
conductive filament is proposed to be the current conduction
cell (SLC) to a multiple-level cell (MLC) to a triple-level
path inside the ReRAM cell. The filament size is imaged
cell (TLC) in 2-D NAND flash memory [9], as well as even
to be smaller than 10 nm × 10 nm, to explain the scaling
more aggressive physical scaling down to 15-nm critical
independence demonstrated down to that dimension (Fig. 3).
dimension (CD), the insertion point of ReRAM on the storage
The filamentary switching theory is well accepted among
roadmap keeps slipping away. Moreover, the introduction [26]
the industry and academia. The modeling efforts [31]–[36]
and commercialization [27] of 3-D NAND technology pave
are mostly spent on the filament creation and switching
a path for NAND scaling in the coming decade and further
processes (Table I summarizes the different modeling efforts in
raises the entry requirement of ReRAM. The ReRAM society
[31]–[36]). The engineering efforts are mostly spent on how to
starts to diverse the application into the low density and
better control the filament creation and switching to improve
low-cost eNVM domain to partially compete with NOR flash
the uniformity and stability.
and create more Internet of Things (IoT) device adoption.
With the introduction to filament theory, a detailed
The concept of SCM gives another hope to ReRAM in an
discussion on its creation and switching processes is
intermediate density range target (i.e., 32–128 Gb per die).
followed.
However, the SCM target sees challenges from both memory
1) Filament Forming: To achieve a revisable switching,
cell and selector integration in a high-density architecture. The
eNVM application has been pursued by several affiliations the filament is created in a controlled manner. A current-
[24], [28]–[30], but its adoption is rather gradual. After limiting mechanism is typically applied during its first cre-
2015, ReRAM technology research and development start to ation (referred to as FORMING) and consecutive recreations
gradually wave down. (referred to as SET). Since ReRAM is usually made from
insulating materials, i.e., oxides, the FORMING and SET
processes are similar as a controlled dielectric soft breakdown.
D. If Not Memory, Anything Else? The current-limiting mechanism is typically a current compli-
With the revival of machine learning in the 2010s, ReRAM ance applied from the external characterization instruments,
for either a binary or an analog computing/storage unit cell has or load resistance/selector transistors on-chip integrated, or
been heavily studied over the past five years. The potential of off-chip connected with the ReRAM cell. As the filament
ReRAM in machine learning and computing in memory (CiM) is created during the very first FORMING step, filament
is there. But its commercial adoption is still at the path-finding properties are intuitively thought to be strongly dependent on
phase. Section VII will briefly discuss ReRAM in machine this process.
learning application. A few questions that physicists typically raise are as follows:
1) What is the physical species created after FORMING?
III. ReRAM D EVICE P HYSICS 2) Can we see them physically?
A. Device Physics: Filamentary Switching A few questions that the engineers typically raise:
As shown in Fig. 1, there are two types of filamentary 1) How high is defect density within the filament?
ReRAM devices: OxRAM (Oxide ReRAM) and CBRAM. 2) How to make a filament with high defect density?

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1422 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

TABLE I
S EVERAL R EPRESENTATIVE P HYSICAL M ODELS OF E XPLAINING AND S IMULATING THE OxRAM S WITCHING P ROCESS [31]–[36]

Fig. 4. 3-D visualization of filament shape with advanced c-AFM

technology. (a) Cu filament in CBRAM [37]. (b) Oxygen vacancy filament
in OxRAM [38]. Fig. 5. Statistics of bipolar versus unipolar switching ReRAM device
demonstration from IEDM, VLSI, NVSMW/IMW between 2004 and 2010.

Physicists’ questions are based on the nature of defects

consisting the filament. As the FORMING is a controlled SET process. This brings practical limitation to integrating
dielectric soft breakdown process, the nature of the species cre- ReRAM with transistors or selectors, as the FORMING volt-
ated is commonly accepted as oxygen vacancies (in OxRAM age can be too high for them to operate properly. To free this
case) and metal ions from the electrode (Cu, Ag, etc., in the limit, numbers of engineering efforts were spent on bringing
CBRAM case). There are seldom other proposals on the the FORMING voltage down to the similar range of the
defect nature, but rather detailed discussion on (in the case SET voltage. By thinning down the dielectric layer or create
of OxRAM) whether it is an oxygen atom moving out of the more defects during dielectric fabrication, the FORMING
oxide lattice (substitutional oxygen vacancy) or a metal atom voltage can decrease. The penalty of using a thinner dielectric
moving into the oxide (interstitial oxygen vacancy). layer or a higher defect density dielectric layer is that the
The efforts in visualizing the filament have been spent resistance ration between the low resistance state (LRS) and
with different techniques used. The most direct visual- high resistance state (HRS) becomes smaller [43]. Physically,
ization in 3-D is based on the conductive atomic force a forming free stack has already certain number of leakage
microscopy (c-AFM) analysis [37], [38], where sizes in paths during device fabrication, and background leakage from
both the CBRAM and OxRAM filaments are observed in a the thin dielectric layer limits the HRS.
single-digit nm range (Fig. 4). 2) Filament Switching: After filament is created, the cells
In terms of engineering methods to better control the fila- are subject to reversible switching between LRS and HRS by
ment properties during FORMING, a few different FORMING SET (HRS to LRS) and RESET (LRS to HRS) operations.
processes were proposed to increase the defect density within Filamentary switching can either be unipolar (SET and RESET
the filament. Though ReRAM does not have the same lateral in the same voltage polarity) or bipolar (SET and RESET in
scaling limitation as does 2-D NAND flash, the switching cur- the opposite voltage polarity).
rent reduction for a high-density memory architecture sets the In early years, unipolar switching, by leveraging the phys-
scaling challenge for ReRAM. The filament stability depends ical model and characterization know-how using the phase
on the total number of defects consisting the filament, and change memory technology, was popular among devices
scales with the maximum FORMING and switching current. (Fig. 5). Unipolar switching is generally regarded as the ther-
With bit density scaling-up requirement for ReRAM, the mal heating assistant mechanism for its RESET process [44].
switching current itself needs to be scaled down, preferably As the RESET process requires Joule heating to melt down
below 10 µA for mass storage or SCM. Defects-based filament the filament, switching current and current density are chal-
shows increasing nonuniformity and much shorter retention lenging to be scaled down. The engineering focus on ReRAM
when the number of defects is scaled [39], [40]. To counter gradually shifted to bipolar switching after 2010 (Fig. 5).
engineer this switching current issue, FORMING with multiple It is worth mentioning that, besides the Joule-heating-based
step [41], reverse bias [41], at higher temperatures [42], etc. mechanism, electron trapping and detrapping was also con-
were proposed. Improvement was seen for typical TMO stacks. sidered for unipolar switching [10], [11]. However, the elec-
Another engineering topic related to the FORMING process tron trapping and detrapping process is more associated with
is the “FORMING-free” device. Typically, the FORMING dielectric to electrode Schottky barrier height modification.
process requires a higher voltage and energy than the It can coexist with the filament present in the device but does

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CHEN: ReRAM: HISTORY, STATUS, AND FUTURE 1423

TABLE II
C ONDUCTION M ECHANISM P ROPOSED FOR ReRAM LRS AND HRS S TATES

not fully explain the relationship between the cell size and of LRS is very tight and the retention is stable. With the
switching current (weakly dependent or independent). switching current scaling (medium current 50–200 µA and low
Bipolar switching in most of the oxide-based material current <50 µA), the LRS conducting current is decreasing.
systems is based on the reduction–oxidation process (referred The filament thus requires fewer defects to conduct the lower
to as redox) via ion movement. Fast-movable ions are either current. In part of the filament, not all defects are well
oxygen vacancies in OxRAM or highly diffusive metal ions in overlapped with each other. The conducting current shows
CBRAM (Cu, Ag, Co, etc.). Thermodynamically, the redox- more nonlinear behavior. Nonlinear I–V itself is not an issue
based switching mechanism defines the SET and RESET oper- but fewer defects in the filament are an issue. With fewer
ations in exchanging the complementary types of species (i.e., defects, the distribution of LRS without verifications becomes
oxygen versus oxygen vacancy) in a complementary switching broader, and the retention starts to seriously degrade.
polarity. Thus, the redox-based bipolar switching is regarded
more sustainable over SET/RESET operations. Numbers of B. Device Physics: Interfacial/Bulk Switching
long endurance (>1010 cycles) were reported on OxRAM
As illustrated in Fig. 1, besides the filamentary switching
devices [18], [69], [77], [78], which points to this advantage.
devices, there are also ionic switching devices that show
Studies on SET and RESET mechanisms are closely linked
the dependence of the switching current on the cell size.
to the engineering work on operation voltage determination
The switching mechanism is understood as the dielectric
for array design as well as endurance improvement.
to electrode Schottky barrier height modulation or redox at
For array design, the SET and RESET voltages are preferred
dielectric bulk with the conductance change of the stack. The
to be stable, particularly at different temperatures and different
interfacial/bulk switching is typically bipolar. As shown in
endurance cycles. From the understood mechanism, both the
Fig. 2, area-dependent type of switching is always present
redox reaction and ion transportation are thermally dependent,
in technology demonstration, but it always stays under the
though experimentally the temperature dependence on SET
shadow of filamentary switching. Owing to the requirement
and RESET voltages is marginal for ReRAM. It is probably
of moving more ions for the interfacial/bulk switching mech-
because the redox and ion transportation within the nm range
anism, area switching is usually slower than filamentary
take place at such faster speeds that no clear impact is visible
switching. However, with the switching current reduction of
on the SET and RESET.
filamentary ReRAM becoming more difficult below 50 µA,
For endurance improvement, the SET and RESET
interests on interfacial/bulk switching have risen over the past
operations in bipolar switching lead to the general understand-
five years.
ing of balancing the number of ions transported back and
Besides the different dependence of the switching current
forth. As the redox reaction and forth back ion transportation
on the cell size, interfacial/bulk switching also has a smaller
are both complementary, balancing the SET and RESET
switching current and more stable retention at a low current
operation with tuning the switching voltage or switching
range [79], [80]. Moreover, the interfacial/bulk switching cell
time or switching current can improve the endurance [77].
typically shows higher nonlinearity than the filamentary cell,
The concept of balancing SET and RESET operations
which provides certain self-rectifying features in array opera-
becomes a standard engineering work for ReRAM endurance
tion. These advantages make interfacial/bulk switching more
improvement.
suitable for large-density and low-current operation memory
3) Current Conduction of LRS and HRS: Current conduc-
array. Section V will provide a more detailed technology
tion mechanisms for LRS and HRS are counted for READ
benchmark on filamentary versus area switching.
operation and the LRS and HRS distributions. It is somewhat
overlooked with respect to SET and RESET switching, as it
IV. ReRAM M ATERIALS
is a static physical event. From the various fit and modeled
mechanisms for LRS and HRS (Table II), one general con- A. Materials of the Switching Layer
clusion is that the LRS and HRS conduction mechanisms are Various materials have demonstrated resistive switching
probably dependent on the current. Take LRS as an example. phenomenon. Table III summarizes the elements used in their
For large current operation (>200 µA), the LRS conduction oxide form as the main switching layer. Since one of the domi-
is mostly ohmic. A filament with a high number of defects nant switching mechanisms is redox-based filamentary switch-
is created with a high switching current, and the total defect ing, oxides and particularly TMO s are the most common
number consisting of the filament is large. The distribution materials. Simply put, if only oxygen vacancies are needed

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1424 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

TABLE III
ReRAM D IELECTRIC AND E LECTRODE M ATERIALS D EMONSTRATED
IN L ITERATURES , W ITH S WITCHING M ODES L ISTED

Fig. 6. Ab initio simulation of required energy for reduction reaction (1).

The lower the energy, the easier the reaction to happen [118].

B. Materials of the Electrodes

Electrodes in the ReRAM stack are not only for electrical
contact, but also are an important part of the resistive switching
layer. The understanding of the role of active electrodes in the
ReRAM stack remained a focus area during the early devel-
opment stage of this technology. The demonstrated electrode
materials are listed in Table III. They can be divided into three
groups:
for switching, there is no major difference between different
oxide materials. The cousins of oxides, nitrides [108], [109], 1) Noble metal, i.e., Pt, Au, Ir, etc.
and some of the chalcogenides [110] also demonstrate resistive 2) Active metal for OxRAM, i.e., Ti, Zr, Hf, Ta,
switching with nitrogen and Te/Se/S vacancies. Al, Ni, etc.
Materials are directly linked to the integration work on 3) Active metal for CBRAM, i.e., Cu, Ag, Co, etc.
the wafer level in the semiconductor fabs. As introduced in Take OxRAM as an example to explain the role of the elec-
Section II, the revival of ReRAM in the 2000s was mainly trodes. Early demonstrations of a ReRAM device show that it
driven for one clear application as NAND flash extension. majorly consists of noble metal electrodes. The SET operation
Therefore, the material stacks need to be feasible and easy of the redox switching mechanism creates oxygen vacancies
for integration on the wafer level. Even though, through and pushes the same amount of oxygen atoms pushed out of
tremendous processes, the technology progress was made, their original lattice position toward the anode. These oxygen
the number of materials typically dealt with in a 12-in fab atoms are needed during RESET operation to oxidize the
is still limited. Oxide materials present in the fab are predom- oxygen vacancies. Thus, when they reach the anode, they
inantly SiO2 . Thanks to the logic Complementary Metal Oxide stay as separate atoms rather than bonding to the electrode
Semiconductor (CMOS) scaling, high-k oxides such as HfO2 materials. Noble metals do not react with oxygen, and thus
are introduced into the fab. Though HfO2 is still has a higher suitable as electrodes to preserve oxygen atoms for reservable
cross-contamination risk than SiO2 , the fabs have know- switching. They offer stable resistive switching owing to their
how to integrate it. HfO2 , thus, becomes a popular choice inner chemical properties. However, they are all difficult to be
as a ReRAM material stack for the integrated device and integrated in a conventional CMOS process.
array.
For the same oxide material, i.e., HfO2 , there are various C. Switching Layer and Active Electrodes’ Interaction
ways of depositing the materials and integrating them under When active electrodes are in contact with the switching
different thermal budgets. Different process conditions for the layer, i.e., Ti to HfO2 , active electrode materials are able
same material change the properties of the material. A reactive to take certain amount of oxygen from the HfO2 lattice
physical vapor deposition sputtered HfO2 has flexibility in owing to the thermodynamic chemical potential driving force.
tuning the Hf:O ratio and modify the defect density dur- Fig. 6 summarizes some typical examples of chemical bond
ing the reaction process. An atomic layer deposition HfO2 formation energy between different metals and HfO2 [118].
is close to stoichiometry, offering excellent film uniformity Owing to the oxygen scavenging effect, certain oxygen gradi-
and coverage in a 3-D vertical structure, but it requires an ent are formed at interface between the active electrode and
extra scavenging layer to create certain defect density for metal oxide. This interface layer [referred to as the oxygen
switching. exchange layer (OEL)] serves as an oxygen reservoir during
With the ReRAM development going on, the technology SET/RESET operation. It stores oxygen after SET and supplies
direction gradually splits into stand-alone and embedded oxygen during RESET. In this sense, the electrode is part of
applications. In both cases, the ReRAM integrates with the the switching stack, rather than merely an electrical contact.
back end of line (BEOL) process (in the definition of logic
CMOS technology). The ReRAM layer is sitting a few BEOL
insulator and metal layers above the CMOS selector transistor D. Asymmetry Stack for 1 and 0 States
and periphery transistor layer. Thanks to this isolation, the con- Besides using active metals to form OEL, oxide-to-oxide
tamination risk of ReRAM stack materials to the front end of stacks are another common way. Typical stacks are based
line (FEOL) CMOS is relatively low. on oxides with many stoichiometries, i.e., TaOx /Ta2 O5 ,

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CHEN: ReRAM: HISTORY, STATUS, AND FUTURE 1425

TABLE IV
T YPICAL OX RAM S TACKS W ITH A SYMMETRIC OXYGEN P ROFILE
C REATED BY D IFFERENT P ROCESSES

Fig. 7. SET and RESET switching current summary. Filamentary and

area switching demonstrations below 10 µA are marked with “F” and “A,”
respectively.

of them are area switching cells rather than filamentary switch-

WOx /WO3 , etc. This method is similar to tuning the metal-to- ing. With more self-rectify feature (nonliner device I −V ) built
oxygen ratio during reactive sputtering. A general description in these area switching cells, the SET and RESET currents are
on the bipolar switching OxRAM stack is that there is an usually asymmetric.
asymmetry of oxygen contents within the stack. With the
asymmetry of oxygen contents, an OEL layer is built in
C. Switching Speed
and serves as an oxygen reservoir. The asymmetric oxy-
gen profile within the stack chemically creates two different Thanks to the fast ionic movement in the nanometer thin
domains, with chemical potential difference for oxygen to film, SET/RESET switching demonstrated on single bit and
metal bonding. With this asymmetry, two different thermo- mini array shows sub-100 ns characteristics. Though on
dynamic energy states are created. Resistive switching then the actual array level with megabit range bank size, the
occurs between these two states. Table IV summarizes some SET/RESET and READ latency are mostly dominant by
typical bipolar switching stacks with asymmetric material the RC of the bitline (BL) and word line (WL), as well as by
regions/compositions within the stack. the periphery circuit. It is still fair to say that the ReRAM cell
itself does not add up significant overhead to the total latency.
V. R E RAM B ENCHMARK The total SET/RESET latency also depends on the actual
program scheme. READ verification after SET/RESET switch-
A. Characteristics Benchmark ing [i.e., incremental step pulse programming (ISPP)] is com-
By summarizing the basic switching and reliability prop- monly used in nonvolatile memory (NVM) (i.e., NAND flash).
erties in International Electron Device Meeting (IEDM), And the total verified attempts define the actual SET/RESET
very large scale integration (VLSI), and International latency. The READ verification attempts at the medium
Memory Workshop (IMW) publications between 2004 and switching current (50 µA) in TMO-based OxRAM stays in
2019 [10]–[15], [17]–[22], [24], [30]–[32], [40], [42], a low range (∼5×) [139], whereas at the 10-µA switching
[43], [45]–[79], [108], [117], [122], [127]–[150], a general current, the number of attempts increases as the switching is
trend of the ReRAM switching characteristics can be drawn. more difficult to reach the target in one single shot. For high
current operation (150–200 µA), single SET/RESET pulses
B. Switching Current with very minor verify scheme shall deliver enough LRS/HRS
window, which enables fast READ and fast SET/RESET on
Fig. 7 shows the SET versus RESET current trend for the array level.
ReRAM devices. For typical bipolar filamentary switching,
the maximum switching current level for the SET and RESET
operations are symmetric. Most of the demonstrations show D. Switching Voltage
the switching current equal to or above 10 µA. For stand- The switching voltage on various ReRAM devices spreads
alone applications (NAND replacement or SCM), sub-10-µA out in a wide range. The actual switching voltage depends
operating current is pursued. However, with the switching cur- on ion mobility, material stack thickness, parasitic resistance,
rent scaling in filamentary switching, retention, nonuniformity, etc. Thus, it is not meaningful to benchmark the switching
and endurance degrade severely. This is one of the reasons that voltage value itself, but rather showing the general trend of
most of the published demonstrations on filamentary switching voltage versus speed tradeoff. A general exponential depen-
are above 10 µA. At sub-10 µA, the symmetric trend of SET dence between voltage versus speed is seen in Fig. 8 for
and RESET currents also breaks apart, indicating a different ReRAM switching [151].
mechanism other than filamentary switching. Fig. 7 lists the The actual switching voltage value is an important parame-
low current switching demonstrations below 10 µA, and most ter for ReRAM in embedded application. Typically, ReRAM is

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1426 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

Fig. 8. SET/RESET voltage versus SET/RESET switching time sum-

mary. A general exponential dependence trend is observed. Fig. 9. Demonstrated ReRAM endurance versus RESET switching
current summary. Filamentary and area switching demonstrations with
current lower than 10 µA and endurance higher than 109 cycles are
driven by a transistor as BEOL NVM in embedded application marked with “F” and “A,” respectively.
(referred to as 1T1R). With the logic CMOS scaling, the VDD
of the MOSFET scales down (i.e., 40-nm foundry CORE
and gradually results in the permanent dielectric breakdown.
0.9–1.2 V, I/O 1.8–2.5 V [152]). The logic transistor voltage
For low and medium switching currents, failure modes vary.
compatibility sets the practical limits for the ReRAM operation
Both failing to RESET and failing to SET have been seen.
voltage, which requires cooptimization in 1T1R integration.
With switching current reduction, the filament contains less
defects and the failure behavior is more random.
E. Endurance
Filamentary OxRAM has demonstrated up to 1012 cycles
[18], [78], and the number of other demonstrations shows F. Retention
1010 cycles [69], [77]. Generally, higher current with balanced Retention benchmark on ReRAM is not straightforward.
SET/RESET conditions gives better endurance. Cautions have Fundamentally all technologies have certain amount of bit
to be taken on the sampling READ approach typically used failure at different temperatures. The definition and statistics
in the long endurance test. Owing to its defect-based nature, of failure criteria are the two essential items of the retention
ReRAM may show random switching failure during cycling. benchmark. Since majority of the ReRAM research work only
Many of these failures are recoverable and the device can demonstrate single bit retention, the benchmark in Fig. 10 is
continue cycling. The READ verify approach is more accurate for the reference purpose only. It is worth mentioning that
to assess the endurance lifetime. Fig. 10(a) is plotted with the switching current on the X-axis,
For the low-end embedded application that ReRAM targets which is the determining factor in ReRAM retention.
for, 104 cycle is typically the lower limit for its endurance From the array statistics viewpoint, from the kilobit to
lifetime. Since eNVM is able to have the current supply megabit range for the embedded application (presumably
>200 µA (higher current generally leads to better endurance, ∼200 µA range), ten-year–retention at 85 ◦ C [28], [143], [147]
as shown in Fig. 9), the 104 cycle endurance spec is a relatively is a reasonably good bit error rate (BER) (<10−7) [30] and
safe number for initial product introduction. even ten-year-retention at 125 ◦ C [146] [149] is achievable.
For NAND replacement, the endurance spec spreads between The extracted activation energy of retention failure is in the
a few thousands and 106 cycles, depending on what types range of 1.2 eV [Fig. 10(b)], which is similar to the FG NAND
of NAND (TLC versus SLC) technology it is compared with. flash.
Though the hope is that ReRAM can reach more than 106 With switching current reduction, retention severely
cycles, to offer better endurance with respect to NAND, for degrades [40] in filamentary switching ReRAM. Accord-
SCM application, 106 cycle is the typical spec. Note that for ing to Fig. 10, demonstration for long retention with the
both NAND and SCM applications, the switching current spec sub-50-µA switching current is limited even on a single-
is scaled to 10 µA. At such low switching current, there are bit level. For the stand-alone application with the targeted
few reports of long endurance. This is one limitation, from switching current below 10 µA, the programmed LRS and
device characteristic point of view, that blocks the way for HRS lose their resistance values even at room temperature
ReRAM in the stand-alone application. within seconds [155]. The fast retention loss at low switching
A few more in-depth studies investigate the endurance current is usually referred to as relaxation. Practically, there is
failure mechanism on OxRAM [154], [155]. Failure depends no straightforward way to mitigate relaxation without tradeoff
on the switching current level, SET/RESET conditions, and of SET/RESET latency. Relaxation is another major limitation
material stacks. A unified failure model is difficult to conclude. for ReRAM in a stand-alone application.
However, the general trend is that, for the high switching Fig. 11 compares the retention and relaxation properties
current, failing to RESET is one of the common modes. The between OxRAM and CBRAM. Though both OxRAM and
dielectric layer is damaged during the SET/RESET operations CBRAM show strong retention degradation at the 10-µA

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CHEN: ReRAM: HISTORY, STATUS, AND FUTURE 1427

Fig. 11. Relaxation (fast retention loss at room temperature)

phenomena comparison between (a) and (b) OxRAM [156] and
(c) and (d) CBRAM [157]. LRS is programed with program and verify to
a predefined read current level (as indicated by the dashed line “Verify”)
and read operations are carried out after different waiting time. The first
read at 500 µs after LRS program already shows a fast retention loss,
with LRS distribution relaxes to the level of single pulse program without
verify (a) and (c). The relaxation shows strong current level dependence.
Low program current level (10 µA) shows clear relaxation while medium
current level (50 µA) shows stable retention (b) and (d).

Fig. 10. (a) Demonstrated ReRAM retention versus RESET switching

current summary. (b) Demonstrated ReRAM retention versus tempera-
ture summary. Calculated guideline with 1.2-eV activation energy for ten
years at 85 ◦ C, one year at 85 ◦ C, one year at 55 ◦ C and one year at
25 ◦ C are plotted.

switching current, the degradation at the 25–50-µA range

is less pronounced for CBRAM. It indicates the fact that
the filament conduction with oxygen vacancies and that with
metal ions are not exactly the same, in terms of defect
density or defect conductivity. The other difference between
OxRAM and CBRAM is that OxRAM filament FORMING Fig. 12. (a) Relaxation of filamentary OxRAM [155]. (b) Relaxation of
area switching ReRAM [80].
is a controlled dielectric breakdown event, whereas metal
ion injection into the dielectric in CBRAM FORMING can
occur well before the applied voltage reaches the dielectric VI. C OMMERCIALIZATION OF ReRAM
breakdown voltage. Thus, the metal ion filament formation
in CBRAM can be decoupled from the dielectric breakdown. The revival of ReRAM from the early 2000s was clearly
A less damaged dielectric with less oxygen vacancies results aimed at a storage technology with better performance and
in less randomness and probably gives better stability at the lifetime than the NAND flash. A 2-D FG NAND was scaling
medium current range (25–50 µA). well, from 90 nm node in 2002 to 24 nm node in 2011 [9],
Owing to the limitation on retention at the scaled switching totalling six generations within one decade. However, there
current, area-dependent switching devices have been studied was always a concern, which was if the 2-D NAND scaling
as an alternative. Fig. 12 shows the retention comparison of was going to hit the limit.
the OxRAM and the area switching (a-VMCO [80]) device. Such concern was strong. Device physics wise, the number
The area-dependent switching ReRAM clearly outperforms the of electrons on the NAND gate was scaling with the device CD.
filamentary ReRAM in relaxation. With a higher number of With projection that when it reached 15-nm CD (1Z nm node
defects involved in the switching, the LRS is better maintained. for 2-D NAND), the electron static control on the multiple
However, the endurance of area-dependent devices at scaled programed VT levels would see a serious overlap. There
dimension (40-nm CD) with a verification scheme shows the were only the single-digit numbers of electrons for each
limited number (1500 cycles) [158], which is far below the VT level, and the electrical impact on adding or losing one
SCM spec. electron became deterministic for the individually programed

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1428 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

Fig. 13. SanDisk/Toshiba 2-deck 24-nm ReRAM demonstra-

tion [161], [162].
Fig. 14. 3-D vertical ReRAM architecture proposals. (a) [128]. (b) [166].
BLs are vertically oriented, and WLs are horizontally extended as comb
VT level. The same challenge was amplified by interference shape.
from densely packed neighboring bits, which were getting
closer and closer with the pitch scaling. potentially a four-deck ReRAM was needed. The continuous
Process technology wise, 2-D NAND flash CD scaling was logic state scaling in NAND technology, from SLC to MLC
driven by lithography. 2-D NAND led the semiconductor indus- to TLC, kept the requirement of ReRAM higher and higher.
try to use 193-nm immersion lithography and self-aligned mul- Together with the switching current versus retention/endurance
tiple patterning [self aligned double patterning (SADP), self issues discussed in Section V, 2-D NAND replacement became
aligned quadruple patterning (SAQP), etc.] for dimensional unachievable.
scaling. It was still possible for the same SAQP scheme to On the other hand, NAND scaling continues. The intro-
continue the lithography printing down to 10 nm, but the duction of fully vertical 3-D NAND technology (referred to
process control became more critical. as BiCS) by Toshiba in 2007 [26] successfully extends the
Architecture wise, 2-D NAND relied on the Si substrate as NAND scaling roadmap after 1Z nm 2-D NAND . Currently,
a channel material. Stacked 2-D NAND with either the c-Si the industry is shipping 9× layers 3-D NAND with QLC
channel [159] or poly-Si thin-film transistor (TFT) was demon- technology. Single die density reaches 1.33 Tb [163]. The 2-D
strated [160], but potentially had thermal budget constraint for memory stacking concept at 20-nm CD probably needs more
the multiple-layer process and higher process cost. than 20 decks to reach such density.
With the consideration to extend the storage roadmap when 2) SCM: With the NAND replacement requirement gradually
NAND scaling was running out of steam, ReRAM as a pure 4F2 faded away, ReRAM saw another potential application as a
memory cell, with potential to be stacked in a simple cross- new memory layer within the memory hierarchy to bridge
point array (BL and WL perpendicular to each other), drew the latency gap between DRAM and NAND: SCM. The con-
attentions. The filamentary nature made the switching itself cept was proposed for some years already [164], while no
almost device CD independent, which was perfect for scaling technology came close to its requirement [165]. 106 cycle
further. Material stacks were usually thinner than 10 nm, mak- endurance with certain nonvolatility (months to a year) and
ing etching easier at the scaled pitch. The switching voltage density/latency between DRAM and NAND are needed for
was much lower than the NAND flash and single-bit switching SCM.
speed was much faster. More importantly, the simple cross- With the density requirement and the fact that most of
point array made individual ReRAM bits randomly accessible. the ReRAM devices could only operate reliably in SLC,
A true RAM with nonvolatility at scaled dimension could be multiple innovation on a 3-D vertical ReRAM technology was
enabled. All these properties made ReRAM a good candidate proposed [14], [128], [142], [166], [173], [174] (Fig. 14). They
to replace the NAND flash. all have similar vertical architectures, with vertical BL and
horizontal WL in a flat trench type of structure. It is similar
A. Stand-Alone to some alternative 3-D NAND architectures [167], [168],
1) NAND Replacement: Following the NAND replacement which were not adopted. With the architecture innovation,
discussion, there were a number of efforts within the semi- the device requirement, however, became stricter. The device
conductor memory industry in pursuing ReRAM as high- shall have certain nonlinearity to enable a selector-less array
density stand-alone memory in a stackable architecture. operation so that the device stack was thin enough to be
Fig. 13, reprinted from the SanDisk/Toshiba demonstra- placed inside the vertical BL trench/hole. The nonlinearity
tion [161], [162], shows a two-deck ReRAM at a 24-nm requirement increased with a higher number of WL layers.
node. The stacked cross-point memory architecture was first At the same time, the switching current shall maintain at
commercialized by a Matrix semiconductor with their one 10 µA or below for power and leakage spec. The READ
time programmable (OTP)-based ROM-type memory [170]. current shall be as high as possible to enable low READ
With its acquisition by SanDisk in 2005, the stacked cross- latency for SCM. In a two-terminal device, such as ReRAM,
point architecture was then coupled with ReRAM. For NAND the switching and READ paths were always coupled. Thus,
replacement, the initial anticipated insertion point was equiv- the low switching current and high READ current require-
alent to 43-nm 2-D NAND (commercialization in 2008). The ments contradicted each other. In case the memory cell did not
43-nm 2-D NAND is a 16 Gb (one plane)/32 Gb (two planes) provide enough nonlinearity, a separate selector was needed.
density with TLC technology. From the density point of view, Memory to selector cooperation at low current switching and
the introduction of TLC NAND raised the market entry bar vertical process integration triggered more difficulties. Since
of ReRAM technology. To compete with MLC NAND, a two- the switching current requirement at the sub-10-µA level
deck ReRAM at the same node could have more scaled die still held for ReRAM as SCM application, the fundamental
size with a smaller periphery. To compete with TLC NAND, LRS/HRS relaxation and retention issues remained unsolved.

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CHEN: ReRAM: HISTORY, STATUS, AND FUTURE 1429

Fig. 15. (a) [24] ReRAM 1T1R cell embedded between M2/M3 on
40-nm CMOS logic (ReRAM physical size 117 nm). (b) [30] ReRAM 1T1R
embedded between M2 / M4 on 22-nm FinFET CMOS logic (ReRAM
physical size 100 nm).
Fig. 16. ReRAM array demonstration for machine learning application
Owing to all this, ReRAM faces practical challenges to be in IEDM and VLSI between 2014 and 2018, with [175]–[179] highlighted.
used for SCM applications.
VII. ReRAM FOR M ACHINE L EARNING
B. eNVM on Logic
With the wave down of ReRAM research as memory
Following many of the early demonstrations of ReRAM technology over the past five years, more attempts are made
in the 1T1R configuration, these technologies are naturally on exploring the potential of using it for machine learning
extended to eNVM integrated at logic BEOL. Panasonic has applications. From early attempts using ReRAM as a dig-
been pioneering their TaOx -based ReRAM in micro controller ital binary switch element [177] to “compute in memory,
units (MCUs), smart cards, and other types of applications CiM” using ReRAM as both storage and computing element,
as NOR flash replacement [24]. TSMC has ReRAM as low- the motivation always stays in leveraging its simple and
end eNVM for NOR flash replacement on their 40-nm logic high-density cross-point architecture. Fig. 16 summarizes the
node [28]. Intel demonstrated their ReRAM as eNVM on ReRAM technology demonstration with different machine
the 22-nm FinFET node [30]. Winbond has their HfO2 - learning implementations and algorithms. With technology
based ReRAM on 90-nm CMOS technology as NVM offer- point of view, encouraging progress has been made from
ing [143] (Fig. 15). With respect to embedded NOR flash, single-bit engineering work with array simulation to kilobit
ReRAM has clear cost advantage [28]. The retention spec and megabit array-level demonstrations. With challenges ahead
may not be sufficient for automobile products, but good to scale up the implementation to even large bit counts, more
enough for most of the consumer products. Thanks to efforts are yet to be made.
its lower energy consumption and lower cost, IoT devices
deployed in the field with energy supply constraint can benefit VIII. C ONCLUSION
from it. Significant efforts have been made over the past 20 years
Though the eNVM market is much smaller than stand-alone in the field of ReRAM technology research and development,
NAND , and the largest segment within eNVM is automobile with aims to commercialize it and understand it. As of today,
products which ReRAM is still not able to compete with its adoption is still limited, and its understanding is still
NOR flash in reliability, the commercialization of ReRAM in incomplete. ReRAM technology offers many unique proper-
this fully established market proves its technology advantage. ties worth the research and development efforts, as well as
Simple process, low cost, and sufficient reliability at high helps overcome difficult scaling barriers. However, with the
current operation are proven by the market. With ReRAM recent interest in energy-efficient machine learning applica-
potentially to be offered on more advanced logic nodes (i.e., tions, we may once again see a rise in ReRAM sentiment.
28-nm high k metal gate (HKMG), 16-/14-nm FinFET, etc.),
the market adoption can be further expanded. ACKNOWLEDGMENT
Sincere acknowledgment to people who ever contribute to
C. Other Attempts
ReRAM technology development and understanding.
Besides the efforts from established industry players, a num-
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