Introduction

1.1 Computer Organization and architecture

1.2 Structure and function
1.3 Designing for performance
1.4 Computer components
1.5 Computer Function
1.6 Interconnection structures
1.7 Bus interconnection
1.8 PCI
 Introduction

ORGANIZATION AND ARCHITECTURE

Computer Architecture refers to those attributes of a system that have a direct impact on the logical
execution of a program. Architectural attributes include the instruction set, the number of bits used to
represent various data types, I/O mechanisms, and techniques for addressing memory. For example, it is
architectural design issues on what type of instructions are to be included, whether to use direct or
indirect addressing for accessing memory and so on. The architectural design decision may be based on
the requirement of the application, and defines the complexity of the system.

Computer organization refers to the operational units and their interconnections that realize the
architectural specifications. Organizational attributes include those hardware details transparent to the
programmer such as control signals, interfaces between the computer and peripherals, and the memory
technology used. For example, it is an organizational issue whether to implement a special purpose unit
or make use the pre-existing unit, for instance, to implement multiply instruction, a special multiply unit
can be used or an add unit can be used repeatedly. The organizational decision may be based on the
expected frequency of use of instruction, the relative speed of the different approaches, and the cost
and physical size of the different units implemented.

STRUCTURE AND FUNCTION

The designer, who only deals with a particular level of the system at a time, must recognize the
hierarchical nature of most complex systems to clearly describe them. At each level, the system consists
of a set of components and their interrelationships; the designer is concerned with structure and
function. Structure of a system can be defined as the way in which the components are interrelated
whereas function of a system may be defined as the operation of each individual component as part of
the structure.

FUNCTION

The general basic functions that a computer can perform are data processing, data storage, data
movement, and control.

Operating
Environment

Figure 1: A functional View of the Computer

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 Data processing: The computer must be able to process data. The data may take a wide variety of
forms and processing requirements.
 Data storage: The computer provides short term data storage function which temporarily stores
data that are being worked on at any given instant. It also performs a long term storage functions in
which data are stored on the computer for subsequent retrieval and update.
 Data movement: The computer must be able to move data between itself and the outside world.
The computer’s operating environment consists of devices that serve as either sources or
destinations of data. When data are received from or delivered to a device (peripheral) that is
directly connected to a computer, the process is known as input-output (I/O). When data are
moved over longer distances, to or from a remote device, the process is known as data
communication.
 Control: The computer must be in control of all the above functions. The control unit manages the
computer’s resources and directs the performance of its functional parts in response to those
instructions.

The numbers of possible operations that can be performed are:

 The computer can function as a data movement device, simply transferring data from one
peripheral or communications line to another. For example: keyboard to screen

 The computer can also function as a data storage device, with data transferred from the external
environment to computer storage and vice versa. For example: Internet download to disk
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 The computer can perform operations involving data processing, on data either in storage or
between storage and the external environment. For example: Updating bank statement, printing
bank statement

STRUCTURE

A computer can be represented in the simplest possible form in which it interacts with its external
environment in some fashion. The simplest possible representation is as shown below:

Peripherals Communication Lines

COMPUTER

 Storage
 Processing

Figure 3: A Simple Computer

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With concern to the internal structure of the computer, there are four structural components;

 Central processing Unit (CPU): It controls the operation of the computer and performs its data
processing functions. It is also referred as processor.
 Main memory: it is used to store data.
 I/O: Moves data between the computer and its external environment.
 System interconnection: It is a mechanism that provides for communication among CPU, main
memory, and I/O. System bus, which consists of a number of conducting wires to which all the other
components attach, is a common example of system interconnection.

Figure: The Computer: Top-Level Structure

The major structural components of the CPU are as follows:

 Control unit: Controls the operation of the CPU and hence the computer
 Arithmetic and logic unit (ALU): Performs the computer’s data processing functions
 Registers: Provides storage internal to the CPU
 CPU interconnection: Mechanism that provides for communication among the control unit, ALU,
and registers
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DESIGNING FOR PERFORMANCE

The driving factors behind the need to design for performance are:

Microprocessor Speed

In addition of new circuits, and the speed boost that comes from reducing the distances between them,
the performance of microprocessor has improved four or fivefold every three years or so. But the raw
speed of the microprocessor will not achieve it potential unless it is fed a constant stream of work to do
in the form of computer instructions. Among the techniques built into contemporary processors are:

 Branch Prediction: The processor looks ahead in the instruction code fetched from memory and
predicts which branches, or groups of instructions, are likely to be processed next. If the
processor guesses right most of the time, it can pre-fetch the correct instructions and buffer
them so that the processor is kept busy. Branch predictions increase the amount of work
available for the processor to execute.
 Data Flow Analysis: The processor analyses which instructions are dependent on each other’s
result, or data, to create an optimized schedule of instructions. In fact, instructions are
scheduled to be executed when ready, independent of the original program order. This prevents
unnecessary delay.
 Speculative execution: Using branch prediction and data flow analysis, some processors
speculatively execute instructions ahead of their actual appearance in the program execution,
holding the results in temporary locations. This enables the processor to keep its execution
engines as busy as possible by executing instructions that are likely to be needed.

Performance Balance

While the processor speed has grown rapidly, the speed with which data can be transferred between
main memory and the processor has lagged badly. The interface between processor and main memory
is the most crucial pathway in the entire computer because it is responsible for carrying a constant flow
of program instructions and data between memory chips and the processor. If memory or the pathway
fails to keep pace with the processor’s insistent demands, the processor stalls in a wait state and
valuable processing time is lost. The above problems can be figured out by following examples:

 Increase the number of bits that are retrieved at one time by making DRAMs “wider” rather
than “deeper” and by using wide bus data paths.
 Change the DRAM interface to make it more efficient by including a cache.
 Reduce the frequency of memory access by incorporating increasingly complex and efficient
cache structures between the processor and main memory. It may include multiple caches or off
chip cache implementation.
 Increase the interconnected bandwidth between processors and memory by using higher speed
buses and by using a hierarchy of buses to buffer and structure data flow.
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The processors can handle the data pumped out by different I/O devices but there remains the problem
of getting that data moved between processor and peripheral. Caching and buffering schemes or the
use of higher-speed interconnection buses and more elaborate structures of buses are some techniques
to resolve the problem.

Improvements in Chip Organization and Architecture

Following are the approaches to achieve increased processor speed.

 Increase the hardware speed of the processor by shrinking the size of the logic gates and
increasing the clock rate. With gates closer together, the propagation time for signals is
significantly reduced, enabling a speeding up of the processor. An increase in clock rate means
that individual operations are executed more rapidly.
 Increase the size and speed of the caches that are placed between the processor and main
memory.
 Make changes to the processor organization and architecture that increase the effective speed
of instruction execution. This involves using parallelism in one form or another.

However, as clock speed and logic density increase, a number of problems will evolve:

 Power: The power dissipation increases, so the difficulty of dissipating the heat generated on
high density, high speed chip becomes a serious issue.
 RC delay: As components on the chip decrease in size, the wire interconnects become thinner,
results in increase in resistance and also the wires are closer together which increase
capacitance. The speed at which electrons can flow on a chip is limited by the resistance and
capacitance of the metal wires connecting them.

Hence, emphasis on organization and architecture is given to improve performance. The use of multiple
processors on the same chip, also referred to as multiples core, or multicore, provides the potential
increase in performance without increasing the clock rate.

COMPUTER COMPONENTS
At a top level, a computer consists of CPU, memory, and I/O components which are interconnected in
some fashion to achieve basic function of the computer.

Central Processing Unit can be specific purpose or general purpose. In specific purpose processor, CPU
consists of arithmetic and logic functions to perform particular arithmetic and logical operations on
data. In such CPU, certain computation to be performed is carried out by the process of connecting
various components in the desired configuration as a form of programming. The set of instructions, to
perform a particular operation, configured in the form of hardware is termed as hardwired program. In
general purpose CPU, a general purpose configuration of arithmetic and logic function is constructed
whose operation varies based on the control signal applied to the hardware. The system accepts data
and control signals and produces results. Instead of rewiring the hardware for each new program, we
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provide a new sequence of codes representing a set of control signals. Each code is an instruction and
part of the hardware interprets each instruction and generates the corresponding control signal. Here
the sequence of codes or instructions is called software.

I/O components consist of the input module and output module. Input module consists of basic
components for accepting data and instructions in some form and converting them into an internal form
of signals usable by the system. However, output module contains basic components as a means of
reporting results. Memory is required to store instructions and data temporarily since the operation on
data may require access to more than just one element at a time.

The figure below illustrates the top level components and indicates the interaction among them.

Figure: Computer Components: Top Level View

 CPU exchanges data with memory making the use of two internal registers MAR and MBR.
 MAR specifies the address in memory for next read or write operation.
 MBR contains the data to be written into memory or receive the data read from memory.
 I/O AR specifies a particular I/O device.
 I/O BR is used for the exchange of data between an I/O module and the CPU.
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 Memory module consists of set of location, each containing a binary number that can be
interpreted as instruction or data, defined by sequentially numbered address.
 I/O module contains internal buffers for temporarily holding data which are transferred from
external devices to CPU and memory, and vice versa.

COMPUTER FUNCTION
The basic function of computer is to execute a program or set of instructions. The processing required
for a single instruction is called an instruction cycle. In simplest form, instruction processing consists of
two steps, fetch cycle and execute cycle.

Figure: Basic Instruction Cycle

Fetch Cycle

 A register called Program Counter (PC) holds address of instruction to be fetched next.
 Processor fetches instruction from memory location pointed to by PC.
 PC gets incremented after each instruction fetch so that it will fetch next instruction in sequence.
 The fetched instruction, containing bits that specify the action to be performed, is loaded in
Instruction Register (IR).
 The processor interprets the instruction and performs required operation.

Execute Cycle

 Data may be transferred from processor to memory or from memory to processor.

 Data may be transferred to or from a peripheral device by transferring between the processor and
an I/O module.
 The processor may perform some arithmetic or logic operation on data.
 An instruction may specify that the sequence of execution be altered.

Instruction Cycle – State Diagram

For any given instruction cycle, some states may be null and others may be visited more than once.

 Instruction address calculation (IAC) determines the address of next instruction to be executed.
Generally, it involves adding fixed number to the address of the previous instruction. For example,
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for a 16 bits long instruction, one must be added to the previous address for 16 bit words memory,
whereas two must be added to the previous address for 8 bit bytes memory.
 Instruction Fetch (IF) read instruction from memory location into the processor.
 Instruction Operation Decoding (IOD) is a state which analyzes instruction to determine type of
operation to be performed and operands to be used.
 Operand Address Calculation (OAC) determines the address of the operand for the operation
involving reference to an operand in memory or I/O.

Figure: Instruction Cycle State Diagram

 Operand Fetch (OF) fetches the operand from memory or read it in from I/O.
 Data Operation (DO) performs the operation indicated in the instruction.
 Operand Store (OS) writes the result into memory or out to I/O.

States in the upper part of the figure involve an exchange between the processor and either memory or
an I/O module. States in the lower part of the diagram involve only internal processor operations. The
OAC state appears twice, because an instruction may involve a read, a write, or both.

INTERRUPT

Interrupts, which halts the ongoing process of the system and serves the exigent device, are primarily
provided as a way to improve processing efficiency. Most of the external devices are much slower than
the processor; therefore processor must pause and remain idle for many hundreds and thousands of
instruction cycle that do not involve memory operation. This is very wasteful use of processor. With
interrupt, the processor can be engaged in execution of other instructions while an I/O operation is in
progress. From user program point of view, an interrupt is just an interruption of the normal sequence
of program execution and when the interrupt processing is completed, normal program execution
resumes. For example, when the external device requires any sort of service, the I/O module for that
external device sends an interrupt signal to the processor, the processor responds by suspending
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operation of the current program, branching off to a program to service that particular I/O device
known as interrupt handler, and resuming the original execution after the device is serviced.

When an interrupt occurs processor does the following actions.

 It suspends execution of the current program being executed and saves its context. It includes
saving the address of the next instruction to be executed and any other data relevant to the
processor’s current activity.
 It sets the program counter to the starting address of an interrupt handler routine.

Figure: Instruction Cycle with Interrupts – State Diagram

To implement interrupts, an interrupt cycle is added to the instruction cycle. In the interrupt cycle, the
processor checks for interrupts, indicated by the presence of an interrupt signal. If no interrupts are
pending, the processor proceeds to the fetch cycle and fetches the next instruction of the current
program. If an interrupt is pending then,

 Suspend execution of current program

 Save context of current activity, address of next instruction to be executed and relevant data
 Set PC to start Address of interrupt handler routine
 Process interrupt request
 Restore context and Continue interrupted program

Classes of Interrupt

 Program: Generated by some condition that occurs as a result of an instruction execution. For
example, arithmetic overflow, divide by zero, invalid memory reference
 Timer: Generated by a timer within the processor. Allows OS to perform certain functions on a
regular basis.
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 I/O: Generated by an I/O controller, to signal normal completion of an operation or to signal a

variety of error conditions.
 Hardware failure: Generated by a failure such as power failure.

Multiple Interrupts

Disabled Interrupt means that processor will ignore further interrupts whilst processing one interrupt.
Interrupts remain pending and are checked after first interrupt has been processed. Interrupts are
handled in sequence as they occur. This approach is simple to implement but it does not consider
relative priority or time critical needs. It results in sequential interrupt processing.

Priority Interrupt causes low priority interrupts to be interrupted by higher priority interrupts. When
higher priority interrupt has been processed, processor returns to previous interrupt. Each device is
assigned a priority based on which the interrupt services are provided by the processor. It may result in
sequential or nested interrupt processing.

I/O FUNCTION

An I/O module can exchange data directly with the processor. As with memory, the processor can also
read data from and write data to an I/O module. Also the processor identifies a specific device that is
controlled by a particular I/O module. In some cases, I/O is allowed to exchange data directly with
memory to relieve the processor’s responsibility. This operation in which the processor grants I/O
module the authority to read from or write to memory so that I/O – memory transfer can occur directly
without the involvement of processor is known as (DMA)direct memory access.

INTERCONNECTION STRUCTURES
The collection of paths connecting the various modules is called interconnection structure. Each module
can be defined based on the major forms of input and output.

Memory

 Consists of N words, each assigned a unique numerical address, of equal length

 A word of data can be read from or written into memory.
 Read and write control signals indicates the nature of operation
 Location for the operation is specified by an address

I/O module

 May control more than one external device

 Each of the interfaces to an external device is referred as a port and a unique address is given.
 External data paths for the input and output of data with an external device
 Sends interrupt signal to the processor
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Processor

 Reads instruction and data, writes data after processing.

 Uses control signal to control the overall operation of the system
 Receives interrupt signals

The interconnection structure must support the following type of transfers:

 Memory to processor: The processor reads an instruction or a unit of data from memory.
 Processor to Memory: The processor writes a unit of data to memory.
 I/O to processor: The processor reads data from an I/O device via an I/O module.
 Processor to I/O: The processor sends data to the I/O device.
 I/O to or from memory: I/O module is allowed to exchange data directly with memory using DMA.

BUS INTERCONNECTION
A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that
it is a shared transmission medium. Multiple devices are connected to a bus, but a signal transmitted by
any one device is available for reception by all other devices attached to the bus. If more than one
device transmits data at the same time then the data will overlap and gets corrupted.

Bus Structure

A bus that connects major computer components (processor, memory, I/O) is called a system bus. A
system bus consists of number of separate lines; each assigned a particular meaning or function. The
lines within any bus can be classified as:

 Data Bus: The collection of data lines providing a path for moving data among system modules are
called data bus. The data bus consists of number of lines referred as width of the data bus. Each line
can carry only one bit at a time. The width of the data bus is a key factor in determining overall
system performance. For example, if the data bus is 32 bits wide and each instruction is 64 bit long,
then the processor must access the memory module twice each instruction cycle.
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 Address Bus: The address lines are used to designate the source or destination of the data on the
data bus. For an instance, if the processor wishes to read a word of data from memory, it puts the
address of the desired word on the address lines. The width of the address bus determines the
maximum possible capacity of the system. Also the address lines are used to address I/O ports.
Generally, the higher-order bits are used to select a particular module on the bus, and the lower-
order bits select a memory location or I/O port within the module. For example, for an 8 bit address
bus, 01111111 and below may refer to locations n memory module (0) and address 10000000 and
above refer to devices attached to an I/O module (1).
 Control Bus: the control lines are used to control the access to and the use of the data and address
lines. The data and address lines are shared by all components. Hence, there must be a means of
controlling their use. Control signals transmit both command and timing information among system
modules. Timing signals indicate the validity of data and address information. Command signals
specify operations to be performed. Some of the common control signals such as memory read,
write, bus request, grant, interrupt request and ACK can be taken as examples.

Multiple-Bus Hierarchies

If a large number of devices are connected to a single bus, the performance will degrade.

 The large number of devices attached to the bus increases the bus length and the propagation
delay. This delay determines the time it takes for devices to coordinate the use of the bus. When
control of the bus passes from one device to another frequently, these propagation delays can
noticeably affect performance.
 The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity
of the bus.

Traditional Bus Architecture

A local bus connects the processor to a cache and may support one or more local devices. The cache
memory controller connects the cache not only to this local bus but to a system bus to which are
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attached all the main memory modules. Cache insulates the processor from a requirement to access
main memory frequency, hence main memory can be moved off of the local bus. In addition, I/O
transfers to and from the main memory across the system bus do not interfere with the processor’s
activity. An expansion bus interface buffers data transfer between the system bus and I/O controller on
the expansion bus, also support a wide variety of I/O devices and insulates memory to processor traffic
from I/O traffic.

High Performance or Mezzanine architecture

A high speed bus is closely integrated with the rest of the system, requiring only a bridge between the
processor’s bus and the high speed bus. A local bus connects the processor to a cache controller, which
in turn connects to a system bus that supports main memory. The cache controller is integrated into a
bridge, or buffering device that connects to a high speed bus. High speed bus arrangement specifically
designed to support high capacity I/O devices. Lower speed devices are supported off an expansion bus
with an interface buffering traffic between expansion bus and high speed bus. The advantage of this
arrangement is that the high speed bus brings high demand devices into closer integration with the
processor and at the same time is independent of the processor.

Figure: Mezzanine Architecture

ELEMENTS OF BUS DESIGN

Bus Types

 Dedicated bus: Physical dedication refers to the use of multiple buses, each of which connects
only a subset of module. A typical example is the use of an I/O bus to interconnect all I/O
modules; this bus is then connected to the main bus through some type of I/O adapter module.
The advantage of physical dedication is high throughput due to less bus contention. Increased
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size and cost of the system is one major disadvantage. Functional dedication is the use of
separate dedicated address and data lines.
 Multiplexed bus: Use of same lines for multiple purposes is known as time multiplexing. In this
method, the address is placed at the beginning of data transfer and address valid line is
activated. The address is then removed after the addressed module is ready, and the same bus
connections are used for the subsequent read or write data transfer. One major advantage of
time multiplexing is the use of fewer lines saving space and cost. Disadvantages may include
complex circuitry, and possible reduction in performance.

Method of Arbitration

More than one module may need control of the bus but only one unit at a time can successfully transmit
over the bus, the mechanism to control such activity is referred as arbitration.

 Centralized: A single hardware device (bus controller or arbiter) is responsible for allocating
time on the bus. The device may be a separate module or a part of the processor.
 Distributed: Each module contains access control logic and the modules act together to share
the bus.

In both methods, the purpose is to designate one device (either processor or I/O module) as master. The
master may then initiate a data transfer with some other devices, which acts as slave for this particular
exchange.

Bus Width

 The width of the data bus has an impact on system performance. The wider the data bus, the
greater the number of bits transferred at a time.
 The width of the address bus has an impact on system capacity. The range of locations that can
be referenced increases with the increasing width of the address bus.

Timing

Timing refers to the way in which events are coordinated on the bus.

 Synchronous timing: Occurrence of events on the bus is determined by a clock. All events start
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at the beginning of a clock cycle. It is simpler to implement and test. But it is less flexible than
asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate, the
system cannot take advantage of advances in device performance.
 Asynchronous timing: The occurrence of one event on a bus follows and depends on the
occurrence of previous event. A variety of slow and fast devices, using older and newer
technology, can share a bus.

Data Transfer Type

A bus supports various data transfer types:

 Write Operation: For multiplexed address/data bus, the bus is first used for specifying the
address and then for transferring the data. In the case of dedicated address and data buses, the
address is put on the address bus and remains there while the data are placed on the data bus.
The master puts the data onto the data bus as soon as the address has stabilized and the slave
takes the opportunity to recognize its address.
 Read Operation: In case of multiplexed bus, the slave recognizes its address and waits for a
while before placing the data onto the bus. In case of dedicated bus, the slave puts the data
onto the data bus as soon as it has recognized its address and has fetched the data.
 Read Modify Write Operation: A read operation is followed immediately by a write to the same
address. The address is only broadcast once at the beginning of the operation. The whole
operation is typically indivisible to prevent any access to the data element by other potential
bus masters. The principal purpose of this capability is to protect shared memory resources in a
multiprogramming system.
 Read after write operation: It is an indivisible operation consisting of a write followed
immediately by a read from the same address. The read operation may be performed for
checking purposes.
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 Block data transfer: One address is followed by n data cycles. The first data item is transferred
to or from the specified address; the remaining data items are transferred to or from
subsequent addresses.

PCI
The Peripheral Component Interconnect (PCI) is a popular high-bandwidth, processor independent bus
that can function as a mezzanine or peripheral bus. It just not only delivers better system performance
for high speed I/O subsystems but also meets the I/O requirement of modern system economically; it
requires very few chips to implement and support other buses attached to the PCI bus. The current
standard allows the use of up to 64 data lines at 66 MHz, for a raw transfer rate of 528 Mbps or 4.224
Gbps. PCI has been widely adopted in personal computer, workstation, and server systems. It is
designed to support a variety of microprocessor based configurations including both single and multiple
processor system. It provides a general purpose set of functions and makes use of synchronous timing
and a centralized arbitration scheme.

Bus Structure

PCI may be configured as a 32 or 64 bit bus. 49 mandatory signal lines of PCI are divided into different
functional groups.

 System pins: Include the clock and reset pins.

 Address and data pins: Include 32 lines that are time multiplexed for addresses and data. The other
lines in this group are used to interpret and validate the signal lines that carry the addresses and
data.
 Interface control pins: Control the timing of transactions and provide coordination among initiators
and targets.
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 Arbitration pins: These signal lines are not shared lines. Each PCI master has its own pair of
arbitration lines that connect it directly to the PCI bus arbiter.
 Error reporting pins: Used to report parity and other errors.

PCI specification defines 51 optional signal lines divided into following functional groups.

 Interrupt pins: These are provided for PCI devices that must generate requests for service. These are
not shared lines and each PCI device has its own interrupt line or lines to an interrupt controller.
 Cache support pins: These pins are needed to support a memory on PCI that can be cached in the
processor or another device.
 64 bit bus extension pins: Include 32 lines that are time multiplexed for addresses and data and that
are combined with the mandatory address/data lines to form a 64 bit address/data bus. Other lines
in this group are used to interpret and validate the signal lines that carry the addresses and data.
Finally, there are two lines that enable two PCI devices to agree to the use of the 64 bit capability.
 JTAG/boundary scan pins: These signal lines support testing procedures defined in IEEE standard
1149.1.

PCI commands

Bus activity occurs in the form of transactions between and initiator or master and a target. When a
master acquires control of the bus, it determines the type of transaction that will occur next. During the
address phase of the transaction, the C/BE lines are used to signal the transaction type. Some of the
commands are

 Interrupt Acknowledge is a read command intended for the device that functions as an interrupt
controller on the PCI bus.
 Special Cycle is used by the initiator to broadcast a message to one or more targets.
 I/O Read and I/O Write are used to transfer data between the initiator and an I/O controller.
 Memory Read is used to specify the transfer of a burst of data, occupying one or more clock cycles.
 Memory Read Line
 Memory Read Multiple
 Memory Write is used to transfer data in one or more data cycles to memory.
 Memory Write and Invalidate guarantees at least one cache line is written.
 Configuration Read & Configuration Write enables a master to read and update configuration
parameters in a device connected to the PCI.
 Dual Address Cycle is used by master to indicate that it is using 64 bit addressing.

Data Transfers

Every data transfer on the PCI bus is a single transaction consisting of one address phase and one or
more data phases. During read or write operation, all events are synchronized to the falling transitions
of the clock, which occur in the middle of each clock cycle.
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Arbitration

PCI makes use of a centralized, synchronous arbitration scheme in which each master has a unique
request (REQ) and grant (GNT) signal. These signal lines are attached to a central arbiter and a simple
request grant handshake is used to grant access to the bus. The arbiter can use a first come first serve
approach, a round robin approach or some sort of priority scheme. A PCI master must arbitrate for each
transaction that it wishes to perform, where a single transaction consists of an address phase followed
by one or more contiguous data phases. Arbitration taking place at the same time that the current bus
master is performing a data transfer where no bus cycles are lost in performing arbitration is referred to
as hidden arbitration.