Max40109-3402282 Dos
Max40109-3402282 Dos
Applications
• Pressure Sensors
• Strain Gauges
• Force Sensors
• Temperature Sensors
• Wheatstone-Bridge
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MAX40109 Precision Signal Conditioning AFE for Pressure
Sensor Applications
TABLE OF CONTENTS
General Description ............................................................................................................................................................ 1
Applications......................................................................................................................................................................... 1
Benefits and Features ......................................................................................................................................................... 1
Simplified Block Diagram .................................................................................................................................................... 5
Absolute Maximum Ratings ............................................................................................................................................... 6
Package Information ........................................................................................................................................................... 6
Electrical Characteristics ..................................................................................................................................................... 7
Typical Operating Characteristics ..................................................................................................................................... 13
Pin Configurations............................................................................................................................................................. 17
Pin Descriptions ................................................................................................................................................................ 17
Detailed Description .......................................................................................................................................................... 18
Register Function .......................................................................................................................................................... 18
Configuration Register ............................................................................................................................................... 20
PGA Input Mux........................................................................................................................................................... 20
ALERT Mode ............................................................................................................................................................. 20
Pressure Digital Output cases: .................................................................................................................................. 21
Temp Current ............................................................................................................................................................. 21
Shutdown ................................................................................................................................................................... 22
Current Source Reference Resistor........................................................................................................................... 22
Reference .................................................................................................................................................................. 22
Digital Filter ................................................................................................................................................................ 22
Pressure Cal Bypass ................................................................................................................................................. 23
Temp Cal Bypass....................................................................................................................................................... 23
MTP_EN .................................................................................................................................................................... 23
Status Register .......................................................................................................................................................... 23
PGA Pressure Gain ................................................................................................................................................... 24
Current Source........................................................................................................................................................... 24
Uncalibrated Pressure ............................................................................................................................................... 25
Uncalibrated Temperature ......................................................................................................................................... 25
ADC Sample Rate...................................................................................................................................................... 25
Interrupt Enable ......................................................................................................................................................... 26
Bridge Drive ............................................................................................................................................................... 26
PGA Temperature Gain ............................................................................................................................................. 26
Calibrated Pressure ................................................................................................................................................... 27
Calibrated Temperature ............................................................................................................................................. 27
Temp Mode ................................................................................................................................................................ 27
Sensor Offset Cal Config ........................................................................................................................................... 28
VDD = 24V
VREF PLC
MAX40109
5V LDO INPUT
DRV
V/I 1.8V LDO DIAGNOSTICS
DRIVER 1.25V
INT
REFERENCE DQ (1-Wire)
SCRATCHPAD MCU
AND MTP
DRV SDA
REXT* INT 1-Wire,
DIAGNOSTIC
MUX INP+ PLC, AND SCL
CAL MTP
INP- MEMORY I2C
PGA
9-BIT DAC
MUX 16-BIT DAC
PGA GAIN/OFFSET
INP+ AND NL 14-BIT DAC
SENSOR COMPENSATION
BRIDGE
INP- OP-AMP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rati ngs only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to abs olute maximum rating conditions for extended periods may affect
device reliability.
Package Information
TQFN
Package Code T2044-5C
Outline Number 21-0139
Land Pattern Number 90-0429
Thermal Resistance, Single Layer Board:
Junction to Ambient (θJA) 48
Junction to Case (θJC) 2
Thermal Resistance, Four Layer Board:
Junction to Ambient (θJA) 33
Junction to Case (θJC) 2
For the latest package outline information and land patterns (footprints), go to https://www.analog.com/en/design-
center/packaging-quality-symbols-footprints/package-index.html. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package
regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to https://www.analog.com/en/technical-
articles/thermal-characterization-of-ic-packages.html.
Electrical Characteristics
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDRV = 4V, 10kΩ bridge, VINP+ –VINP- =
System Level 4mV (DC), G = 252V/V, Noise BW 3dB = 12.4
Performance: Noise- 1kHz, GOUT = 4V/V
bits
Free Effective IDRV = 500μA, 3.5kΩ bridge, VINP+ –
Resolution VINP- = 75mV (DC), G = 15V/V, Noise 12.8
BW 3dB = 1kHz, GOUT = 1V/V
INPUT PGA
G = 15V/V 0.6V < VCM < 1.7V 180 850
Zero-pressure
offset
1.7V < VCM < 2.8V 440 2000
compensation
disabled
Input Offset Voltage VOS µV
G = 144V/V
Zero-pressure 0.6V < VCM < 2.8V
offset 76 450
compensation
disabled
VCM > 1.7V 0.062 1.6
Input Offset Drift TCVOS μV/°C
VCM < 1.7V 0.018 0.8
TA = +25°C 60 400
Input Bias Current IB pA
-40°C ≤ TA ≤ +125°C 3860
Input Offset Current IOS 9.2 400 pA
VDDHV ≥ 4.4V 0.6 2.8
Zero-pressure
3.8V ≤ VDDHV ≤
offset 0.6 2.6
compensation 4.4V
Input Common Mode VCM VVDDHV
Range disabled VDDHV ≤ 3.8V 0.6
-1.2
Zero-pressure offset compensation 0.37 x 0.63 x
VDRV VDRV V
enabled
5, 10,
15, 20,
24, 40,
60,
72,
90,
108,
Programmable Internal ADC Input 126,
Range of Gain G through 1-wire Full-Scale Range is 144, V/V
and/or I2C 1.25V 160,
180,
200,
252,
540,
1080,
1440,
2520
Gain Selection Settling
10 ms
Time
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
G = 15V/V 0.15 0.9
Gain Error GE %
G = 144V/V 0.45 1.4
Gain Error Temperature G = 15V/V 4
TCGE ppm/ºC
Coefficient G = 144V/V 9
INPUT PGA/AC SPECIFICATIONS
G = 15V/V 55
Signal Bandwidth BW3dB kHz
G = 144V/V 24.5
Zero-pressure
offset
2.5
compensation
disabled
0.1Hz ≤ f ≤ 1kHz,
Zero-pressure
G = 15V/V
offset
compensation 2.7
enabled (at
30mV/V)
Input Voltage-Noise VN μVRMS
Zero-pressure
offset
0.23
compensation
disabled
0.1Hz ≤ f ≤ 10Hz,
Zero-pressure
G = 144V/V
offset
compensation 0.78
enabled (at
80mV/V)
VRFpeak = 100mVp, f = 400MHz,
EMI Rejection Ratio EMIRR
900MHz, 1800MHz, 2400MHz, both IN+ 80 dB
and IN-
INPUT PGA/ZERO-PRESSURE OFFSET COMPENSATION
Corresponds to
Resolution Including sign 12 bits
44μV/V
Offset Range 80 93 mV/V
TEMPERATURE MEASUREMENT
150,
Sourced at INT pin
Current Source Range VINT = 0V to 1.6V 250, uA
500, 750
Input Common Mode VCM Guaranteed by CMRR parameter 0.25 1.6 V
Range
Common Mode VCM = 0.25V to 1.6V
CMRR 95 dB
Rejection Rate
1.5, 2, 3,
G = 1, 1.5, and 2 5, 6, 10,
Programmable are for single- 15, 20,
Range of Gain G through 1-wire ended only. G = 3 24, 30, V/V
and/or I2C is for differential 36, 40,
only 45, 60,
72, 90
Input Offset Voltage VOS 50 2,000 µV
Gain Error GE Gain = 10V/V ±0.4 ±2.5 %
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Gain-Bandwidth Product GBW 200 kHz
Input Voltage-Noise VN f = 1kHz 180 nV/√Hz
Density
BRIDGE DIAGNOSTICS
Applies to all: OV_INP+,
OV_INP-, UV_INP+,
UV_INP-,
Diagnostic Voltage
OV_DRV, UV_DRV, 8 bits
Threshold Resolution
OV_INT,
UV_INT
Applies to all:
OV_INP+,
OV_INP-,
UV_INP+,
UV_INP-, From 0% to 90% of
VDD5V ±3
OV_DRV,
UV_DRV,
OV_INT,
UV_INT
Diagnostic Voltage
LSB
Threshold Accuracy Applies to all:
OV_INP+,
OV_INP-,
UV_INP+,
UV_INP, Above 90% of
VDD5V -3 ±2
OV_DRV,
UV_DRV,
OV_INT,
UV_INT
ANALOG-TO-DIGITAL CONVERTER
1, 2, 4,
Sample Frequency ksps
8, 16
SENSOR BRIDGE VOLTAGE SOURCE
Programmable
VDRV IDRV = 0mA to 2mA 1.8, 2.3,
Voltage Source Range through Digital V
3.3, 4.0
Interfaces
Voltage Source Range ΔVDRV IDRV = 0mA to 2mA 3.5 %
Accuracy
SENSOR BRIDGE CURRENT SOURCE
250,
300,
400,
Programmable
IDRV VDRV = 4V 450,
Current Source Range through 1-wire µA
500,
and/or I2C
550,
650,
750
Current Source Range ΔIDRV VDRV = 0V to 4V 5 %
Accuracy
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Zero-pressure
compensation
offset enabled
VDDHV ≥ 4.65V 1.8 4.2
Guaranteed by
Input Referred
Voltage Range at Bridge Residual Voltage
VDRV V
Top Zero-pressure
compensation
offset enabled 3 x ln
3V ≤
1.8 (VDDHV)
VDDHV ≤ 4.65V
Guaranteed by -0.41
Input Referred
Residual Voltage
Applies over "Voltage Range at Bridge
Top" specification. Zero-pressure
Input Referred Residual VRES compensation offset = FS/4 ±3 mV
Voltage
Input PGA Gain = 15
INTERNAL/EXTERNAL REFERENCE
Reference Voltage VREF 1.25 V
Internal Reference VREFTC 15 ppm/ºC
Voltage Temp-Co
OUTPUT AMPLIFIER AND DIGITAL TO ANALOG CONVERTER
Current (4mA–20mA) Output 1
DAC Full-Scale
Voltage Output, 5V 1.25V, VDDHV = 4
Gain GOUT 5.5V V/V
DAC Full-Scale
Voltage Output, 3V 0.5V, VDDHV = 6
3.3V
Output Voltage High VOH VDD5V - VOUT RL= 10KΩ to GND 94 160 mV
Output Voltage Low VOL VOUT - GND RL = 10KΩ to GND 3 15 mV
Slew Rate SR 0.12 V/µs
Capacitive Loading CLOAD AV = 4V/V 500 pF
Stability
POWER SUPPLY
Guaranteed by PSRR, -40°C < TA <
Supply Voltage VDDHV 3 36 V
+125°C
Internal Digital Supply VDD2V 1.7 1.8 1.9 V
Voltage
Internal Analog Supply VDD5V VDDHV ≥ 6V 5.05 5.28 5.5 V
Voltage
VDDHV –
VDDHV = 5V 121 201
Internal Analog Supply VDD5V
mV
LDO Dropout VDDHV –
VDDHV = 3V 121 199
VDD5V
Power Supply Rejection 6 ≤ VDDHV≤ 36V
PSRR 105 dB
Ratio
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current IDD 2 2.57 mA
Communication
2
ready
Power-Up Time tON VDDHV = 0V to 5V ADC Calibration ms
completed – Ready 140
for Measurements
Low-Power Mode ISHDN -40ºC ≤ TA ≤ +125ºC 250 μA
Supply Current
Turn-On Time tONSD From Low-Power Mode (through I2C) 50 µs
I2C LOGIC DC CHARACTERISTICS
0.7 x
Input High Voltage VIH V
VDD5V
0.3 x
Input Low Voltage VIL V
VDD5V
Input High Leakage IIH Logic Input to VDD5V -1 ±0.005 +1 µA
Current
Input Low Leakage IIL Logic Input to 0V -1 ±0.005 +1 µA
Current
Input Capacitance CIN 5 pF
Output Low Voltage VOL IOL = 3mA 0 0.3 V
Output High Leakage VOUT = VDD5V ±0.005 1 µA
Current
I2C TIMING
Serial Clock Frequency fSCL 50 1M Hz
Bus Free Time Between
Start and Stop tBUF 0.5 µs
Conditions
START Condition Hold tHD:STA 0.26 µs
Time
STOP Condition Setup tSU:STO 90% of SCL to 10% of SDA 0.26 µs
Time
Clock Low Period tLOW 0.5 µs
Clock High Period tHIGH 0.26 µs
START Condition Setup tSU:STA 90% of SCL to 90% of SDA 0.26 µs
Time
Data Setup Time tSU:DAT 10% of SDA to 10% of SCL 50 ns
Data In Hold Time tHD:DAT 10% of SCL to 10% of SDA 0 µs
SCL/SDA Rise Time tR 120 ns
SCL/SDA Fall Time tF 20 120 ns
20 x
Transmit SDA Fall Time tF Bus capacitance = 550pF. VDD ≥ 2.4V (VDD 120 ns
/5.5V)
SCL Time Low for Reset tTIMEOUT 20 45 ms
of Serial Interface
Maximum Pulse Width
of Spikes That Must Be
50 ns
Suppressed by the Input
Filter
(Global conditions unless otherwise stated. VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values
at 25°C, Min\Max Temperature = -40°C ≤ TA ≤ +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capacitive Load for CB 550 pF
Each Bus Line
1-Wire LOGIC DC CHARACTERISTICS (DQ)
VDDHV = 3V to 0.8 x
Input Voltage Level High VIH DQ only V
5.5V VDDHV
VDDHV = 3V to 0.2 x
Input Voltage Level Low VIL DQ only V
5.5V VDDHV
Output Voltage Level VDDHV = 3V to 0.75 x
VOH DQ only 4 V
High 5.5V VDD5V
VDDHV = 3V to
Output Voltage Level VOL DQ only 5.5V, ISINK = 200 mV
Low
500μA
PLC LOGIC DC CHARACTERISTICS (INPUT V DDHV, OUTPUT OUT)
Input Voltage Level High VIN_HIGH 31 V
Input Voltage Level Low VIN_LOW 24 V
DAC output ≥
Output Voltage Level VOH 0.82 x
Analog OUT only 0x3665 (85% of V
High FS
full-scale)
DAC output ≤
Output Voltage Level VOL 0.18 x
Analog OUT only 0x0999 (15% of 0 V
Low FS
full-scale)
1-Wire TIMING ON DQ
Time Slot tSLOT 60 120 μs
Recovery Time tREC 1 μs
Write-Zero Low Time tLOW0 60 120 µs
Write-One Low Time tLOW1 1 15 µs
Read Data Valid tRDV 20 µs
Reset Time High tRSTH 480 µs
Reset Time Low tRSTL 480 µs
Presence-Detect High tPDHIGH 15 60 μs
Presence-Detect Low tPDLOW 60 240 µs
DQ (Data) Capacitance CIN/OUT 25 pF
PLC TIMING WITH VDDHV AS INPUT AND OUT AS OUTPUT
Time Slot tSLOT 480 960 μs
Recovery Time tREC 8 μs
Write-Zero Low Time tLOW0 480 960 µs
Write-One Low Time tLOW1 100 120 µs
Read Data Valid tRDV 120 µs
Reset Time High tRSTH 3.84 ms
Reset Time Low tRSTL 3.84 ms
Presence-Detect High tPDHIGH 120 480 μs
Presence-Detect Low tPDLOW 480 1920 µs
VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values at 25°C, Min\Max Temperature = -40ºC ≤
TA ≤ +125ºC.
VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values at 25°C, Min\Max Temperature = -40ºC ≤
TA ≤ +125ºC.
VDDHV = 5V, VDRV = 4V, VIN+ = VIN- = VDRV/2, Analog Filter BW = 1.2kHz, Typical values at 25°C, Min\Max Temperature = -40ºC ≤
TA ≤ +125ºC.
Pin Configurations
TOP VIEW
VDD2V
(PINS AT THE BOTTOM)
OUT
FB-
DQ
NC
15 14 13 12 11
SCL 16 10 FB+
VDD5V 17 9 SDA
MAX40109
18 8 INT
VDDHV 19 7 DGND
EP
NC 20 + 6 DRV
1 2 3 4 5
AGND
REFIN
NC
INP+
INP-
20-PIN TQFN
(4mm × 4mm)
Pin Descriptions
PIN NAME FUNCTION
Sensor Bridge Drive: Drive either current or voltage. It is also used to measure the temperature (as a
6 DRV
voltage) from the bridge.
2 INP+ Non-inverting Pressure Sensor Input. Users can connect up to 10nF between INP+ and INP-.
4 INP- Inverting Pressure Sensor Input. Users can connect up to 10nF between INP+ and INP-.
5 AGND Analog Ground
7 DGND Digital Ground
VDDHV Main positive supply voltage and power line communication serial interface input. The range is from 3V
19
to 36V. The suggested (but not required) bypass capacitor is from 10nF to 100nF.
8 INT Input Temperature: Connect to either a diode or a thermistor.
Input reference and also bypass capacitor (100nF) for the Internal reference: A bit in the Config Regist er
1 REFIN
selects between external and internal voltage reference.
9 SDA I2C Data
16 SCL I2C Clock
14 DQ 1-Wire Serial Input/Output. It must be held to a logic level high when idle.
18 ALERT Active Low Alert Interrupt Output. See the ALERT Mode section for the functionality of this output.
10 FB+ Output Amplifier Feedback Input, Positive.
11 FB- Output Amplifier Feedback Input, Negative.
12 OUT Analog output, as well as PLC serial interface output.
17 VDD5V Internal 5V output from LDO: Bypass with a 220nF capacitor.
15 VDD2V Internal 1.8V output from LDO: Bypass with a 220nF capacitor.
3, 13, 20 NC Do not connect.
EP EP Exposed Pad. Connect to analog ground.
Detailed Description
The MAX40109 is a low-power, precision sensor interface SoC that includes a high-precision, programmable AFE, ADC,
calibration memory, and digital signal processing. It also includes a DAC with an output buffer to support analog voltage
output and a 4mA–20mA current loop. It is designed for sensor applications such as strain gauges, pressure, force, and
temperature.
Register Function
The registers are accessible from all digital interfaces such as 1-Wire, I2C, and PLC.
All digital interfaces follow the same sequence of sending the register address first (command field), followed by the data
field. Data can be either one byte or two bytes, depending on the type of register.
Upon power-up, all registers listed in Table 1 as both Random-access memory (RAM) and Multi-time programmable
(MTP) memory will initialize with the last saved content in the MTP memory. Such content can be overwritten during
normal functionality, but unless saved in the MTP memory, this new content will be lost once the device is powered down.
See the section Burning to MTP for the procedure of saving the register content in the MTP memory.
Zero Pressure Offset Sets the zero pressure offset RAM override
1Ch 1 0h R/W
Select value.
The analog output stage register sets the signal
Analog Output Stage 1Eh 4 0h R/W
at the OUT pin.
SLP_MR 9Bh 16 0000h R/W Register for initializing MTP.
SLP_MREF 9Dh 16 0000h R/W Register for initializing MTP.
CP_Control_1 9Fh 8 00h R/W Control register 1.
CP_Control_2 A0h 8 00h R/W Control register 2.
MTP_Control A2h 8 00h R/W MTP control.
MTP_Status A3h 8 00h R/W MTP status.
MTP_PROT_ADDR A4h 8 00h R/W MTP prototyping write address.
MTP_PROT_WDATA A5h 16 0000h R/W MTP prototyping write data.
MTP_PROT_RDATA A7h 16 0000h RO MTP prototyping read data
MTP_LEVEL A9h 16 00h RO MTP burn count.
SLP_MRV ABh 16 0000h R/W Register for initializing MTP.
SLP_MREFV ADh 16 0000h R/W Register for initializing MTP.
MTP_DATA0 AFh 16 0000h R/W Setting MTP data.
MTP_ADDR B1h 8 00h R/W Setting MTP address.
Configuration Register
The configuration register contains 16 bits of data.
INP+ INP-
PGA PGA
INP– INP+
ALERT Mode
The ALERT mode contains 3-bit of data, as shown in Table 3.
000: The ALERT output is used to issue interrupts as defined in the "Status" register by using the "Interrupt Enable"
register as a mask.
001: The ALERT output generates a PWM signal based on the most significant 12-bit of the data from the "Calibrated
Temperature" register. The PWM frequency is fixed at 2MHz / 4,096 = 488Hz.
Temp Current
Current Source for temperature measurement. This current is generated to the INT pin when an external thermistor is
used.
Table 5. Source Current [5:4]
BIT 5 BIT 4 SOURCE CURRENT (µA)
0 0 150
0 1 250
1 0 500
1 1 750
Shutdown
Bit 7 is used to shutdown the MAX40109.
Bit 7 = 0: The MAX40109 is active (default).
Bit 7 = 1: The MAX40109 is in shutdown mode. In this mode, all analog functionality is disabled, and the device only
responds to 1-Wire and I2C commands.
Current Source Reference Resistor
Bit 8 is used to select a reference resistor for the current source between the internal resistor and the external resistor
connected to the INT pin.
See the Applications Information section "Use External Resistor for Bridge Current Source" for more details.
Bit 8 = 0: Internal resistor (default).
Bit 8 = 1: External resistor.
If an external resistor is selected, it is not possible to set the temp mode to thermistor.
Reference
Bit 9 is used to select between the internal and external references.
Bit 9 = 0: Use internal reference (default).
Bit 9 = 1: Use external reference.
Digital Filter
This option calculates the average among samples. See Table 6 for more details.
In case any of these faults happen, the user has the possibility to shutdown the MAX40109 by accessing the shutdown
bit in the Configuration register. The user can select which faults to receive on the ALERT pin by using the Interrupt
Enable register.
To clear each flag in bits D11 to D0, a write to this register with the same word that was read is required. Writing 1 will
clear the bit that reads 1. When doing this flag clearing, what is written in the upper byte is meaningless and will not affect
this register.
Current Source
This register selects the current source values.
Table 10. Current Source
BIT 2 BIT 1 BIT 0 CURRENT (µA)
0 0 0 250
0 0 1 300
0 1 0 400
0 1 1 450
1 0 0 500
1 0 1 550
1 1 0 650
1 1 1 750
Uncalibrated Pressure
16-bit read-only register that holds the last pressure measurement data from the ADC before the digital calibration.
The pressure format is normalized. The smallest pressure is 1.0/32768 (0x0001), and the largest is 32767/32768
(0x7FFF).
Uncalibrated Temperature
16-bit read-only register that holds the last temperature measurement data from the ADC prior to the calibration.
The temperature measurement is effectively a voltage measurement performed by the MAX40109.
See the Applications Information section for more details.
Users can choose the unit scale (oC or oK) in their MCU firmware. The MAX40109 is agnostic to the unit scale.
The temperature sample must be interleaved between two pressure samples seamlessly, meaning that the pressure data-
rate must never be interrupted.
Interrupt Enable
This register includes the enables for interrupt generation flags with the same bit order as they are reported in the status
register. 1 = Interrupt is enable (default). 0 = Interrupt is disabled POR condition is 0xFF.
Table 14. Interrupt Register
BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Temp Pressure
Data Data UV_DRV OV_DRV UV_INT OV_INT UV_INP- OV_INP- UV_INP+ OV_INP+
Ready Ready
Bridge Drive
Table 15. Bridge Drive
BIT BIT
BRIDGE DRIVE BIT 1 COMMENT
2 0
Disconnected 0 0 0 Default mode at device power up
Current Source 0 0 1 The ADC reference is connected to the internal reference
Voltage Source at 4V 0 1 0 The ADC reference is connected to the bridge voltage
Voltage Source at 3.3V 0 1 1 The ADC reference is connected to the bridge voltage
Voltage Source at 1.8V 1 0 0 The ADC reference is connected to the bridge voltage
Voltage Source at 2.3V 1 0 1 The ADC reference is connected to the bridge voltage
Calibrated Pressure
16-bit read-only register that holds the last pressure measurement data after the digital calibration.
The pressure format is normalized. The smallest pressure is 1.0/32768 (0x0001), and the largest is 32767/32768
(0x7FFF).
Temp Mode
Select how to configure the temperature channel at INT and DRV pins.
See the Temperature Measurement section Applications Information for more details.
Analog Filter BW
This register is used to select the internal analog filter for the pressure channel.
SLP_MR
16-bit register reserved for MTP initialization.
SLP_MREF
16-bit register reserved for MTP initialization.
CP_Control_1
8-bit register reserved for MTP burning.
CP_Control_2
8-bit register reserved for MTP burning.
MTP_Control
Table 25. MTP_Control Register
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MTP_RESTORE RESERVED RESERVED MTP_PROT_EN RESERVED RESERVED STOP_PROG SRT_PROG
The MTP_Control register is used in MTP prototyping to the shadow register and burning to the MTP registers.
SRT_PROG: Used to start MTP burn.
STOP_PROG: Used to stop MTP burn.
MTP_PROT_EN: Used for prototype an MTP write to the shadow registers before burning to the MTP registers.
MTP_RESTORE: Used for restoring the MTP registers during prototyping of an MTP write to the shadow registers.
MTP_Status
Table 26. MTP_Status
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DONE ECC_ERR_2BIT ECC_ERR_1BIT RESERVED VPP_INIT_FAIL MTP_FULL VERI_FAIL VPP_ACT
The calibration can be bypassed through the Configuration Register. By bypassing the calibration the MAX40109 is
providing raw sensor data (Raw Mode).
The format of the coefficients is shown in Table 28.
Table 28. Offset Coefficients, k0 and h0:
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Sign Data
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data
- All other coefficients.
Table 29. All Other Coefficients
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Sign Integer Fraction
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fraction
MA
As shown in Table 30, there are four bits, each reserved for both the p- and n- sides of the trim. Together with 7 bits
shared by both p- and n- sides, we have 11 total bits of offset trim for each side.
The independently controlled/programmable "LSB" bits for p- and n- sides can be used to minimize the mismatch between
p- and n- currents. If the p/n current mismatch residue after the trim is 0 then the sensor offset compensation remains
valid for any gain setting.
If this is important, then this residue must be minimized and confirmed for the required gain values.
Table 31 shows the typical value of bridge offset compensation bit-weights. For example, when the bridge sensor input
has zero pressure, if we set sign bit to 0, B14 to 1, and B13-B0 to 0 (0x4000), the typical value of offset compensation is
4.5e-2 V/V, for 2.3V bridge drive voltage, we see an effective input voltage of -103.5mV at the input. For the 1.8V bridge
drive voltage, we are seeing an effective input voltage of -81mV.
This feature can be enabled/disabled with the zero-pressure offset enable MTP bit, which by default is disabled.
Config Register
Configuration register includes miscellaneous functions.
I2C Client Address
The MAX40109 uses a 7-bit MTP register to store the I2C address.
Such a register can only be written and read through the 1-wire interface.
Lock MTP
The MTP lock bit is located in the MTP register CONFIG MTP (0x44), bit 15.
0 = MTP memory is not locked (default).
1 = MTP memory is locked, and no further changes are possible.
Once the MTP lock bit is burned in memory, it will stay locked and cannot be changed. MTP registers will be read-only.
Zero-pressure Offset Enable
The zero-pressure offset enable bit is located in the MTP register COMFIG MTP (0x44), bit 14.
0 = The "Zero-pressure offset" compensation is enabled.
1 = The "Zero-pressure offset" compensation is disabled.
Sensor Polarity
The sensor polarity bit is in the MTP register CONFIG MTP (0x44), bit 13.
0 = The sensor is unipolar (default).
1 = The sensor is bipolar.
MTP Re-programmability
The MTP memory can be re-programmed a finite number of times.
In particular, the calibration memory (see "Bridge Sensor Calibration") can be re-programmed 40 times.
All other memories and registers can be re-programmed ten times.
Output Clipping Thresholds
The MAX40109 uses two thresholds (upper and lower) to program the analog output clipping levels.
Each of the two thresholds is a 5-bit register.
See the MTP register "Analog Output Stage" to determine whether the analog output is in voltage mode or current mode.
The clipping range is different in the two cases.
See "Output Clipping Enable" to see whether this feature is enabled.
Initializing MTP
When the user is ready to burn to MTP, the user will need to apply a minimum of 12V at the V DDHV supply pin. The
following I2C/1-Wire sequence of commands must be performed.
• Write CP_Control_1 register with 8’h80.
• Write CP_Control_2 register with 8’h1B.
• Write SLP_MR register with 16’h0302.
• Write SLP_MREF register with 16’h0200.
• Write SLP_MRV register with 16’h0300.
• Write SLP_MREFV register with 16’h0401.
Burning to MTP
When burning to MTP, 12V is the minimum supply voltage at VDDHV. For each register, the user will need to burn in the
data by using the following procedure.
• Write to the MTP_ADDR register with 8’hxx where xx is the desired MTP register.
• Write to the MTP_DATA0 register with 16’hxxxx where xxxx is the desired MTP data.
• Write to the MTP_Control register with 8'h01.
Example: To set the TEMP_OFFSET register in MTP, the user would set the MTP_ADDR0 register to 0x3E. Next, write
0x0FF to set the MTP_DATA register to half scale of the 9-bit DAC. Lastly, write 0x01 to the MTP_Control register.
Repeat the above steps until all the MTP registers are burned to the desired settings. Once completed, the user should
power down and power up to check the MTP settings. To confirm the settings, a read must be performed.
• Write to the MTP_Control with 8'h10;
• Set the MTP_PROT_ADDR to the desired MTP address to read.
• Read from the MTP_PROT_RDATA register.
Digital Interface Management
All internal RAM registers as well as various MTP memories and registers can be accessed by any of the digital interfaces.
The only exceptions are the MTP register for I2C address that can only be accessed through 1-wire.
The MAX40109 responds to either of its digital interfaces, meaning either to 1-wire or I2C. In case of concurrent access,
1-Wire takes the priority.
1-Wire Interface
The MAX40109 1-Wire interface is a bi-directional communication through the DQ pin. The DQ line should be held to the
logic level when 1-Wire is idle.
Power Line Communication (PLC)
The MAX40109 power line communication is a two-wire uni-directional interface that takes input data on the VDDHV line
and output data coming out from the analog OUT pin. The DQ line must also be held high to enable PLC functions. These
protocols do not function if DQ is low ever.
To use the PLC, the digital signal must have a VIH above 31V and a VIL below 24V. DQ must be connected to a high
logic level. VDDHV one-wire is activated if a particular key-code is entered within 1 second of the power applied.
The VDDHV key-code timer starts with a rising edge of VDDHV through the VIH level. There are three 50ms periods from
that rising edge point in time.
In the first 50ms period, the sequence starts from a rising edge at 0ms, and there must be exactly four pulses of ≥1ms
high and ≥1ms low in the first 45ms. At least the last 5ms of the 50ms period must be low for timing tolerance.
In the second 50ms period, there must be at least 5ms of low time before pulses, again, a minimum of 1ms high and 1ms
low and a minimum 5ms low before the 100ms time. In this second period, there must be 1 to 4 whole pulses applied.
The pulse count, 1-4, will override the 2 LSB bits of Analog Output Stage register bits (in a shadow temporary register).
In the third 50ms period, there must be at least 5ms of low time before pulses, again, a minimum of 1ms high and 1ms
low. In this third period, there must be 1.5 to 4.5 pulses applied, ending at a high state. There must be a minimum of 10ms
high time before the 150ms time, and 10ms held past the 150ms time to accommodate timing tolerances. The pulse
count, 1.5-4.5, will override the 2 MSB bits of Analog Output Stage register bits (in a shadow temporary register).
The overall number of pulses in the second and third 50ms periods will determine the analog output configuration by
overriding the Analog Output Stage MTP register with a shadow 4-bit RAM register, as follows:
In Group 2, 50ms duration:
• if we have 1 pulse (high +low) then AOS[1:0] = 00.
• if we have 2 pulses (high +low) then AOS[1:0] = 01.
• if we have 3 pulses (high +low) then AOS[1:0] = 10.
• if we have 4 pulses (high +low) then AOS[1:0] = 11.
Normal transactions consist of 2-byte writes and reads, however some registers are single byte read. Attempting longer
transactions is not recommended. A transaction always begins with a START (S) condition followed by the client address
and the Write/Read bit.
A 2-byte write transaction (Write Word) begins with the host generating a START condition and then transmitting the
MAX40109's client address, followed by the Write bit. The MAX40109 acknowledges with an ACK (A) bit, and the host
transmits the target register, followed by another ACK from the MAX40109. The host then writes the two data bytes, and
the MAX40109 ACKs each. The host ends the transaction by generating a STOP (P) condition. Writing more bytes (not
recommended) will overwrite the register (e.g., DATA HIGH - DATA LOW - DATA HIGH - DATA LOW for a 4-byte write).
A 2-byte read (Read Word) is more complex than a write. After transmitting the register byte and receiving an ACK from
the MAX40109, the host generates a REPEAT START (Sr) and writes the address and a Read bit. The MAX40109 then
ACKs the address/read byte and transmits the two data bytes. The host ACKs the first and NACKs the second, signaling
that the transaction is complete, and generating the STOP condition.
A one-byte read is similar to the Read Word above, but only one byte is read; see Figure 11.
Hardware Configuration
The MAX40109 supports two hardware options using asynchronous serial data interfaces.
These options are one-time programmed at the factory.
1. 1-Wire serial data has an independent input/output pin (DQ).
2. Serial data input is shared with VDDHV, and serial data output is shared with the analog voltage output (OUT).
The 1-Wire bus has, by definition, only a single data line. Each device (host or client) interfaces to the data line using an
open-drain or three-state port. This allows each device to “release” the data line when the device is not transmitting data,
making the bus available for use by another device. The device’s 1-Wire port (DQ) is an open drain with an internal circuit
equivalent to that shown in [[Hardware Configuration]].
The 1-Wire bus requires an external pullup resistor of approximately 5kΩ; thus, the idle state for the 1-Wire bus is high.
If, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume.
Infinite recovery time can occur between bits so long as the 1-Wire bus is in the inactive (high) state during the recovery
period. If the bus is held low for more than 480µs, all components on the bus are reset.
MA
Transaction Sequence
The transaction sequence for accessing the device is as follows:
Step 1: Initialization.
Step 2: ROM Command (followed by any required data exchange).
Step 3: Function Command (followed by any required data exchange).
It is very important to follow this sequence every time the MAX40109 is accessed, as the MAX40109 only responds if any
steps in the sequence are in order. An exception to this rule is the Search ROM command. After issuing this ROM
command, the host must return to step 1 in the sequence.
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset
pulse transmitted by the bus host followed by a presence pulse(s) transmitted by the client(s). The presence pulse lets
the bus host know that client devices (MAX40109) are on the bus and are ready to operate. Timing for the reset and
presence pulses is detailed in 1-Wire Signaling section.
ROM Commands
After the bus host has detected a presence pulse, it can issue a ROM command. These commands operate on the unique
64-bit ROM codes of each client device and allow the host to single out a specific device if many are present on the
1-Wire bus. These commands also allow the host to determine how many and what types of devices are present on the
bus. There are four ROM commands, and each command is 8 bits long. The host device must issue an appropriate ROM
command before issuing a MAX40109 function command. An exception to the rule is when the detect address is used to
communicate with devices. ROM commands are not used when selecting an address to communicate. [[MAX40109
ROMs Command Flowchart]] shows a flowchart for the operation of the ROM commands.
Data Format
The data format for a Command Field (either ROM or Function Command) is shown in Figure 17 and Figure 18.
1-Wire Signaling
Using a strict 1-Wire communication protocol helps to ensure data integrity. This protocol defines several signal types:
reset pulse, presence pulse, write-zero, write-one, read-zero, and read-one. The bus host initiates all these signals except
the presence pulse.
Initialization Procedure: Reset and Presence Pulses
All communication with the device begins with an initialization sequence that consists of a reset pulse from the host
followed by a presence pulse from the device (illustrated in [[Initialization Timing]]). When the device sends the presence
pulse in response to the reset, it indicates to the host that it is on the bus and ready to operate.
During the initialization sequence, the bus host transmits (Tx) the reset pulse by pulling the 1-Wire bus low for 480µs
(min). The bus host then releases the bus and enters receive mode (Rx). When the bus is released, the pullup resistor
pulls the 1-Wire bus high. When the device detects this rising edge, it waits for 15µs to 60µs and then transmits a presence
pulse by pulling the 1-Wire bus low for 60µs to 240µs.
Applications Information
Temperature Measurement
The MAX40109 offers two modes to collect temperature measurements:
1. Directly from the bridge resistance. In this mode, the sensor bridge must be driven with current through the DRV
output pin. The device measures the voltage directly at DRV. Temperature measurements from DRV (as voltage
signals) are collected seamlessly from pressure measurements by automatically inserting a temperature
measurement within two pressure measurements. The data rate ratio between pressure and temperature samples
is determined in the register ADC Sample Rate.
2. By connecting a thermistor to the input INT.
See register Temp Mode for details on enabling each mode and the "Configuration" register for the driving current at the
INT pin.
In addition, the temperature channel input amplifier may be configured as either single-ended or differential, as shown in
Figure 23.
IB
K1
INT
RT
G1
BRIDGE G2
SENSOR K6
A2
K7
K8
Y-CODE
9-BIT DAC
CURRENT
MIRROR
MAX40109
DRV
INT
BRIDGE
VREF SENSOR
REXT
RINT EXTERNAL
CURRENT SET
RESISTOR
24V
MAX40109
OUT ROUT
R1
OP-AMP R3
R2
R4
RSENSE
MAX40109
OUT ANALOG
R1 OUTPUT
OP-AMP R3 STAGE
R2
R4
R2EXT
Layout Recommendations
Some critical layout guidelines are as follows.
• Place bypass capacitors near supply and reference pins (VDDHV, VDD5V, VDD2V, REFIN).
• Use PCB with ground planes when possible. Avoid crossing analog and digital signals.
• Connect the EP to the analog ground.
• Create a star connection between AGND and DGND (TQFN package only).
VDD = 24V
VREF PLC
MAX40109
5V LDO INPUT
DRV
V/I 1.8V LDO DIAGNOSTICS
DRIVER 1.25V
INT
REFERENCE DQ (1-Wire)
SCRATCHPAD MCU
AND MTP
DRV SDA
REXT* INT 1-Wire,
DIAGNOSTIC
MUX INP+ PLC, AND SCL
CAL MTP
INP- MEMORY I2C
PGA
9-BIT DAC
MUX 16-BIT DAC
PGA GAIN/OFFSET
INP+ AND NL 14-BIT DAC
SENSOR COMPENSATION
BRIDGE
INP- OP-AMP
SUPPLY VOLTAGE
VREF PLC
MAX40109
5V LDO INPUT
DRV
V/I 1.8V LDO DIAGNOSTICS
DRIVER 1.25V
INT
REFERENCE DQ (1-Wire)
SCRATCHPAD
AND MTP MCU
DRV SDA
REXT* INT 1-Wire,
DIAGNOSTIC
MUX INP+ PLC, AND SCL
CAL MTP
INP- MEMORY I2C
PGA
9-BIT DAC
MUX 16-BIT DAC
PGA GAIN/OFFSET
INP+ AND NL 14-BIT DAC
SENSOR COMPENSATION
BRIDGE
Analog Sensor with Ratio-metric Voltage Output and External Resistors to Set the Gain
SUPPLY VOLTAGE
VREF PLC
MAX40109
5V LDO INPUT
DRV
V/I 1.8V LDO DIAGNOSTICS
DRIVER 1.25V
INT
REFERENCE DQ (1-Wire)
SCRATCHPAD
AND MTP MCU
DRV SDA
REXT* INT 1-Wire,
DIAGNOSTIC
MUX INP+ PLC, AND SCL
CAL MTP
INP- MEMORY I2C
PGA
9-BIT DAC
MUX 16-BIT DAC
PGA GAIN/OFFSET
INP+ AND NL 14-BIT DAC
SENSOR COMPENSATION
BRIDGE
VREF PLC
MAX40109
5V LDO INPUT
DRV
V/I 1.8V LDO DIAGNOSTICS
DRIVER 1.25V
INT
REFERENCE DQ (1-Wire)
SCRATCHPAD
AND MTP MCU
DRV SDA
REXT* INT 1-Wire,
DIAGNOSTIC
MUX INP+ PLC, AND SCL
CAL MTP
INP- MEMORY I2C
PGA
9-BIT DAC
MUX 16-BIT DAC
PGA GAIN/OFFSET
INP+ AND NL 14-BIT DAC
SENSOR COMPENSATION
BRIDGE
INP- OP-AMP
Ordering Information
PART NUMBER PIN-PACKAGE DIGITAL INTERFACES
MAX40109IATP+ 20-TQFN I2C, 1-Wire, and PLC
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 12/23 Initial release —
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their
respective owners.
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