COUNTER

Dr. Deepali Borakhade

Assistant Professor
S.No. Synchronous Counter Asynchronous Counter
In asynchronous counters FF are
In Synchronous counters clock
connected in such a way that
1. is applied simultaneously for all
output of first FF is applied as
the flip-flops.
clock to second FF and so on.

The operation of synchronous Asynchronous counters operate at

2.
counters is relatively faster. a slower pace.
Asynchronous counters are
Synchronous counters are also
3. commonly known as Serial
referred to as Parallel counters.
counters.
Synchronous counters are less Asynchronous counters are more
4. prone to errors as compared likely to produce errors than
to asynchronous counters. synchronous counters.
The design of synchronous Asynchronous counters have a
5.
counters is more complex. simpler design.
Since clock is applied
Asynchronous counters has low
simultaneously to all FF, the
speed as clock propagated
6. speed of Synchronous counters
through all the flip flops before
is more and propagation delay
reaching to last FF
is less
 F= 16 Hz

1
1 FF F1= F / 2
=> = 16 / 2 =
8Hz

2 FF 2
F2= F / 2
=> = 16 / 4 =
4 Hz

3
3 FF F3= F / 2
=> = 16 / 8 = 2
Hz

4
4 FF F4= F / 2
=> = 16 /
16
= 1 Hz
  4 4

 8 200 Hz
100 Hz 400 Hz
50 Hz
 2
 16
Clock Input

800 Hz
q Counter may be UP – Counter or Down Counter

q An Up Counter counts in upward direction i.e. 0,1,2,3,4…….

q A Down counter counts in downward direction i.e.….6,5,4,3,2,1,0 etc i.e. N,N-1, N- 2, N- 3…..1,0

q The number of states through which the counter passes before returning to starting state is called

modulus of counter. Hence modulus of counter is total number of distinct states.

q Since 2 bit counter has four states, its is called as mod – 4 counter. It requires two flip flops. It divides

the input clock frequency by 4, therefore also called as divide-by-4 counter

q Similarly 3 bit counter uses 3 flip flop and has 23 = 8 states hence called as mod – 8 counter.

q In general, an 8 bit counter will have n FF and 2 n states and divides the input frequency by

2n.Hence it is divide-by-2n counter

 Asynchronous/Ripple Counter
Two bit Ripple Up - Counter QA

q Counter is initially at reset state i.e. 00

QB
q When first negative edge trigged clock pulse is
1 1 2 2
applied to first FF1, flip flop toggles therefore Q1
1 2
goes from LOW to HIGH.
q This becomes positive going clock to FF2. Hence it 1 1 2 2
remains unaffected.
q Hence state of the counter after first clock is Q1= 1
and Q2= 0 . i.e. 01.
q At the negative edge of second clock FF1 toggles,
So Q1 changes from High to LOW which act as
negative clock for FF2. 1

q Hence state of counter will be Q1 = 0 and Q2= 1 i.e.

10. 2
q This will repeat and counter will count Count Stage 00 01 10 11 00
00,01,10,11,00 and so on.
Clock Cycle 0 1 2 3 4
Two bit Ripple Down - Counter
3 bit(mod-8) Asynchronous /Ripple Counter using J-K Flip Flop
4 bit(mod-16) Asynchronous /Ripple Down Counter using J-K Flip Flo
 STEPS FOR DESIGNING ASYNCHRONOUS COUNTER

qDETERMINE NUMBER OF FLIP FLOPS REQUIRED.

qFIND TYPE OF FF TO BE USED.
qWRITE TRUTH TABLE AND K – MAP.
qDRAW LOGIC DIAGRAM. ADDITIONAL CIRCUIT WILL BE CONNECTED TO
CLR INPUT OF FF.
 Design mod-6 Asynchronous /Ripple Counter using T Flip Flop

q A mod-6 counter has six stable states 000, 001, 010, 011, 100,101.
q When sixth clock pulse will come counter will automatically goes
Clock Q3 Q2 Q1 Output of
reset
to 110 but immediately resets to 000.
logic R
q Number of FF requires are 3.
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1
Q2Q1
Q3 00 01 11 10

1
X 1

R = Q3.Q2
 DESIGN MOD-10 ASYNCHRONOUS /RIPPLE COUNTER USING T FLIP FLOP

q A mod-10 counter has six stable states 0000, 0001, 0010, 0011,
0100. 0101, 0110, 0111, 1000, 1001 Clock Q4 Q3 Q2 Q1 Output
of reset
q When sixth clock pulse will come counter will automatically logic R
goes to 1010 but immediately resets to 0000. 0 0 0 0 0 0
q Number of FF requires are 4.
1 0 0 0 1 0
Q2Q1
Q4Q3 00 01 11 10 2 0 0 1 0 0
00 3 0 0 1 1 0
01 4 0 1 0 0 0
11
X X X X 5 0 1 0 1 0
10
X 1 6 0 1 1 0 0
7 1 1 1 1 0
R = Q4.Q2
8 1 0 0 0 0
9 1 0 0 1 0
10 0 0 0 0 1
IMPLEMENT 3 BIT RIPPLE DOWN COUNTER USING D FLIP FLOP
SYNCHRONOUS COUNTER
qDetermine Number of Flip Flops required.
qState Diagram.
qFind type of FF to be used and excitation table.
qWrite truth table and k – map.
qDraw Logic diagram.
 DESIGN 3 BIT (MOD – 8) SYNCHRONOUS UP COUNTER USING T FLIP FLOP

q A 3 bit synchronous counter has eight stable states 000, 001, 010, 011, 100. 101, 110, 111.
q Number of FF requires are 3.

Requires
Present State Next State
Excitation
Q3 Q2 Q1 Q’3 Q’2 Q’1 T3 T2 T1
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1 1
2 0 1 0 0 1 1 0 0 1
3 0 1 1 1 0 0 1 1 1
4 1 0 0 1 0 1 0 0 1
5 1 0 1 1 1 0 0 1 1
State Diagram
6 1 1 0 1 1 1 0 0 1
7 1 1 1 0 0 0 1 1 1
 Q2Q1
Q2Q1
Q3 00 01 11 10
Q3 00 01 11 10
0 1 0 1 1
1
1 1
1 1
T3 = Q2Q1 T2 = Q1
Q2Q1
Q3 00 01 11 10

0 1 1 1 1
1 1 1 1 1

T1 = 1
 DESIGN 3 BIT (MOD – 8) SYNCHRONOUS UP COUNTER USING J-K FLIP FLOP

q A 3 bit synchronous counter has eight stable states 000, 001, 010, 011, 100. 101, 110, 111.
q Number of FF requires are 3.

Present State Next State Requires Excitation

Q3 Q2 Q1 Q’3 Q’2 Q’1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
 Q2Q1
Q2Q1 Q2Q1
Q3 00 01 11 10
Q3 00 01 11 10 Q3 00 01 11 10

1
0 X 1 1 X
0 0 1 X X
X X X X
1 X 1 1 X
1 1
1 X X
J3 = Q2Q1 K2 = Q1 J1 = 1

Q2Q1 Q2Q1 Q2Q1

Q3 00 01 11 10 Q3 00 01 11 10 Q3 00 01 11 10

0 X X X X 0 X X 1 0 1 X X 1
1
1 1
X X 1 1 1 X X 1
K3 = Q2Q1 K2 = Q1 K1 = 1
Q1 Q2 Q3
(1)

FF1 FF2 FF3

DESIGN 3 BIT UP DOWN COUNTER USING T FLIP FLOP 20
Present State Next State
 Design synchronous counter for sequence:
0 → 1 → 3 → 4 → 5 → 7 → 0, using T flip-flop.
q The sequence has six stable states 000, 001, 011, 100. 101, 111.
q Number of FF requires are 3.
q The state 010, and 110 (2 & 6) are not appearing

Present State Next State Input table of Flip-Flops

Q3 Q2 Q1 Q3(t+1) Q2(t+1) Q1(t+1) T3 T2 T1

0 0 0 0 0 1 0 0 1

0 0 1 0 1 1 0 1 0

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 1 0 1 0

1 1 1 0 0 0 1 1 1
 Q2Q1 Q2Q1

10 Q3 00 01 11 10
Q3 00 01 11

0 0

1 1

T3 = Q2 T2 = Q1

Q2Q1
Q3 00 01 11 10

T1 T2 Q2 T3 Q3
T1 = Q2’ Q1

Q1’ Q2’ Q3’

CLK
 Ring Counter
q A ring counter is a special type of application of the Serial IN Serial OUT Shift register.
q The only difference between the shift register and the ring counter is that the last flip flop outcome is taken as
the output in the shift register.
q But in the ring counter, this outcome is passed to the first flip flop as an input. All of the remaining things in the
ring counter are the same as the shift register.
q The main point of this Counter is that it circulates a single bit(0/1) around the ring.
q The clock pulse (CLK) is applied to all the flip-flops simultaneously. Therefore, it is a Synchronous Counter.
q Also, here we use Overriding input (ORI) for each flip-flop. Preset (PR) and Clear (CLR) are used as ORI.
q When PR is 0, then the output is 1. And when CLR is 0, then the output is 0. Both PR and CLR are active low
signal that always works in value 0.
q PR = 0, Q = 1 CLR = 0, Q = 0
q R i n g c o u n te r s o f fe r s eve ra l
advantages, including simplicity
of design, compactness due to
the closed loop structure, and
the ability to generate
predictable sequences.
q They are well suited for
applications requiring repetitive
sequences, such as digital clocks,
LED displays, and control logic
in various systems.
 Twisted Ring Counter/ Johnson Counter
q Twisted ring counter is also known as a switch-tail ring counter or Johnson counter .
q In this the inverted output of the last stage flip flop is connected to the input of first flip flop.
q This is an advantage of the Johnson counter that it requires only half number of flip flops that of a ring
counter uses, to design the same Mod.
THANK YOU
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