CS232 Lecture Notes 5.

VHDL Fall 2021

VHDL (II)

A Full Adder in VHDL

- In this course, we use VHDL to assist our circuit design.
- So, if we have a more complex circuit, we can leverage some VHDL to help with the
validation.

- What is VHDL?
• An acronym for Very High Speed Integrated Circuit Hardware Description Language.
• A program language used to describe a logic circuit by function, data flow behavior, or
structure.

- What is GHDL?
• Like Java and C, VHDL programs need to be compiled before running.
• GHDL is a compiler for VHDL.
• GHDL is short for G Hardware Design Language. Currently, G has no meaning.

- How do you get VHDL and GHDL?

• The dwarves in the robotics lab have VHDL and GHDL ready for you to use.

- Now, let’s see how to use VHDL to describe the full adder we talked in last class.

-- Comments in VHDL start with --

-- Ying Li
-- A full adder

-- import useful packages

library ieee;
use ieee.std_logic_1164.all; -- provide enhanced signal types

-- filename must be the same as entity name

-- entity defines the inputs and outputs of the circuit
entity adder is
-- A, B, Ci are inputs
-- S and Co are the outputs
port (
A, B, Ci : in std_logic; -- std_logic represent one bit signal
S, Co: out std_logic -- that can take on the value 0 or 1
);
end adder;

-- architecture define the circuit

architecture behavior of adder is
begin
-- statements in the architecture enclosed by begin and end are executed concurrently
-- compute the sum
s <= A xor B xor ci; -- <= assign the result of A xor B xor ci to s
-- compute the carry
co <= (A and B) or ((a xor b) and ci); -- VHDL is case-insensitive
end behavior;

-- to analyze this design, using ghdl -a adder.vhd 1

CS232 Lecture Notes 5. VHDL Fall 2021

- The above code is in a file named adder.vhd.

- It describes the full adder circuit with 3 inputs, 2 outputs, two XOR gates, two AND gates, and
one OR gate.
- To compile the program, use the command ghdl -a adder.vhd
• -a means analysis

- Now, we need a test program for the circuit so that we can tell whether the circuit works
correctly.

-- Ying Li
-- A testbench for the full adder

library ieee;
use ieee.std_logic_1164.all;

-- A testbench has no ports

entity addertest is
end addertest;

architecture behavior of addertest is

-- Declaration of the component that will be instantiated
component adder
port (
A, B, Ci: in std_logic;
S, Co: out std_logic
);
end component;

-- the adder signals

signal I0, I1, I2, O0, O1 : std_logic;

begin
-- component instantiation
-- connect the inputs and outputs of the entity to the local signals
adder1 : adder port map (A=>I0, B=>I1, Ci=>I2, Co=>O0, S=>O1);

I0 <= '0', '1' after 4 ns; -- send signals to port a, the signal is 0 in the first 4 ns
and 1 afterward
I1 <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 6 ns;
I2 <= '0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns, '0' after 4 ns, '1' after 5
ns, '0' after 6 ns, '1' after 7 ns, '0' after 8 ns;

end behavior;

- The above code is in a file named addertest.vhd

- The testbed gives three inputs signals to the three inputs of the full adder. In the first 8 ns, the
first input has value 0 during the first 4 ns and 1 afterward. The second input starts with 0 and
varies the value every 2 ns. The third input starts with 0 and varies the value every ns.

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CS232 Lecture Notes 5. VHDL Fall 2021

- We need to compile the program using ghdl -a addertest.vhd

- Then, elaborate the testbench: ghdl -e addertest
• This step may not generate output files on some platforms.
- The last step is to run the test program using ghdl -r addertest —-vcd=adder.vcd
- This step will generate an adder.vcd file. You can use gtkwave to open the vcd file and
valid the correctness of the full adder behavior.

- Open the adder.vcd file using gktwave, you will get a window like this

- Select the all the signals and click “Insert”, then click the “Zoom Fit” button. You will get a
window like this. The green signals can help us to validate the full adder.

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CS232 Lecture Notes 5. VHDL Fall 2021

Two-Bit Adder
- Design a circuit that takes two 2-bit inputs as unsigned binary sequences, add them, and
generate a 3-bit outputs.
- We can design the circuit using gates like what we did for the full adder, but we can also
leverage the numeric_std library to simplify the process.

• numeric_std library provides numeric types (signed/unsigned) and arithmetic functions.

- We need a vhd file describe the circuit for 2-bit adder, twoBitAdder.vhd

-- Ying Li

-- A circuit that takes two 2-bit inputs and generate a 3-bit output

-- import useful packages

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all; -- provides numeric types (unsigned/signed) and arithmetic

functions

-- filename must be the same as entity name

-- entity defines the inputs and outputs of the circuit

entity twoBitAdder is

-- A and B are an array of inputs

-- F is an array of outputs

port (

A, B: in unsigned (1 downto 0); -- array/vector of unsigned type

F: out unsigned (2 downto 0)

);

end twoBitAdder;

-- architecture define the circuit

architecture behavior of twoBitAdder is

begin

-- extend both 2-bit inputs to 3-bit inputs and then do the addition

F <= ('0' & A) + ('0' & B);

end behavior;

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CS232 Lecture Notes 5. VHDL Fall 2021

- To test this circuit, we also need a test file, twoBitAdderTest.vhd.

-- Ying Li
-- A testbench for the 2bitAdder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- A testbench has no ports

entity twoBitAdderTest is
end entity;

architecture behavior of twoBitAdderTest is

-- Declaration of the component that will be instantiated
component twoBitAdder
port (
A, B: in unsigned (1 downto 0); -- array/vector of unsigned
F: out unsigned (2 downto 0)
);
end component;

-- the twoBitAdder signals

signal I0, I1: unsigned (1 downto 0);
signal O: unsigned (2 downto 0);
constant num_iterations: integer := 4;

begin
-- component instantiation
-- connect the inputs and outputs of the entity to the local signals
twoBitAdder1 : twoBitAdder port map (A=>I0, B=>I1, F=>O);

I0(1) <= '0', '1' after 8 ns;

I0(0) <= '0', '1' after 4 ns, '0' after 8 ns, '1' after 12 ns;

process begin
for i in 1 to num_iterations loop
I1(1) <= '0';
wait for 2 ns;
I1(1) <= '1';
wait for 2 ns;
end loop;
wait;
end process;

process begin
for i in 1 to num_iterations loop
I1(0) <= '0';
wait for 1 ns;
I1(0) <= '1';
wait for 1 ns;
I1(0) <= '0';
wait for 1 ns;
I1(0) <= '1';
wait for 1 ns;
end loop;
wait;
end process;

end behavior;

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CS232 Lecture Notes 5. VHDL Fall 2021

- Then, compile and run the code

- We can get a gtkwave file like this to demonstrate the correctness of the circuit.

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CS232 Lecture Notes 5. VHDL Fall 2021

Test the twoBitAdder using Counter

- Now we know how to test a circuit using process and signal assignment to simulate
the input signals.
- We can also use a counter to generate the signals for inputs of the tested circuit.
- Here is a revised counter.vhd file.

-- Quartus II VHDL Template

-- Binary Counter
-- modified by Ying Li

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is

port
(
clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
q: out std_logic_vector (1 downto 0) -- array/vector of std_logic
);

end entity;

architecture behavior of counter is

signal cnt: unsigned (1 downto 0);

begin

process (clk)
begin
if reset = '1' then
-- Reset the counter to 0
cnt <= "00";
elsif (rising_edge(clk)) then
if enable = '1' then
-- Increment the counter if counting is enabled
cnt <= cnt + 1;
end if;
end if;
end process;

q <= std_logic_vector(cnt);

end behavior;

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CS232 Lecture Notes 5. VHDL Fall 2021

- The twoBitAdder.vhd is the same as the previous sample code.

-- Ying Li
-- A circuit that takes two 2-bit inputs and generate a 3-bit output

-- import useful packages

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- provides numeric types (unsigned/signed) and arithmetic
functions

-- filename must be the same as entity name

-- entity defines the inputs and outputs of the circuit
entity twoBitAdder is
-- A and B are an array of inputs
-- F is an array of outputs
port (
A, B: in unsigned (1 downto 0); -- array/vector of unsigned type
F: out unsigned (2 downto 0)
);
end twoBitAdder;

-- architecture define the circuit

architecture behavior of twoBitAdder is
begin
-- extend both 2-bit inputs to 3-bit inputs and then do the addition
F <= ('0' & A) + ('0' & B);
end behavior;

- In the twoBitAdderTest.vhd, we want to use counter. So, there are two components
in this test file: one for twoBitAdder, and the other for counter.vhd.
- We want each input of the twoBitAdder get signals from a counter, so we instantiate
two counter instances (counter1 and counter2).
- We then map the ports of the two counters to the local signals, and assign the two
counter outputs to the two inputs of the twoBitAdder.
• Please note that if the local signals have the same names as the component ports,
we can simplify the port map as counter1: counter port map (clk, reset, enable,
unsigned(q)=>I0); No => needed here.
• We use a type casting here. q is a std_logic_vector, and I0 is unsigned array,
although they have the same size. So, we type cast q to an unsigned array here to
make the assignment happen.
- Finally, we set the reset, enable, and clk signals appropriately, so that the counters
can work.

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CS232 Lecture Notes 5. VHDL Fall 2021

-- Ying Li
-- A testbench for the 2bitAdder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- A testbench has no ports

entity twoBitAdderTest is
end entity;

architecture behavior of twoBitAdderTest is

-- Declaration of the component that will be instantiated
component twoBitAdder
port (
A, B: in unsigned (1 downto 0); -- array/vector of unsigned
F: out unsigned (2 downto 0)
);
end component;

-- counter is used to generate signals for the two inputs of the twoBitAdder
component counter
port (
clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
q: out std_logic_vector (1 downto 0)
);
end component;

-- the twoBitAdder signals

signal I0, I1: unsigned (1 downto 0);
signal O: unsigned (2 downto 0);

-- the counter signals

signal clk: std_logic;
signal enable: std_logic;
signal reset: std_logic;
signal q: std_logic_vector (1 downto 0);

constant num_cycles : integer := 6;

begin
-- component instantiation
-- connect the inputs and outputs of the entity to the local signals
twoBitAdder1 : twoBitAdder port map (A=>I0, B=>I1, F=>O);
counter1: counter port map (clk, reset, enable, unsigned(q)=>I0);
counter2: counter port map (clk, reset, enable, unsigned(q)=>I1);

-- start off with a short reset

reset <= '1', '0' after 1 ns;
enable <= '1';

-- create a clock
process begin
for i in 1 to num_cycles loop
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;

end behavior;

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CS232 Lecture Notes 5. VHDL Fall 2021

- After compiling the code, we can get a gtkwave like this.

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