Bhoj Reddy Engineering College for Women

IV B Tech I Sem Objective Question Bank

Branch and Section: ECE A, B & C Subject: VLSI Design
Units I and II
Choose the correct alternative:

1. In CMOS logic circuit the p-MOS transistor acts as [ ]

a) Pull down network b) Pull up network

c) Load d) Short to ground

2. In CMOS logic circuit, the switching operation occurs because [ ]

a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON
simultaneously for input ‘1’

b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF
simultaneously for input ‘1’

c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-
MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’

d) None of the mentioned

3. nMOS devices are formed in [ ]

a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level

4. In depletion mode, source and drain are connected by [ ]

a) insulating channel b) conducing channe lc) Vdd d) Vss

5. The condition for non-saturated region is [ ]

a) Vds = Vgs – Vt b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt d) Vds greater than Vgs – Vt

6. In enhancement mode, device is in _________ condition [ ]

a) conducting b) non conducting c) partially conducting d) insulating

7. The condition for non-conducting mode is [ ]

a) Vds lesser than Vgs b) Vgs lesser than Vds

c) Vgs = Vds = 0 d) Vgs = Vds = Vsb = 0

8. The condition for linear region is [ ]

a) Vgs lesser than Vt b) Vgs greater than Vt
c) Vds lesser than Vgs d) Vds greater than Vgs

9. As source drain voltage increases, channel depth [ ]

a) increases b) decreases

c) logarithmically increases d) exponentially increases

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10. MOS transistors consists of [ ]
a) diffusion layer b) metal layer
c) layer of silicon-di-oxide d) all of the mentioned

11. In MOS transistors, _____ is used for their gate [ ]

a) metal b) silicon-di-oxide c) polysilicon d) gallium

12. The gate region consists of [ ]

a) insulating layerb) conducting layerc) lower metal layerd) p type layer

13. Electrical charge flows from [ ]

a) source to drain b) drain to source c) source to groundd) source to gate

14. Source in NMOS transistors is doped with ______ material [ ]

a) n-type b) p-type c) n & p type d) none

15. In N channel MOSFET which is the more negative [ ]

a) source b) gate c) drain d) source and drain

16. If the gate is given sufficiently large charge, electrons will be attracted to [ ]

a) drain region b) channel region c) switch region d) bulk region

17. Enhancement mode NMOS acts as ____ switch, depletion mode acts as _____ switch if
Vin=0 [ ]
a) open, closed b) closed, open c) open, open d) close, close

18. Depletion mode MOSFETs are more commonly used as [ ]

a) switches b) resistors c) buffers d) capacitors

19. The design flow of VLSI system is [ ]

1. architecture design 2. market requirement 3. logic design 4. HDL coding
a) 2-1-3-4b) 4-1-3-2c) 3-2-1-4d) 1-2-3-4

20. nMOS fabrication process is carried out in [ ]

a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals

21. The photoresist layer is exposed to [ ]

a) visible lightb) ultraviolet lightc) infra red lightd) LED

22. The commonly used bulk substrate in SOI fabrication is [ ]

a) silicon crystalb) silicon-on-sapphirec) phosphorus d) silicon-di-oxide

23. Heavily doped polysilicon is deposited using [ ]

a) chemical vapour decomposition b) chemical vapour deposition
c) chemical deposition d) dry deposition

24. CMOS technology is used in developing [ ]

a) microprocessors b) microcontrollers
c) digital logic circuits d) all of the mentioned

25. CMOS has [ ]

a) high noise margin b) high packing density
c) low power dissipation d) high complexity

26. P-well is created on [ ]

a) p subtrateb) n substratec) p & n substrated) none

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27. Which type of CMOS circuits are good and better? [ ]
a) p wellb) n wellc) all of the mentionedd) none of the mentioned

28. What is the disadvantage of MOS device? [ ]

a) limited current sourcing b) limited voltage sinking
c) limited voltage sourcing d) unlimited current sinking

29. What are the advantages of BiCMOS? [ ]

a) higher gain b) high frequency characteristics
c) better noise characteristics d) all of the mentioned

30. What are the features of BiCMOS ? [ ]

a) low input impedance b) high packing density
c) high input impedance d) high output drive current

31. Lithography is: [ ]

a) Process used to transfer a pattern to a layer on the chip

b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip

32. Silicon oxide is patterned on a substrate using: [ ]

a) Physical lithography b) Photolithography
c) Chemical lithography d) Mechanical lithography

33. The ______ is used to reduce the resistivity of poly silicon: [ ]

a) Photo resistb) Etchingc) Doping impuritiesd) None of the mentioned

34. The chemical used for shielding the active areas to achieve selective oxide growth is:
[ ]
a) Silver Nitrideb) Silicon Nitridec) Hydrofluoric acidd) Polysilicon

35. Ids can be given by [ ]

a) Qc x Ʈb) Qc / Ʈ c) Ʈ / Qcd) Qc / 2Ʈ

36. Transit time can be given by [ ]

a) L / v b) v / L c) v x L d) v x d

37. Velocity can be given as [ ]

a) µ / Vds b) µ / Eds c) µ x Eds d) Eds / µ

38. Eds is given by [ ]

a) Vds / L b) L / Vds c) Vds x L d) Vdd / L

39. Mobility of proton or hole at room temperature is [ ]

a) 650 cm2/V sec b) 260 cm2/V sec

c) 240 cm2/V sec d) 500 cm2/V sec

40. In resistive region [ ]

a) Vds greater than (Vgs – Vt)b) Vds lesser than (Vgs – Vt)
c) Vgs greater than (Vds – Vt)d) Vgs lesser than (Vds – Vt)

41. Threshold voltage is negative for [ ]

a) nMOS depletion b) nMOS enhancement
c) pMOS depletion d) pMOS enhancement

42. The current Ids _______ as Vds increases in saturation region. [ ]

a) increases b) decreases

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 c) remains fairly constant d) exponentially increases

43. In linear region, ______ channel exists [ ]

a) uniformb) non-uniformc) wided) uniform and wide

44. When the channel pinches off? [ ]

a) Vgs>Vds b) Vds>Vgs c) Vds>(Vgs-Vth) d) Vgs>(Vds-Vth)

45. MOSFET is used as [ ]

a) current source b) voltage source c) buffer d) divider

46. According to body effect, substrate is biased with respect to [ ]

a) source b) drain c) gate d) Vss

47. Increasing Vsb, _______ the threshold voltage [ ]

a) does not effect b) decreases c) increases d) exponentially increases

48. Transconductance gives the relationship between [ ]

a) input current and output voltage
b) output current and input voltage
c) input current and input voltage
d) output current and output voltage

49. Stick diagrams are those which convey layer information through
a)thickness b)color c)shapes d)layers [ ]

50. Which color is used for n-diffusion?

a)red b)blue c)green d)yellow [ ]

51. Which color is used for implant?

a) red b) blue c) green d) yellow [ ]

52. Which color is used for contact areas?

a) red b) brown c) black d) blue [ ]

53. Which color is used for polysilicon?

a) brown b) red c) white d) orange [ ]

54. Which color is used for buried contact? [ ]

a) black
b) white
c) green
d) brown

55. n and p transistors are separated by using [ ]

a) differentiation line
b) separation line
c) demarcation line
d) brown line

56. _______ layer should be over ______ layer [ ]

a) ntype, polysilicon b) polysilicon, ntype c) None d) both

57. Implant is represented using [ ]

a) black, dark line b) black, dotted line c) yellow, dark line d) yellow, dotted line

58. Metal1 and Metal2 are connected through a [ ]

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 a) contact cut

b) electrical contact

c) Via

d) cross contact

59. Design rules does not specify [ ]

a) line widths
b) separations
c) extensions
d) colours

60. The width of n-diffusion and p-diffusion layer should be [ ]

a) 3λ
b) 2λ
c) λ
d) 4λ

61. What should be the spacing between two diffusion layers? [ ]

a) 4λ
b) λ
c) 3λ
d) 2λ

62. What should be the width of metal 1 and metal 2 layers? [ ]

a) 3λ, 3λ
b) 2λ, 3λ
c) 3λ, 4λ
d) 4λ, 3λ

63. Implant should extend _______ from all the channels [ ]

a) 2λ
b) 3λ
c) 4λ
d) λ

64. Which type of contact cuts are better? [ ]

a) buried contacts
b) butted contacts
c) butted & buried contacts
d) none of the mentioned

65. Which gives scalable design rules? [ ]

a) lambda rules
b) micron rules
c) layer rules
d) thickness rules

66. Diffusion and polysilicon layers are connected together using [ ]

a) butting contact
b) buried contact
c) both a and b
d) cannot be connected

67. Which is more complex process? [ ]

a) buried contact
b) butting contact

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 c) buried & butting contact
d) none of the mentioned

68. Which contact cut occupies smaller area? [ ]

a) buried contact
b) butting contact
c) buried & butting contact
d) none of the mentioned

69. Which layer is used for power and signal lines? [ ]

a) metal
b) polysiicon
c) n-diffusion
d) p-diffusion

70. Minimum n-well width should be ____ [ ]

a) 2λ
b) 6 λ
c) 12 λ
d) 11 λ

71. Advantages of design rules are [ ]

a) durable
b) scalable
c) portable
d) all of the mentioned

72. Contact cuts should be ____ apart [ ]

a) 2λ
b) 3λ
c) 4λ
d) λ

73. Which has higher Rs values? [ ]

a) n-diffusion
b) p-diffusion
c) both of the mentioned
d) none of the mentioned

74. A feature size square has [ ]

a) L > W
b) W > L
c) L = W
d) L > d

75. What is the transition point of an inverter? [ ]

a) Vdd
b) 0.5 Vdd
c) 0.25 Vdd
d) 2 Vdd

Fill in the Blanks

1. Transconductance can be increased by ___________________

2. Increasing the transconductance ____________________

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3. Ids is _______ to length L of the channel

4. Switching speed of a MOS device depends on ___________________

5. A fast circuit requires ______________________

6. Inverters are essential for ___________________

7. In basic inverter circuit, ______ is connected to ground

8. In inverter circuit, ________ transistors is used as load

9. For depletion mode transistor, gate should be connected to______

10. In nMOS inverter configuration depletion mode device is called as _____

11. The ratio of Zp.u/Zp.d in NMOS inverter is given by ______

12. Pass transistors are transistors used as __________________

13. An inverter driven through one or more pass transistors has Zp.u/Zp.d ratio of
____________________

14. In depletion mode pull-up, dissipation is high since current flows when

_____________

15. CMOS inverter has ______ regions of operation

16. If n-transistor conducts and has large voltage between source and drain, then it is said to be
in _____ region

17. If p-transistor is conducting and has small voltage between source and drain, then the it is
said to work in ____________________

18. In the region where inverter exhibits gain, the two transistors are in _______ region

19. If both the transistors are in saturation, then they act as______________

20. If βn = βp, then Vin is equal to ________________

21. Mobility depends on ______________

22. CMOS inverter has ______ output impedance

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23. Input resistance of CMOS inverter is ______________

24. In CMOS logic circuit the n-MOS transistor acts as _____________

25. ______________ is the process of translating an abstract form of desired circuit behaviour
into a design implementation in terms of logic gates.

26. Logic optimization aims at __________ of silicon area.

27. __________ is the process of verifying the logical correctness of a hardware design.

28. __________ is group of standard cells glued together as a package.

29. The basic idea of_________ is to reduce the dimensions of MOS transistors and wires
connecting them.

30. _________ allows the description of the structure of the hardware system.

31. The optimization targets of logical synthesis are __________

32. The ____________ acts as an interface between symbolic circuit and actual layout.

33. When two or more sticks of different type cross each other there is electrical contact.
(True/false)

Solutions:

1 a 19 a 37 c 55 c 73 b

2 c 20 a 38 a 56 b 74 c

3 c 21 b 39 c 57 d 75 b

4 b 22 b 40 b 58 c

5 c 23 b 41 a 59 d

6 b 24 d 42 c 60 b

7 d 25 b 43 a 61 d

8 b 26 b 44 c 62 c

9 a 27 b 45 a 63 a

10 d 28 a 46 c 64 a

11 c 29 a 47 c 65 a

12 b 30 d 48 b 66 c

13 a 31 a 49 d 67 d

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 14 a 32 b 50 c 68 a

15 a 33 c 51 d 69 a

16 b 34 a 52 c 70 c

17 a 35 b 53 b 71 d

18 b 36 a 54 d 72 a

Fill in the Blanks:

1 increasing ids or 12 Switches connected 23 high

decreasing vgs in series

2 Decreases area 13 8:1 24 Pull down transisitor

3 Inversly proportional 14 Both MOS on 25 Synthesis

4 Gate voltage above 15 5 26 Reduction

threshold

5 High gm 16 Saturation 27 Simulation

6 For all digital circuits 17 non Saturated 28 ASIC Library

7 source 18 Saturated 29 Scaling

8 Depletion mode 19 Current source 30 HDL

9 source 20 Vin=0.5VDD 31 Speed, Area, Power

10 Pull up 21 Transverse electric 32 Stick Diagram

field

11 4:1 22 low 33 False

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