Glossary of Acronyms High Performance Protection Switching for Legacy

Ring and Mesh Transport Networks

ADM— Add-Drop Multiplexer

APS/MSP— Automatic Protection

By Partha Srinivasan and Rajashree Mungi
Switching, Multiplex Section Protection
High performance, deterministic protection switching is a key
BLSR/MS-SPRing— Bi-Directional Line requirement of evolving transport networks. Maintaining the standard
Switched Ring, Manual Switch, Shared
Section Protection Ring
performance levels as networks scale in size has proven difficult.
Stacked ring implementations add further performance challenges. The
DWDM— Dense Wavelength Division
combination of a centralized architecture and an SoC implementation
Multiplexing has been demonstrated to far exceed the 50 ms protection switching
specification. In addition, the performance is maintained as the
FM— Fault Management Block protection events scale in number of signals switched for common ring
implementations. Bandwidth-efficient mesh topologies also are slowly
GFP— Generic Framing Procedure gaining momentum, and they pose their own set of performance issues.
Standard mesh networks typically experience non-deterministic or
HAL— Hardware Access Layer degraded performance or both as new connections are added, or failure
events result in a high number of connections being re-routed. The
I/O— Input/Output centralized architecture approach considerably helps in this situation.

ITU— International Telecommunications

Union

MSPP— Multi-Service Provisioning Before delving deeper into how centralized architecture helps with
Platform overall protection switching performance, a brief overview of the
centralized architecture is provided (Figure 1). The basic goals of a
OC— Optical Carrier centralized architecture are to reduce the cost of network elements and
increase the performance. The specific implementation discussed here
OC-48 = 2.488 Gb/s combines an STS-1 cross-connect, line framers and tributary framers
onto a single VLSI chip. This integration reduces system cost by
OC-192 = 9.952 Gb/s removing functions of framing and overhead processing from the I/O
cards. It also simplifies the software effort by centralizing the
OC-768 = 39.680 Gb/s switching decisions and overhead processing to a single set of
redundant cards. As a result, the time required to detect network
PC— Personal Computer degradation, compute necessary actions and execute the switching
decision is substantially reduced.
SDH— Synchronous Digital Hierarchy,
fiber-optic transmission that can transport
digital signals with different capacities

SoC— System-on-a-Chip
Legacy Protection Switching Performance for
SONET— Synchronous Optical Network, Scaling Transport Networks
a standard for connecting fiber-optic
transmission systems
As shown in Figure 2, the protection switching software is
implemented as a simple state machine that applies to line and
SONET/SDH— Synchronous Optical
Network, Synchronous Digital Hierarchy tributary ports alike. This has the interesting effect of treating all
switching in a uniform matter once the failure has been detected. As a
STS-1— SONET basic transmission rate result, lines and tributaries can take on different protection methods,
of 51.84 Mb/s and from the perspective of the state machine, they are equivalent.
This builds an added layer of functionality into the system where for
UAPS— Unified Automatic Protection instance BLSR/MS-SPRing protection could be implemented on a
Switching tributary if desired. The SoC hardware provides interrupt notification
on failure events. It implements interrupt masking per event, and a
UPSR— Uni-directional Path Switched
Ring
single notification per event regardless of number of protection
instances. The SoC hardware interfaces through the HAL to the FM.
UPSR/SNCP— Unidirectional Path
Switched Ring, Sub-Network Connection
Protection

VLSI— Very Large-Scale Integration

XCA— Cross-Connect Agent

The FM handles hardware event notifications where it generates a single message per event with bitmap
indicating all affected paths. It leaves interrupt for specific event disabled until an explicit enable request is
received. Higher priority events can occur and will be serviced.

The UAPS module receives event notification from FM, performs protocol specific event processing
(BLSR/MS-SPRing, UPSR/SNCP, Linear APS/MSP) and determines the state machine specific action to
be performed. It then sends a single request notification to XCA with a set of state machine identifiers and
traffic requests.

Figure 1:
Centralized
architecture. As mentioned previously, the XCA is not aware of the
Click here to physical traffic topology. To complete the action, the
enlarge. HAL receives request from XCA, computes the new
hardware cross-onnect map, programs new hardware
cross connect map, and re-enables the event interrupt.

We created a test bed to measure the performance of the architecture which is shown in figure 3. It consists
of three SONET/SDH single-card ADMs built around the SoC technology. These cards are interconnected
in a 2-fiber BLSR/MS-SPRing. Gigabit Ethernet traffic is generated using PCs and adapted to the SONET
framing using GFP.

Using the centralized architecture and SoC implementation described, the protection switching times for a
3-node local BLSR occurs in 5 ms. This is of course on a small local ring, but nevertheless the performance
is quite favorable. The ITU and Telcordia specifications call for a maximum of 50 ms in a 1200 km ring
with 16 nodes. The calculations for scaled-up performance are as follows. Using a measured pass-through
node’s transit time of 1 ms, a real-world propagation delay of 6 ms for 1200 km of fiber, and switching-
node switching time of 4 ms, we reach the following performance estimates:

Figure 2. • Recovery for a 16-node, 1200 km ring with uni-

Protection
switching
directional failure assuming the signal traverses 14
implementation. nodes, requires 14 transit delays of 1 ms, two ring
Click here to traverses of 6 ms, and switching time of 4 ms for a
enlarge. total of 28 ms. • Recovery for a 16-node, 1200 km
ring with bi-directional failure requires no ring
traverse for a total of 18 ms.

For stacked rings, performance is often affected when

multiple failures occur simultaneously. This is a common risk when implementing stacked rings over a
shared DWDM span, where the failure of a single fiber can affect multiple rings simultaneously. We have
measured an additional 2.5 ms for seven additional stacked rings in our laboratory environment for a total
time of 7.5 ms for eight stacked rings in a local 3-node configuration. This multi-event protection
performance is an inherent capability of the centralized architecture and the software design.
UPSR protection has been measured at 2.8 ms for a single path failure event. There are two cases of
performance scalability that we have analyzed. The first is that of multiple simultaneous UPSR events. We
examined the case of 48 simultaneous path failure events, which resulted in a protection time measured at
4.8 ms. Approximately 1.5 ms of this is attributable to cross-connect algorithm.

Figure 3.
Protection
switching Latency through an idle system (implying no pending
test protection event) is the transit time of one
environment.
Click here to
event/message sequence through the above processes
enlarge.
along with associated program logic. Examining the
software architecture shown in Figure 2, 2.8 ms
represents one full transit of the software. The failure
events occurring when interrupts are disabled have a
maximum latency of 2x the latency of an idle system
which provides an upper bounds for the second
scalability challenge — that of a series of protection events arriving in unpredictable intervals. Scalability
is independent of failure event rate with the upper bounds for this class of events being two cycles or 5.6
ms.

Enabling efficient Mesh topologies with deterministic performance

We can now turn our attention to SONET mesh, which is a logical extension of SONET BLSR combined
with bandwidth efficiencies of mesh networks. Mesh networks are gaining momentum but at a slow pace
mainly because of performance concerns. The proposed SONET mesh architecture allows network
designers to separate the physical topology from the restoration architecture, resulting in much more
efficient, less complex networks that are simpler to design, easier to maintain and fully SONET reliable.

Physical networks are very rarely built as a series of rings. Fiber routes follow more organic routes where
rights-of-way exist along highways, under sidewalks, along railroad tracks, and on telephone poles (see
Figure 4a). These networks form physical meshes, on top of which physical rings are often designed.
Overlaying a physical ring network on a physical mesh network results in multiple elements at each node
and significant overbuilding of fiber facilities.

Figure
4a. A
physical SONET mesh architecture provides a more elegant solution,
mesh as it separates the physical mesh plane from the SONET
network.
Click
ring plane. To build a complex network, a provider merely
here to places a network element at each node and connects them
enlarge. with a single fiber pair running OC-48, OC-192, or OC-768
line rates (or their SDH equivalents.) Using the capabilities
discussed above, logical rings can be defined on top of the
physical mesh, either simply in the obvious voids or in other
logical patterns based on traffic demand (see Figure 4b).
Through the use of the centralized state-machine technology, these logical rings can share spans and
implement per-service protection. The size of these logical rings need not be specified at provisioning time.
In most cases, rings in the voids will result in a design flexible enough to handle any demand, requiring
little pre-planning and resulting in a balanced network.
 Figure
4b.
Logical As long as each ring in a SONET mesh architecture meets
rings the requirements of a standard BLSR — 6 nodes or less,
over a
physical
1200 km or less — the network can restore in 50 ms from
mesh. any combination of failures, so long as there is a single
Click failure per ring. This means that a SONET mesh network
here to
can recover at SONET rates from multiple network failures
enlarge.
— a clear advantage over span-based shared mesh protocols.
A SONET mesh network can even restore in 50 ms from a
complete node failure where the node supports multiple
rings. Using SONET for restoration in situations such as this guarantees reliability.

Conclusion

The combination of a centralized architecture and SoC implementation enables high and deterministic
protection switching performance. The architecture maintains performance levels as connections and
protection events scale. The demonstrated performance of this approach — 5 ms protection switching
performance for traditional UPSR/SNCP and BLSR/MS-SPRing — allows for a new evolution of
SONET/SDH MSPPs.

The SONET mesh architecture enables predictable, reliable and easy-to-operate networks. It can provide
the network efficiency, lower overall cost and planning simplicity typically provided by mesh networks,
plus reliable and deterministic restoration resembling legacy SONET protection architectures.

Scaling performance of legacy and new SONET/SDH protection mechanisms is critical to the deployment
of new services on next-generation transport networks, and a centralized architecture enables just that.