ASSIGNMENT ON MODES OF

TRANSFER
Submitted in the partial fulfilment of the requirement for the
award of degree of

BACHELOR OF TECHNOLOGY IN
COMPUTER SCIENCE
From
UNIVERSITY INSTITUTE OF ENGNEERING
AND TECHNOLOGY
KURURKSHETRA UNIVERSITY
KURUKSHETRA

Session 2019-2023
Submitted to: - Submitted By: -
Mr. Pankaj Chauhan Name: - Navneet
Assistant professor Roll No.: - 251902137
C.S.E. Department 3rd Year (V Semester)
  Programmed I/0:
Programmed input–output (also programmed input/output,
programmed I/O, PIO) is a method of data transmission, via
input/output (I/O), between a central processing unit (CPU)
and a peripheral device, such as a network adapter or a
Parallel ATA storage device. Each data item transfer is
initiated by an instruction in the program, involving the CPU
for every transaction. In contrast, in direct memory access
(DMA) operations, the CPU is uninvolved in the data transfer.

The term can refer to either memory-mapped I/O (MMIO) or

port-mapped I/O (PMIO). PMIO refers to transfers using a
special address space outside of normal memory, usually
accessed with dedicated instructions, such as IN and OUT in
x86 architectures. MMIO[1] refers to transfers to I/O devices
that are mapped into the normal address space available to the
program. PMIO was very useful for early microprocessors
with small address spaces, since the valuable resource was not
consumed by the I/O devices.
It is due to the result of the I/O instructions that are written in
the computer program. Each data item transfer is initiated by
an instruction in the program. Usually the transfer is from a
CPU register and memory. In this case it requires constant
monitoring by the CPU of the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does
not have direct access to the memory unit. A transfer from I/O
device to memory requires the execution of several
instructions by the CPU, including an input instruction to
transfer the data from device to the CPU and store instruction
to transfer the data from CPU to memory. In programmed I/O,
the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is a time consuming
process since it needlessly keeps the CPU busy

 Interrupt driven I/O:

Interrupt driven I/O is an alternative scheme dealing with I/O.
Interrupt I/O is a way of controlling input/output activity
whereby a peripheral or terminal that needs to make or receive
a data transfer sends a signal. This will cause a program
interrupt to be set. At a time appropriate to the priority level
of the I/O interrupt. Relative to the total interrupt system, the
processors enter an interrupt service routine. The function of
the routine will depend upon the system of interrupt levels and
priorities that is implemented in the processor. The
interrupt technique requires more complex hardware
and software, but makes far more efficient use of
the computer’s time and capacities. Figure 2 shows the simple
interrupt processing.
Figure 2: Simple Interrupt Processing

For input, the device interrupts the CPU when new data has
arrived and is ready to be retrieved by the system processor. The
actual actions to perform depend on whether the device uses I/O
ports or memory mapping.

For output, the device delivers an interrupt either when it is ready

to accept new data or to acknowledge a successful data transfer.
Memory-mapped and DMA-capable devices usually generate
interrupts to tell the system they are done with the buffer.
Here the CPU works on its given tasks continuously. When an
input is available, such as when someone types a key on the
keyboard, then the CPU is interrupted from its work to take care
of the input data. The CPU can work continuously on a task
without checking the input devices, allowing the devices
themselves to interrupt it as necessary.

Basic Operations of Interrupt

1. CPU issues read command.
2. I/O module gets data from peripheral whilst CPU does
other work.
3. I/O module interrupts CPU.
4. CPU requests data.
5. I/O module transfers data.
Interrupt Processing

1. A device driver initiates an I/O request on

behalf of a process.
2. The device driver signals the I/O controller
for the proper device, which initiates the
requested I/O.
3. The device signals the I/O controller that is
ready to retrieve input, the output is
complete or that an error has been
generated.
4. The CPU receives the interrupt signal on
the interrupt-request line and transfer
control over the interrupt handler routine.
5. The interrupt handler determines the cause
of the interrupt, performs the necessary
processing and executes a “return from”
interrupt instruction.
6. The CPU returns to the execution state
prior to the interrupt being signaled.
7. The CPU continues processing until the
cycle begins again.

Advantages & Disadvantages of Interrupt Drive I/O

Advantages - fast
- efficient
Disadvantages - can be tricky to write if using a low
level language
- can be tough to get various pieces
to work well together
 - usually done by the hardware
manufacturer / OS maker, e.g. Microsoft

Design Issues
There are 2 main problems for interrupt I/O, which are:
 There are multiple I/O modules, how should the
processor determine the device that issued the interrupt
signal?
 How does the processor decide which module to process

when multiple interrupts have occurred?

There are 4 main ways to counter these problems, which are:
 Multiple Interrupt Lines
 Software Poll

 Daisy Chain (Hardware Poll, Vectored)

 Bus Arbitration (Vectored)

These are known as the 4 general categories of techniques that

are commonly used in I/O interrupt.
Multiple Interrupt Lines
As the name suggests, we provide multiple interrupt lines
between the processor and the I/O modules. This allows
multiple modules to be handled at the same time. However, it
is not practical to assign many bus lines and processor pins to
interrupt lines. One of the reasons is that there might be more
than one I/O module attached to a single line. This defeats the
purpose of this technique. The 3 techniques of the latter are
usually used together with this technique to rectify its’
problems.
Software Poll
Whenever an interrupt is detected by the processor, it
branches to an interrupt service routine which will poll each
and every I/O module to determine the exact interrupting
module. The processor raises a poll which could be in the
form of a command line. Consequently, the address of the
respective I/O module which is interacted by the poll will be
placed on the address line. The module will respond positively
if it is responsible for setting the interrupt. On the other hand,
every I/O module has an addressable status register. This
register can be read by the processor to determine the
interrupting module. After that, the processor is then branched
to a specific device-service routine. The downside to this
techniques is that it is time consuming.
Daisy Chain (Hardware Poll, Vectored)
This is actually a hardware poll. The interrupt acknowledge
line is daisy chained to all the modules. Whenever there is an
interrupt, the processor send out an interrupt acknowledge
which will propagate throughout the series of I/O modules.
This process will continue until it reaches a requesting
module. The module will respond by placing a word on the
data lines. The word is known as vector. This vector can
either be the address of the module or a specific identifier.
The processor subsequently directs the module to its’ specific
device-service routine based on its’ vector. This technique is
also known as the vectored interrupt. It completely removes
the need for interrupt-service routine.
Bus Arbitration (Vectored)
The last method which also utilizes vectored interrupts is bus
arbitration. This method involves the I/O module gaining
control over the bus before requesting for the interrupt. This is
limited to only one module at a time. The processor sends an
acknowledge signal whenever it detects an interrupt. The
requesting module then places its’ vector on the data lines.
However, when there are multiple interrupts at a single time,
there will be a need to assign priorities. These 4 methods
have their own way of assigning priorities:
 Multiple Interrupt Lines: The processor picks the
interrupt line with highest priority.
 Software Poll: The priority is determined by the order in
which the modules are polled.
 Daisy Chain (Hardware Poll, Vectored): The priority is
determined by the order in which the modules are polled.
 Bus Arbitration (Vectored): Employs a priority scheme.
 Examples of Interrupt Structures
Intel 82C59A

Use of the 82C59A Interrupt Controller

 This is a type of interrupt controller/external interrupt

arbiter.
 Main purpose is for managing interrupts, especially

priorities.
  Contains an Interrupt Request (INTR) and Interrupt
Acknowledge (INTA) line.
 Connects to external device and then to Intel 80386,

allowing the handling of a variety of devices and priority

structures.
 A single 82C59A can connect up to eight I/O modules.

 Can be arranged in cascaded arrangement for up to 64

modules.
 It has 3 modes:

1. Fully nested: Interrupt request ordered based on priority.

2. Rotating: Some applications have equal priority. Thus, a
particular device has lowest priority in a group after
being serviced.
3. Special mask: Processor can inhibit interrupts from some
devices.
Intel 82C55A Programmable Peripheral Interface
 This is an I/O module used for programmable I/O and
interrupt-driven I/O along with 80386.
 In Figure 3, there are 24 I/O lines in the right hand side
which are programmable by 80386 with the control
register.
 The 24 lines are separated into three 8-bit groups (A, B
and C). The C group can be further separated into two 4
bit-groups which can carry status and control signals.
 At the left hand side, there is an 8-bit data bus used to
transfer control information to the control register.
 There are 2 address lines that specify 1 of the 3 I/O ports
or the control register.
 A transfer can be done when CHIP SELECT line and the
READ or WRITE line is enabled.
 The RESET line is used to initialize the module.
Figure 3: Intel 82C55A Programmable Peripheral Interface
 The processor uses the control

register to determine the mode of

the module.
 Usually in mode 0, the three 8-bit

ports (A, B and C) can be assigned

as input or output.
 C lines can be assigned as the

control lines for A and B.

 It can have 3 lines based on 2

principals: “handshaking” and

interrupt request.
 “Handshaking” includes the

DATA READY line for indicating

presence of data, and
ACKNOWLEDGE line to inform
the module whenever read or write Keyboard/ Display
processes are finished. Interface to 82C55A
 INTERRUPT REQUEST line is

tied back to the system bus.

 PRIORITY INTERRUPT and DAISY
CHAINING

Priority Interrupts | (S/W Polling and Daisy Chaining)

 Difficulty Level : Medium

 Last Updated : 08 Feb, 2018

In I/O Interface (Interrupt and DMA Mode), we have

discussed concept behind the Interrupt-initiated I/O.
To summarize, when I/O devices are ready for I/O transfer,
they generate an interrupt request signal to the computer. The
CPU receives this signal, suspends the current instructions it
is executing and then moves forward to service that transfer
request. But what if multiple devices generate interrupts
simultaneously. In that case, we have to have a way to decide
which interrupt is to be serviced first. In other words, we have
to set a priority among all the devices for systemic interrupt
servicing.
The concept of defining the priority among devices so as to
know which one is to be serviced first in case of simultaneous
requests is called priority interrupt system. This could be done
with either software or hardware methods.

SOFTWARE METHOD – POLLING

In this method, all interrupts are serviced by branching to the

same service program. This program then checks with each
device if it is the one generating the interrupt. The order of
checking is determined by the priority that has to be set. The
device having the highest priority is checked first and then
devices are checked in descending order of priority. If the
device is checked to be generating the interrupt, another
service program is called which works specifically for that
particular device.
The structure will look something like this-
if (device[0].flag)
device[0].service();
else if (device[1].flag)
device[1].service();
.
.
.
.
.
.
else
//raise error
The major disadvantage of this method is that it is quite slow.
To overcome this, we can use hardware solution, one of which
involves connecting the devices in series. This is called Daisy-
chaining method.

HARDWARE METHOD – DAISY CHAINING

The daisy-chaining method involves connecting all the

devices that can request an interrupt in a serial manner. This
configuration is governed by the priority of the devices. The
device with the highest priority is placed first followed by the
second highest priority device and so on. The given figure
depicts this arrangement.
WORKING:

There is an interrupt request line which is common to all the

devices and goes into the CPU.
 When no interrupts are pending, the line is in HIGH

state. But if any of the devices raises an interrupt, it

places the interrupt request line in the LOW state.
 The CPU acknowledges this interrupt request from the

line and then enables the interrupt acknowledge line in

response to the request.
 This signal is received at the PI(Priority in) input of

device 1.
 If the device has not requested the interrupt, it passes this

signal to the next device through its PO(priority out)

output. (PI = 1 & PO = 1)
 However, if the device had requested the interrupt, (PI

=1 & PO = 0)
 The device consumes the acknowledge signal and
 block its further use by placing 0 at its PO(priority
out) output.
 The device then proceeds to place its interrupt

vector address(VAD) into the data bus of CPU.

 The device puts its interrupt request signal in HIGH

state to indicate its interrupt has been taken care of.

NOTE: VAD is the address of the service routine which
services that device.
 If a device gets 0 at its PI input, it generates 0 at the PO

output to tell other devices that acknowledge signal has

been blocked. (PI = 0 & PO = 0)
Hence, the device having PI = 1 and PO = 0 is the highest
priority device that is requesting an interrupt. Therefore, by
daisy chain arrangement we have ensured that the highest
priority interrupt gets serviced first and have established a
hierarchy. The farther a device is from the first device, the
lower its priority.
BIBLIOGRAPHY:

 https://www.geeksforgeeks.org

 http://inputoutput5822.weebly.com/

 https://en.wikipedia.org/wiki/Wiki