Lecture 3

Design Abstractions

Design Abstractions
The Digital Design Flow

Raúl Camposano
Silvaco and Silicon Catalyst
[email protected]

Copyright ©2024 by Raúl Camposano, Antun Domic and Patrick Groeneveld

“Abstraction forces you to reach the
highest level of the basics.”
Alan Soffer, Abstract Expressionist
Outline
• HW / SW stack
• Wafer fabrication
• Design abstraction levels
• Layout
• Design rules
• Placement and Routing
• Optical proximity correction, mask data preparation
• Standard cell libraries, FPGA, technology mapping
• Logic synthesis
• High-Level Synthesis

April 9, 2024 Stanford EE292A Lecture 9 3

 Stacks

Simplified
general purpose computer Simplified ML Containerized
https://en.wikipedia.org/wiki/Operating_system

April 9, 2024 Stanford EE292A Lecture 9 4

 Semiconductor Design and Manufacturing
“Fabless” Semiconductor
Manufacturer Foundry

Wafer

Die
IDM Integrated Device EDA Tapeout Fab
Manufacturer

Package
April 9, 2024 Stanford EE292A Lecture 9 5
Simplified Fabrication Process (1)
Heat
1. Grow field oxide
ox. Thermal oxidation, 800o-1200o
Optical Lithography
p-type substrate Etch
UV ArF laser 193nm Wet Plasma
2. Etch oxide for pMOSFET Mask
ox.

Mask (pattern)
p-type substrate Photoresist
Heat Arsenic
3. Diffuse n-well Phosphorus
ox.

n-well Isotropic, high temp, not directional

p-type substrate

4. Etch oxide for nMOSFET

ox.
April 9, 2024 Stanford EE292A Lecture 9 6

n-well
p-type substrate

5. Grow gate oxide

ox.
p-type substrate

2. Etch oxide for pMOSFET

ox.

p-type substrate

3. Diffuse n-well
Simplified Fabrication Process (2)
ox.

n-well
p-type substrate

4. Etch oxide for nMOSFET Mask

ox.

n-well
p-type substrate
Heat
5. Grow gate oxide
Thermal oxidation
ox.

n-well
p-type substrate

6. Deposit polysilicon Silane SiH4 gas at 630° C

CVD (Chemical Vapor Deposition)
ox.

n-well
p-type substrate

7.AprilEtch
9, 2024polysilicon and oxide Stanford EE292A Lecture 9 7
ox.

n-well
p-type substrate

8. Implant sources and drains

5. Grow gate oxide
ox.

n-well
p-type substrate

6. Deposit polysilicon

Simplified Fabrication Process (3)

ox.

n-well
p-type substrate

7. Etch polysilicon and oxide Mask

ox.

n-well
p-type substrate

8. Implant sources and drains Masks

ox. Anisotropic, low temp, directional
n+ n+ p+ p+ n+ Arsenic or Phosporus
p-type substrate
n-well p+ Boron or Indium

9. Grow nitride
Low Pressure CVD (Chemical
ox.
n+ n+ p+ p+ Vapor Deposition) of Si3N4
n-well Insulate
p-type substrate

10. Etch
April 9, 2024 nitride Stanford EE292A Lecture 9 8

ox.
n+ n+ p+ p+
n-well
p-type substrate

11. Deposit metal

p-type substrate

8. Implant sources and drains

ox.
n+ n+ p+ p+
n-well
p-type substrate

9. Grow nitride

Simplified Fabrication Process (4)

ox.
n+
p-type substrate
n+ p+
n-well
p+

10. Etch nitride Mask

Mask
ox.
n+ n+ p+ p+
n-well
p-type substrate

11. Deposit metal Barrier Sputtering, accelerating ions towards the target
Masks Seed Sputtering
ox. Film Electroplating
n+ n+ p+ p+ CMP
n-well
p-type substrate

12. Etch metal Mask g g

d d s
s
ox.
n+ n+ p+ p+ n-channel p-channel
n-well
p-type substrate

April 9, 2024 Stanford EE292A Lecture 9 9

Metal Layers

BEOL - Back End Of Line

April 9, 2024 Stanford EE292A Lecture 9 10

Main Manufacturing Steps
• Lithography: Transfer pattern to wafer by exposing a thin uniform layer of
photo-resist on the wafer surface through a mask
• UV ArF laser 193nm
• EUV laser pulsed tin plasma 13.5nm
• Etch: Selectively removing unwanted material from the surface of the wafer,
wet- or plasma-etching
• Deposition: Films of the various materials are applied on the wafer, e.g,
oxide, metal
• Chemical Mechanical Polishing (CMP): Planarization technique that removes
unwanted material by polishing, leaving the wafer flat
• Implant: Accelerated ionized particles (dopants) are introduced into the
semiconductor
• Diffuse: Introduce particles (dopants) into the semiconductor by
concentration gradient at temperature
April 9, 2024 Stanford EE292A Lecture 9 11
Abstractions: The Magic of Design Automation
Language, DB, Representation Abstraction
SystemC Architecture, ISP
ip ip
SystemVerilog System High-Level
C++ ip Behavioral
VHDL
Verilog RTL Data Path, Controller
Liberty
VHDL-AMS Logic, FSM
LVF
VerilogA Circuit
SDF EDIF Switch Level
Spice Transistor
SPEF
Stick Diagram
OASIS Mask Physical
OpenAccess GDS II
Layout
NDM LEF/DEF Geometry
CIF

April 9, 2024 Stanford EE292A Lecture 9 12

Mask Physical Level
Layout, Geometry, Mask layout or design
1. Representation of the IC in terms of
planar geometry shapes
corresponding to the patterns on the
wafer, e.g., metal, oxide, implant, etc.
2. Tapeout is the final result of the
design process for integrated circuits
before it is sent for manufacturing.
Specifically, it is the point at which the
graphic for the photomasks of the
circuit is sent to the fabrication
facility.
OASIS Mask Physical
OpenAccess GDS II
Layout
NDM LEF/DEF Geometry
CIF

April 9, 2024 Stanford EE292A Lecture 9 13

Mask Physical Level Formats
OASIS Open Artwork System Interchange Standard, 2001, aimed at reducing file sizes (as compared to GDSII)
GDSII is a database binary file format which is the de facto industry standard for data exchange of integrated
circuit or layout artwork. Goes back to Calma, 1971
LEF Library Exchange Format models a library of cells geometrically
DEF Design Exchange Format models an IC layout using LEF, including the netlist
CIF Caltech Intermediate Format, goes back to Mead and Conway
OpenAccess open reference database for IC design, with a supporting standard API. Originally Cadence, now
supported by SI2

OASIS Mask Physical

GDS II
LEF/DEF
CIF

April 9, 2024 Stanford EE292A Lecture 9 14

Physical Design Styles
Standard Cell (digital) Custom (analog) System on a Chip (SOC)

GPU 1 & 2 GPU 3 & 4

Imagination PowerVR 7XT

https://en.wikipedia.org/
wiki/Integrated_circuit_design GPU 5 & 6

L3 Cache
4Mb

“Twister” CPU
L2

Dual Core
3Mb

FPGA
Source: Altera Corp.
April 9, 2024 Stanford EE292A Lecture 9 15
Design Rules
• Specify the allowed geometries in a given technology, e.g.,
• 28nm bulk CMOS ~2,500 design rules
• 12nm SoI CMOS ~5,000 design rules
• From very simple: distance, width, overlap
• To very complex: antenna, density, cross-coupling, voltage
dependent…
• Used by the Design Rule Checker

April 9, 2024 Stanford EE292A Lecture 9 16

Design Rule Example: Metal Space

L1

Condition: w < 0.09

e1.Length >= 0.07
e2.Length >= 0.07

DRCheck: not L1_Overlaps_T1 or

not L1_Overlaps_T2

April 9, 2024 Stanford EE292A Lecture 9 17

Physical Design Main Steps
Placement
ip ip
• Place the LUT / cells / transistors on the chip ip
System
• Optimizing
• Area RTL
• Wire length (delay)
• Critical net length (delay)
Circuit
• Preceded by floor planning, tentative placement

Physical
of larger blocks

Design
Mask
• Many algorithms [18, 19], e.g. min-cut, quadratic Physical
placement, force directed, density-based, …

April 9, 2024 Stanford EE292A Lecture 9 18

Physical Design Main Steps
Routing
• Design of the wires that connect components
• Using several levels of metal (2-15)
• Many cases: Global and detailed, channel, switchbox, power & ground, clock
tree, …
• Optimizing
• Area
• Wire length (delay)
• Critical net length (delay)
• Crosstalk
• Many algorithms [18, 20], e.g., graphs, iterative, Steiner-tree, line probe,
maze, …

April 9, 2024 Stanford EE292A Lecture 9 19

OPC
Optical Proximity Correction
• Photolithography enhancement technique to print features smaller than the
wavelength used (mostly 193nm)
Diffraction limit 𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 0.61 𝜆 Wavelength
Raleigh Criterion 𝑁𝐴 Numerical Aperture

The blue Γ-like shape is what chip

designers would like printed on the wafer,
in green is the shape after applying optical
proximity correction, and the red contour is
how the shape actually prints (quite close
to the desired blue target).

Source: Wikipedia

April 9, 2024 Stanford EE292A Lecture 9 20

Further Steps
Used in addition to OPC
• Immersion, refractive index of water ~ 1.4 air water

• Multiple exposure (requires coloring)

= +

April 9, 2024 Stanford EE292A Lecture 9 21

Further Steps: Mask Data Preparation
• Main task is fracturing
• Pattern file polygons are
fractured into primarily
Manhattan shapes
• Sorted and organized in a format
most suitable for the processing
tool
• E.g., single beam Variable Shape
Beam (VSB) tools can only
expose rectangular and
triangular shots
April 9, 2024 Stanford EE292A Lecture 9 22
Further Steps: Mask Data Preparation
• Multiple formats Mebes, JEOL, Toshiba, Hitachi…
• Manufacturing Rule Checks, metrology sites…
• Data explosion

April 9, 2024 Stanford EE292A Lecture 9 23

Circuit Level
Transistor Level
1. Mostly CMOS
2. Berkeley Short-channel Insulated
Gate FET (IGFET) Model (BSIM [12])
• About 100 basic parameters
• 100’s of additional parameters
• Asymmetric Rds
• Ionization
• Drain Leakage
• Tunneling Circuit
• High Speed RF
• Charge and capacitance Transistor
• Thermal noise, flicker
• Asymmetric Source/Drain
• Temperature
• Stress
• Well proximity

April 9, 2024 Stanford EE292A Lecture 9 24

Circuit Level
Stick diagram [13]
Close to actual layout
Metal
Contact
Poly
P Diffusion

PMOS Transistor

Circuit

Stick Diagram

April 9, 2024 Stanford EE292A Lecture 9 25

Circuit Level
Switch Level
1. Faster simulation than
circuit level
2. Includes delays
3. Symbolic switch level [10]

Circuit Switch Level

IRSIM [11] circuit model

April 9, 2024 Stanford EE292A Lecture 9 26

Circuit Level
Logic
1. Boolean logic circuit, a
diagram consisting of logic
gates such as AND, OR,
NOT, NAND, NOR , XOR,
XNOR

Logic, FSM
a
b Circuit
c
abc+d
d

April 9, 2024 Stanford EE292A Lecture 9 27

Circuit Level
Finite State Machine
1. Machine that is in exactly
one of a finite number of
states. It changes states as
a function of inputs and its
state.
2. Can be a sequencer,
microcontroller, … Logic, FSM
Circuit

t
z rese
s1

reset
start reset
rese
t
z res
et s2

April 9, 2024 Stanford EE292A Lecture 9 28

Circuit Level Languages
1. VerilogA [15], VHDL-AMS [14] are language extensions for Analog and
Analog-Mixed-Signal
2. Spice [17] netlist input (deck)
3. Liberty Format to describe library cells, particularly timing. Originally
Synopsys , now IEEE
4. LVF Liberty Variation Format, extension for on-chip, parametric, statistical
variations
5. SDF Standard Delay Format, IEEE standard 1497 for timing data
6. SPEF Standard Parasitic Exchange Format for parasitics of wires, IEEE 1481 Circuit
Output of Parasitic extraction, Input to Static Timing Analysis (post
layout)

April 9, 2024 Stanford EE292A Lecture 9 29

Logic Synthesis
• Combinational logic, “random” logic
ip ip
• Design blocks specific to a design are often ip
System
synthesized as random logic (as opposed to
data-path, IP) RTL

Logic Synthesis
• RTL languages imply the registers and memory
used, so only the combinational logic in between Circuit
is synthesized.
• Since large part of delays is in the wires, often Mask
combined with floor planning / placement Physical

April 9, 2024 Stanford EE292A Lecture 9 30

Logic Synthesis Main Steps
• Optimization
• 2-Level: Reduce-Expand-Irredundant
• N-level: Simplify-Remove-Factoring
• Algebraic optimization, kernels
• Don’t cares, observability, controllability
• SAT
• Peephole, heuristics…
• Technology mapping
• Standard cell library
• FPGA lookup tables

April 9, 2024 Stanford EE292A Lecture 9 31

Sequential Logic
• Finite State Machine Synthesis
• Control memory (read-only memory, ROM)
• Programmable Microcontroller
control program
reset
Compiler
next state
Debugger
t
z rese
s1

reset
control code
reset
addr Control
start rese
t
Micro control
z res
et ROM control in
s2
controller signals
in signals
reset

April 9, 2024 Stanford EE292A Lecture 9 32

Logic Synthesis
Technology mapping onto a standard cell library
Standard cell - Inverter • Logic gates INV, NAND, AND, NOR, OR, XOR, different
Vdd number of inputs, etc.
• Single height and double height
pMOS
Fixed height • Flip-flop, latch, scan, memory
7-12 tracks • Low power, high performance, high density…
nMOS • Contains typically hundreds to thousands of cells
GND • Cells are characterized once forever

April 9, 2024 Stanford EE292A Lecture 9 33

Logic Synthesis
Standard Cell Block
• Rows of abutting cells
• Power / GND / Clk rails
• Not full, empty places

April 9, 2024 Stanford EE292A Lecture 9 34

Logic Synthesis
Technology mapping onto FPGA LUT

R0

y = a’b’c’d’ + abcd + abc’d’

Mask 1000 0000 0000 1001

R15 R0

R15
https://www.altera.com/en_US/pdfs/literature/wp/wp-01003.pdf
April 9, 2024 Stanford EE292A Lecture 9 35
Logic Synthesis
Building the FPGA (Altera)

https://www.altera.com/en_US/pdfs/literature/wp/wp-01003.pdf
April 9, 2024 Stanford EE292A Lecture 9 36
Register-Transfer Level

VHDL
Verilog RTL Data Path, Controller

Register Transfer Level

• Abstraction of a synchronous
digital system in terms of
registers and operations

April 9, 2024 Stanford EE292A Lecture 9 37

Register-Transfer Level

RTL Data Path, Controller

Data Path
• Set of functional units that carry
a + Reg out data processing, typically
b
c
Mux
“n-bit wide”
clk
Controller, Control Logic, Sequencer
• A finite state machine that
FSM
controls the operation of the
data path
clk
April 9, 2024 Stanford EE292A Lecture 9 38
Register-Transfer Level Languages
Hardware Description Language (HDL)
1. VHDL - Very High Speed IC (VHSIC) HDL, IEEE standard 1076
2. Verilog, originally Cadence, IEEE standard 1364

VHDL [6]
Verilog [7, 8, 9] RTL

Verilog EE108 material [8, 9]

April 9, 2024 Stanford EE292A Lecture 9 39

High Level Synthesis
• Comparable to compiler code generation ip ip
System
• Main tasks ip

HLS
• Resource allocation, operators and memory
• Scheduling of operations, data access RTL
• Exploring (architectural) trade-offs
• Generating data path and control logic Circuit

Mask
Physical

April 9, 2024 Stanford EE292A Lecture 9 40

Example: Linear Classifier for 10 n-pixel images
𝑠𝑐𝑜𝑟𝑒 = 𝑊’𝑋’ + 𝑏’ 𝑠𝑐𝑜𝑟𝑒 = 𝑊𝑋

X’ = (x0, x1, x2,…xn-1) Image vector X = (x0, x1, x2,…xn-1, 1 )

𝑥00 … 𝑥0𝑛_1 𝑥00 … 𝑥0𝑛_1𝑏0

𝑊’ = Weight matrix 𝑊 =
𝑥90 … 𝑥9𝑛_1 𝑥90 … 𝑥9𝑛_1𝑏9

B’ = (b0, b1, b2,…b9) Bias vector

April 9, 2024 Stanford EE292A Lecture 9 41

Linear Classifier in C
images is a 28x28xN array (N images) of bytes (each pixel is 8 bit grayscale)
weights is a 28x28x10 array, holding the weights for each digit [0 – 9]
#define ARRAY_DIM 784 // Array dimension: 28*28 pixels
__kernel void
linearClassifier(const unsigned int imageNumber, // <-input
const unsigned char * __restrict images, // <-input: images
const float * __restrict weights, // <-input: char weights
unsigned char * __restrict guesses) // ->output: best guess
{
const int imageArrayIndex = imageNumber * ARRAY_DIM; // selects image in array
unsigned char bestGuess = 0;
float score[10] = {0.0}; // initializes the score for each option to 0.0

#pragma unroll 2 // Tells HLS to unroll the loop

for (int x = 0; x < ARRAY_DIM; x++) {
for (int i = 0; i < 10; i++) {
score[i] += images[imageArrayIndex + x] * weights[ (i*ARRAY_DIM) + x];
}
}

for (unsigned char i = 1; i < 10; i++) {

if (score[i] > score[bestGuess]) {
bestGuess = i; // remember highest score
}
}
guesses[imageNumber]
April 9, 2024
= bestGuess; // store guess as result for this image
Stanford EE292A Lecture 9 42
}
Scheduling and Allocation
1. Reset
2. Read (weights 0:7839)
3. REPEAT bufferi
0
4. Read (images index*784:index*784+783) 1
5. Score0=MAC (weight0, image) images Multiply
2
3
6. Score1=MAC (weight1, image) 4 guess
Add 5
7. ….
Array 6
8. Guess=MAX(Score0:Score9) weights 7
8
9. END 9
bufferw
score Max
images addr, reg
R/W
A B Point-to-Point weights addr,
A B C D R/W guess
Bus bufferi
R/W
index control bufferw index
score reg
A B C D NoC

April 9, 2024 Stanford EE292A Lecture 9 43

Using IP Blocks

bufferi
0
1
2
Multiply 3
images, weights USB USB 4 guess
PHY logic Add 5
Array 6
7
8
9
bufferw
score Max
images addr, reg
R/W
weights addr,
R/W guess
bufferi
index control bufferw R/W
index
score reg

April 9, 2024 Stanford EE292A Lecture 9 44

 System Level
SystemC [4] Architecture, ISP
ip ip
SystemVerilog [5] System High-Level
C++ ip Behavioral

Domain Specific: 1. Processors (ISP)

• Gem5 [23] is an open-source computer architecture • Programmer visible Instruction set
simulator used in academia and in industry. gem5 as opposed to implementation [2]
supports the Alpha, ARM, SPARC, MIPS, POWER, • Instruction set, organization and
RISC-V and x86 ISAs hardware [3]
• Halide [24] is a programming language designed to 2. Behavior of a system, independent of
make it easier to write high-performance image and implementation
array processing code 3. Block diagram
4. Interface Spec [3]

April 9, 2024 Stanford EE292A Lecture 9 45

Design
ip ip
System
ip

HLS
RTL

Synthesis
Logic
Circuit

Physical
Design
Mask Physical

Cerebras Wafer

April 9, 2024 Stanford EE292A Lecture 9 46

The Design Process
Check, analyze models Refine models
Verification ip Synthesis
ip
Goals: System Goals:
ip
• Correct? • Meet Constraints
• Constraints? • Optimize
RTL • Trade-off

What What
• Functionality • PPA: Performance , Power,
• Properties Circuit Area (Cost)
• PPA • NRE: Design effort
• Design Rules (geometry) • TTM: design time
• Litho Mask Physical • Yield / manufacturability,
• Electrical constraints, setup/hold… thermal, peak power,
• Thermal energy,…
• SW

April 9, 2024 Stanford EE292A Lecture 9 47

Main Design Steps
Formal Ver,
Simulation,
ip ip
Emulation System
ip

HLS
Formal Ver &
Simulation
RTL

Synthesis
Logic
checking
Equiv.
Static Timing
Analysis Circuit

Physical
Design
Extraction
, LVS

Circuit
Simulation Mask Physical

DRC, LVS, ERC

April 9, 2024 Stanford EE292A Lecture 9 48

Agile Hardware Development?
Waterfall Agile

Fully designed and verified models Incomplete prototypes that can be fabricated

Rigid, sequential methodology, specialist teams Collaborative, flexible teams

Improvement of the design Improvement of tools / generators

Follow a plan Respond to change

Long time to final design Short time to prototype, iterative improvement

April 9, 2024 Stanford EE292A Lecture 9 49

 Examples

Scala
C++
Chisel EDA
Verilog

Rocket
Core
Caches
SoC
Coprocessor EDA
Tiles
Peripherals

[21] Berkeley [22] Stanford

Scala: Programming language supporting OO and Halide: Programming language for writing digital image processing code using
functional programming memory locality, vectorized computation and multi-core CPUs and GPUs
Chisel: Constructing HW in a Scala embedded language CGRA: Coarse-Grained Reconfigurable Array
Rocket: Chip generator written in Chisel
April 9, 2024 Stanford EE292A Lecture 9 50
Summary
• Wafer fabrication involves Lithography, Etching, Deposition, Chemical Mechanical
Polishing, Ion Implantation

• Hardware design uses design abstractions; among the main uses are simulation
(“executing”) and synthesis (successive refinement)

• The main abstractions levels are System, RTL, Circuit and Physical

• Logic synthesis and physical design involve many steps that have been automated

• System level tradeoffs involve

• scheduling /allocating operations
• a memory architecture (storing/moving data)
• An Interconnect architecture (point-to-point, bus, NoC)
April 9, 2024 Stanford EE292A Lecture 9 51
References
1. Chip Manufacturing - How are Microchips made? | Infineon https://www.youtube.com/watch?v=bor0qLifjz4
2. J.L. Hennessy, D.A. Patterson, Computer Architecture a Quantitative Approach, Elsevier, 2007
3. D.P. Siewiorek, C. Bell, A. C. Newell, Computer Structures: Principles and Examples, McGraw-Hill, 1982
4. https://standards.ieee.org/standard/1666-2011.html
5. http://ieeexplore.ieee.org/document/6469140/
6. http://ieeexplore.ieee.org/document/4772740/
7. https://ieeexplore.ieee.org/document/1620780
8. https://web.stanford.edu/class/ee183/handouts_win2003/VerilogQuickRef.pdf
9. http://cva.stanford.edu/people/davidbbs/classes/ee108a/winter0607%20labs/ee108a_nham_intro_to_verilog.pdf
10. C.B.McDonald, R.E.Bryant, CMOS circuit verification with symbolic switch-level timing simulation, IEEE Transactions on
Computers, March 2001
11. A. Salz, M.A. Horowitz, IRSIM: An Incremental MOS Switch-level Simulator, DAC June 1989
12. http://bsim.berkeley.edu/models/bsim4

April 9, 2024 Stanford EE292A Lecture 9 52

References
13 C. Mead, L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980
14 http://ieeexplore.ieee.org/document/4384309/
15 http://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf
16 https://en.wikipedia.org/wiki/EDIF
17 https://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/UserGuide/description_fr.html
18 T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, John Wiley, 1994
19 I.L. Markov, J. Hu, M. Kim, Progress and Challenges in VLSI Placement Research, Proc. IEEE, Nov. 2015
20 L.K. Scheffer, L. Lavagno, G.Martin, Electronic Design Automation For Integrated Circuits Handbook, 2006
21 Yunsup Lee et.al., An Agile Approach to Building RISC-V Microprocessors, IEEE Micro, 2016
22 Rick Bahr et.al., Creating an Agile Hardware Design Flow, 2020 DAC
23 [26] N. L. Binkert, B. M. Beckmann, G. Black, S. K. Reinhardt, A. G. Saidi, A. Basu, J. Hestness, D. Hower, T. Krishna, S. Sardashti, R.
SenK. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The gem5 simulator,” SIGARCH Computer Architecture News, vol. 39,
no. 2, pp. 1–7, 2011. https://www.gem5.org
24 Jonathan Ragan-Kelley, Andrew Adams, Dillon Sharlet, Connelly Barnes, Sylvain Paris, Marc Levoy, Saman Amarasinghe, Frédo
Durand. Halide: decoupling algorithms from schedules for high-performance image processing, Communications of the ACM Vol.
61, No. 1

April 9, 2024 Stanford EE292A Lecture 9 53