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IEEE TRANSACTIONS ON ELECTRON DEVICES 1

Symmetric BSIM-SOI—Part I: A Compact Model

for Dynamically Depleted SOI MOSFETs
Chetan Kumar Dabhi , Member, IEEE, Dinesh Rajasekharan , Member, IEEE,
Girish Pahwa , Member, IEEE, Debashish Nandi , Graduate Student Member, IEEE,
Naveen Karumuri, Sreenidhi Turuvekere , Anupam Dutta, Balaji Swaminathan,
Srikanth Srihari, Yogesh S. Chauhan , Fellow, IEEE, Sayeef Salahuddin , Fellow, IEEE,
and Chenming Hu , Life Fellow, IEEE

Abstract— In this article, we present a symmetric

surface-potential-based model for dynamic depletion (DD)
device operation of silicon-on-insulator (SOI) FETs for RF
and analog IC design applications. The model accurately
captures the device behavior in partial depletion (PD) and
full depletion (FD) modes, as well as in the transition from
PD to FD, based on device geometry, doping, and bias con-
ditions. The model also exhibits an excellent source–drain
symmetry during dc and small-signal simulations, resulting
in error-free higher order harmonics. The model is fully
scalable with bias, temperature, and geometry and has
been validated extensively with real device data from the
industry. The symmetric BSIM-SOI model is developed in Fig. 1. (a) Schematic of a typical SOI MOSFET. (b) Cgg versus Vgb for
Verilog-A and compatible with all commercial SPICE simu- different substrate bias, the PD-to-FD transition is visible around Vgb =
lators, e.g., HSPICE, Spectre, and ADS. 0 V. Vb = 0V, Vd = 0 V, and Vs = 0 V.
Index Terms— Analog, BSIM-BULK, BSIM-silicon-on-
insulator (SOI), BSIM4, CMOS compact model, compact dynamic depletion (DD) region, where they could operate in
model, RF.
the partial depletion (PD) region, full depletion (FD) region,
or have a transition from PD to FD based on bias conditions,
I. I NTRODUCTION
silicon body doping, and geometry values [4], [5]. Fig. 1(a)
HE compact models are an essential part of process
T design kit (PDK) [1], which bridges the IC designer
and semiconductor foundry [2], [3], and hence IC designers
shows a typical SOI device structure where with different
combinations of body bias (Vb ) and substrate bias (Ve ), we can
make the device operate in different regions of operation.
demand fast and robust but reasonably accurate compact mod-
Fig 1(b) depicts that for Veb = −20 V, the device operates in
els, including the real device effects for IC simulation. Various
the PD region across Vgb . However, for Veb = 0 and 5 V, the
device models for silicon-on-insulator (SOI) devices have been
decrease in capacitance indicates that the device is in a transi-
developed over the past few decades [4], [5], [6]. The Compact
tion from PD to FD around Vgb = 0 V. The existing industry
Model Coalition (CMC) found several of the SOI models
standard BSIM-SOI model had been developed using the
useful for product design [7], [8], [9], [10], [11]. However,
threshold-voltage-based BSIM4 as a core model [7]. On top of
as device scaling continued, the silicon body thickness of the
it, the SOI device-specific effects were added, maintaining the
SOI devices was reduced, and the devices could enter the
accuracy, speed, and real device effects to satisfy the requests
Manuscript received 2 December 2023; revised 21 January of BSIM users for a BSIM4-like [2] experience. The existing
2024 and 28 January 2024; accepted 30 January 2024. This work was BSIM-SOI model used to cover the DD operation using the
supported by the Berkeley Device Modeling Center (BDMC), EECS, UC
Berkeley. The review of this article was arranged by Editor G. D. Smit. concept of source-to-body potential barrier lowering, i.e., when
(Corresponding author: Chetan Kumar Dabhi.) the device is in the FD regime, it lowers the source-to-body
Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, built-in potential, allowing the source-to-body junction to sink
Sayeef Salahuddin, and Chenming Hu are with the Department of
Electrical Engineering and Computer Sciences (EECS), University of a large amount of current without changing body potential,
California, Berkeley, CA 94720 USA (e-mail: [email protected]). and hence, no floating body effect is observed. If a device is
Debashish Nandi and Yogesh S. Chauhan are with IIT Kanpur, Kanpur in the PD regime, the source-to-body potential is not lowered
208016, India.
Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, and the body potential becomes dependent on the source-body
Balaji Swaminathan, and Srikanth Srihari are with GlobalFoundries, current, resting in the floating body effect [7], [12]. The BSIM
Bangalore 560045, India. models are widely accepted for their accuracy and speed [9].
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2024.3363110. However, the symmetry around Vds = 0 V is a major source
Digital Object Identifier 10.1109/TED.2024.3363110 of concern for RF and analog IC designers [13]. The origin

0018-9383 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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2 IEEE TRANSACTIONS ON ELECTRON DEVICES

of this issue lies in the threshold-voltage-based formulations, [Fig. 1(a)] with gradual channel approximation (as mentioned
bias-dependent real device effects, and other factors [2], [14]. below) similar to [18], [25], and [26], with expressing full
Surface-potential-based and charge-based models have become explicit solution, and updated front and back gate surface
more popular since the last decade because of source–drain potential coupling relationship to ensure continuity in surface
symmetry, simple formulation, and model robustness [9], [10], potential derivatives, which is essential for RF applications.
[11], [15], [16]. These are very important features of a good Vx denotes the bias in absolute scale, whereas vx = (Vx /Vt )
compact model suitable for RF and analog IC design. Several denotes the normalized bias. Vt is the thermal voltage
models of dynamically depleted SOI (DD-SOI) have been
d 2 ψ(x) q 
developed in [6], [17], [18], and [19]. Models in [6], [18], = N A + n(x) − p(x) (2a)
and [19] open the door for a compact model suitable solution. dx 2 ϵs
Bolouki et al. [17] uses an abrupt transition between PD/FD n(x) = n 0 e(ψ(x)−vch ) (2b)
−ψ(x)
regions and may lead to a discontinuity in the first derivative. p(x) = p0 e (2c)
Wu et al. [18] have proposed a DD-SOI model where a
where q is the electron charge, vch is the channel potential,
front-and-back gate coupled surface potential relationship was
ψ(x) is the potential in silicon body, and body doping N A =
used that creates discontinuity issues in the derivatives of
p0 − n 0 , using the following two boundary conditions at
surface potential around flat-band voltage, as demonstrated
Si − SiO2 interfaces
further (Fig. 2). Wu et al. [18] and Livingston et al. [19] do
ϵs E sf = Cox vg − ψ f ; −ϵs E sb = Cbox (ve − ψb )


not explicitly mention the accuracy of the solution presented (3)
with numerical simulation, and also, the transconductance
using these models exhibits nonphysical behavior in the where vg = vgb − vgfb , ve = veb − vefb , Cox = (ϵox /Tox ),
saturation region of operation. Considering these facts and Cbox = (ϵbox /Tbox ), and vgb and veb are the front gate bias
f
demands from the semiconductor industry, the BSIM group and substrate bias, respectively. ψ f (E s ) and ψb (E sb ) are
started to develop a surface potential/charge-based symmetric the front and back normalized surface potential (normalized
BSIM-SOI model with real device effects similar to the other surface electric field), respectively. The described model is
BSIM models, such as output conductance, velocity saturation, body (Vb ) referenced. vgfb and vefb are the front and back
short-channel effects, quantum mechanical effects (QMEs), gate flat-band voltages, respectively. Using (2a) and (3), the
nonuniform doping effects, gate leakage current, flicker and final coupled Poisson’s equation can be obtained as shown
thermal noise, stress effect, and intrinsic input resistance [2], in (1), at the bottom of the page, where RT = (Tox /Tbox ),
[7], [20], [21], [22], [23], [24]. The DD model for SOI γ0 = ((2 · q · ϵs · N A )1/2 /Cox (Vt )1/2 ), and φ B = ln((N A /n i ))
MOSFETs with moderately doped Si body is formulated by is the neutral Si body potential. where N A is silicon body
solving the coupled Poisson’s equation across the thickness doping, and ni is the intrinsic carrier concentration of Si.
of the Si body with appropriate boundary conditions at Si– All the biases (mentioned as vx ), potentials, and the electric
SiO2 interfaces, and a robust initial guess of surface potential fields are normalized by Vt . The factor of (ψ f 2 /(ψ f 2 + 2))
is developed for DD operation, suitable for compact model in (1) is for well-conditioned surface potential around flat-band
formulation. To take advantage of our expertise with BSIM- voltage in the PD case only [16]. Two assumptions were
BULK, a pure PD-SOI model is also developed considering made while deriving (1) and to formulate the explicit solution
charge-based formulations of BSIM-BULK as the core model compatible with SPICE implementation without sacrificing
with SOI-specific effects integrated, and the same is presented accuracy much, as given below.
in a separate article (as a Section-II). This helps our PD-SOI 1) Field penetration into the substrate is ignored [18].
users to have a fast and robust PD-SOI model, as it does 2) Back interface is assumed to never reach strong inver-
not require the complete surface-potential-based solution of sion, which is true for most of the circuit applications
coupled Poisson’s equation as in the case of DD. The rest with very thick-BOX, SOI devices [10], [18].
of this article is arranged as follows. Section-II deals with The second approximation helped in ignoring the term shown
the derivation of the initial guess of surface potential for an below in (4), hence not included in (1)
accurate DD-SOI solution and model formulations. Section-III
ψb 2
 
(−2φ B +vch ) ψb
describes the model validation with experimental data, and the e e − ψb − 2 −1 . (4)
conclusion is given in Section-IV. ψb + 2

II. DD M ODEL F ORMULATIONS B. Front and Back Gate Surface Potential

A. Surface Potential Relationship of Coupling Relationship
Dynamic-Depletion Operation To solve (1), a relationship between front and back surface
Our model derivation starts by solving 1-D Poisson’s potential is required. Ortiz-Conde et al. [25] and Mallikarjun
equation across the Si body thickness in the x-direction and Bhat [26] use very complex forms of surface potential

ψf2
  
(−(2φ B +vch ))
· eψ f − ψ f −

2
vg − ψ f − RT · (ve − ψb ) = γ0 · e
2 2 2 −ψ f
−e −ψb
+ ψ f − ψb + exp −1 (1)
ψf2 + 2

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DABHI et al.: SYMMETRIC BSIM-SOI—I 3

where

ψc′ = ψc − RC · ve + (1 + RC) · ψb0 (9a)

 
vg  vg ·γ0 (−(2φ B +vch )) 
ψvfb =


1+ i2 1−exp · T 0
1+ √γ02
h
1 γ0
√
6 2
· 1+ √
2
(9b)
1 
T 0 = tanh(−5(vg − 2)) + tanh(5(vg + 2)) (9c)
2
Fig. 2. Front gate surface potential and its derivatives versus front where (9b) excluding T 0 is obtained by ignoring the back
gate voltage for substrate bias of +5 V (Veb = +5 V). The sharp rise gate contribution in (1), and third-order Taylor expanding
′′
(second peak, around Vgb = −0.5 V) in the second derivative (ψf ) of
surface potential for Veb = +5 V indicates that the device operates the right-hand side. T 0 ensures the effectiveness of ψvfb
dynamically. Around flat-band voltage, Vgb = Vgfb , the second derivative around flat-band voltage. Furthermore, the coupling relation-
′′
of the gate surface potential (ψf ) shows discontinuity if ψvfb term is ship shown in (8) results in the nonphysical behavior of gm
not used. The discontinuity is resolved (yellow curve) in the presence
when PD–FD transition occurs for the saturation region of
of ψvfb . NA = 5 × 1017 cm−3 , Tbox = 200 nm, Tsi = 40 nm, Tox =
2 nm, Vgfb = −1 V, Vefb = 0 V, Vsb = 0 V. Potentials and biases are operation, as seen in Fig. 3(a). Physically, the relationship
on an absolute scale. in (8) does not correctly account for the imperfect FD situation
in saturation condition, which occurs when the source end of a
channel is still operating in PD operation while the drain end is
coupling relationships, and these require numerical solutions, in FD, as illustrated in Fig. 3(b) using linearization coefficient
which make them nonsuitable for compact models. Hence, (αDD ) [18] (αDD ≈ 1 (more precisely, αDD = 1 + (Cb /Cox ))
we have used the following relationship between front and for full FD operation, when Vb = −2 V, Vd = +2 V, and
back potential in the case of FD, and it can be obtained Vs = 0 V). This leads to the nonphysical gm hump in Fig. 3(a).
by solving Poisson’s equation across Si thickness as below In addition, Fig. 3(a) shows that the proposed coupling rela-
[18], [27] tionship in (10) is better and captures the imperfect FD
ψb = ψ f − ψc − E sb · Tsi (5a) condition for large Vd value while eliminating the unphysical
transconductance
q N A Tsi2
ψc = . (5b) (
− ψc′ −ψ f )
!
2ϵs · Vt ln e
′
+1
e−(ψc −ψvfb ) +1
Using (3) in (5a), the front and back gate coupling relationship ψb0 ψb0 + (1+RC)
for FD case is given by ψb =  ψ
f
 + ! . (10)
ψc′
−1
1+e 1+ 1
ψf
1 RC
 

ψb = ψ f − ψc + (ve )

−1
(6) e ψc′
1 + RC 1 + RC
where RC = (Cbox /Cb ), Cb = (ϵs /Tsi ), and the second Equation (10) provides a correction to the back surface
term accounts for the back gate effect. For the PD case, the potential ψb coupling relationship stated in equation (8). This
front and back surface potentials are not coupled, and back correction guarantees smooth transitions from the PD-to-FD
surface potential ψb assumes the value ψb0 which is solved regime (i.e., takes care of imperfect FD situation
in saturation
independently using the equation given below condition). Mathematically, for ψ f − ψc′ < −3 , the device
operates in the PD regime and ψb = ψb0 , while for (ψ f −ψc′ >
RT 2 (ve − ψb0 )2 = γ0 2 e−ψb0 + ψb0 − 1 .


(7) 1), the source end is PD and the drain

end is in the FD regime
[Fig. 3(b)], and exp (ψ f /ψc′ ) − 1 contributes to (10), which
The continuous back surface potential which has the capability
corrects the rate at which the back surface potential increases
of a smooth transition from PD-to-FD operation based on
and eliminates the nonphysical gm hump. For ψ f − ψc′ ≫ 1 ,


device geometry and bias is formulated using the relationship
the device moves to the FD regime with very large ψ f ,
given in (8). A similar relationship has been used in [18];
so the impact of exp (ψ f /ψc′ ) − 1 term in the denominator


however, it produces discontinuity in derivatives of front
vanishes, and we recover FD relationship given in (6).
gate surface potential (near flat-band voltage) when positive
substrate bias is applied for which the device transits through
DD operation, as shown in Fig. 2. The presence of ψvfb [given C. Initial Guess Formulations for Compact Model
in (9b)], helps remove the discontinuities.
We have used the following function to ensure smooth At this point, we have all the required quantities to solve (1).
derivatives around flat-band voltage which is very much essen- However, (7) is implicit in nature and requires good initial
tial for analog and RF design guess for an explicit solution which is derived as follows.
1) PDSOI Back Surface Potential-Independent Initial Guess
−(ψc′ −ψ f )
 
ln e−(ψc′ −ψvfb +1 and Solution: For the PD case, the back gate is decoupled from
e )+1
ψb = ψb0 + (8) the front gate, and we assumed that the back interface never
RC + 1 reaches strong inversion (keeping in mind that the BOX is

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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

dependent on vgb , and hence approximate initial guess is

ψsFDs = 2 φ B + vch . The continuous initial guess considering
depletion to strong inversion is given by
 
1
q

2
ψsFD0 = · ψ fFDd + ψ fFDs − ψ fFDd − ψ fFDs + 40.0 .


2
(14)
Second Refinement Step: Using (1), and considering only
minority carrier concentration
Fig. 3. (a) Transconductance versus gate bias plot, gm is nonphysical

2
for Vd = 2 V when coupling relationship indicated by (8) is used. The vg − ψ f − RT 2 (ve − ψb )2
nonphysical gm behavior is avoided by the revised coupling relationship
= γ0 2 ψs − ψb + exp(−(2φ B +vch )) eψ f .



given in (10). In the validation portion [refer to Fig. 10(b)], the gm data (15)
are validated using the improved coupling relationship given by (10).
(b) Linearization coefficient [18] demonstrates that the nonphysical Substituting ψ f = ψsFD0 + ψsFD1 in (15), after algebraic
gm hump is eliminated when improved coupling relationship is used.
Physically, it also handles the situation when the channel has imperfect
simplification, ψsFD1 can be deduced as
FD, meaning the drain end is in FD, but the source end is in PD. Tbox =
" #
cFD · ψsFD1 dFD · ψs2FD1
300 nm, Tsi = 70 nm, Tox = 6 nm, Vgfb = −1 V, Vefb = 0 V, Vs = 0 V. ψsFD1 = τFD + ln 1 − + (16)
Potentials and biases are on an absolute scale. aFD aFD
where
thick for targeted DDSOI technology). Back surface potential
2
2
in the case of PD is governed by aFD = vg − ψsFD0 − RT 2 · ve − ψsFD0 + ψ fcrit
− γ0 2 ψ f − ψb


RT 2 (ve − ψb0 )2 = γ0 2 e−ψb0 + ψb0 − 1 .


(11)
= 2 · vg − ψsFD0 − 2 · RT 2 · ve + ψ fcrit − ψsFD0



cFD
The above equation is similar to the gate overlap region surface
= 1 − RT 2 · aFD


potential solution in [28], with the exception of the extra dFD (17)
multiplication of RT 2 on the left-hand side of (11), and thus, and τFD is given by
the solution algorithm used in [28] is adopted to obtain an  
aFD
initial guess for the back gate-independent surface potential. τFD = (2φ B + vch ) − ψsFD0 + ln . (18)
It is crucial that ψb0 has the correct solution even at higher γ0 2
decimal digits to prevent discontinuities around the flat-band Furthermore, using (16), and making third-order Taylor expan-
voltage in the solution of (1) at smaller step sizes (i.e., 0.1-mV sion of logarithmic term, it results in a quadratic equation in
step size) of bias sweep. (Because (10) uses ψb which is a terms of ψsFD1 , and linearizing the quadratic expression results
function of ψb0 and is substituted in (1) to solve the front in further approximated ψsFD1 as below
gate surface potential.) To assure the accuracy of ψb0 at aFD · VFD
higher decimal digits (ten digits after the decimal point), one ψsFD1 =  3  (19)
·cFD cFD
µFD + VFDµFD 2


Newton–Raphson iteration is applied to the initial guess of the 3
− 1 − RT · a FD
PDSOI back surface potential-independent solution obtained VFD 2 c2
µFD = + FD − aFD · 1 − RT 2


using the algorithm in [28].
τFD 2
2) FDSOI Case Front Gate Surface Potential Solution—Initial VFD = cFD + aFD . (20)
Guess: To solve ψ f using (1), we require FD operation initial
guess. ψ f during PD operation is evaluated using well-known The first-order approximation of ψ f is ψ f i = ψsFD0 + ψsFD1 .
bulk MOSFET model solution [29]. FD operation initial guess Third Refinement Step: Starting with (15), and substituting,
is obtained as below. ψ f = ψ f i +ψsFD2 , and Taylor expanding the exponential terms,
First Refinement Step: Using (1), and ignoring the minority the final refined step to obtain the surface potential ψsFD2 is
carrier concentration for front and back sides, the approximate given by
first refinement initial front gate surface potential solution at 2 · yFD
ψsFD2 = (21)
the point where SOI
body becomes fully depleted is given by,
q

2
xFD + xFD − 4 · yFD · z FD
i.e., ψ f = ψ fcrit
q where
ψ fFDd = vg − γ0 2 e−ψ fcrit + ψ fcrit − 1 + RT 2 (ve − ψb )2


xFD = 2 · vg − ψ fi − 2 · RT 2 ve − ψ fi + ψ fcrit



(12)
+ γ0 2 · eψ fi −(2·φ B +vch )
where
2
= 2 · vg − ψ fi − 2 · RT 2 ve − ψ fi + ψ fcrit


yFD
q · N A · Tsi 2
ψ fcrit = −RC · ve + ψb . − γ0 2 · eψ fi −(2·φ B +vch ) + ψ fcrit


(13)
2 · ϵs · Vt
The ψ fcrit for initial guess is obtained using (6), with the γ0 2 ψ f −(2·φ B +vch )
z FD = 1 − RT 2 − ·e i . (22)
assumption that 1 + RC ≈ 1. In strong inversion, ψs is weakly 2

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DABHI et al.: SYMMETRIC BSIM-SOI—I 5

 
vg  vg · γ0 (−(2φ B +vch )) 
ψf =


1 + i2 1 − exp
1 + √γ02
h 
1
√
6 2
· 1 + √γ02
else
f · f ′′
 
f
ψ f = ψ finit − ′ · 1+ (25)
f 2· f′ · f′
where ξ = 1 + (γ0 /(2)1/2 ), f is coupled Poisson’s equation
in (1), and ψb used in (1) is as expressed in (10). The f ′ and f ′′
Fig. 4. (a) Front gate surface potential and its derivatives versus front
gate voltage for substrate bias of +5 V (Veb = +5 V). The sharp are the first and second derivatives of ψ f , respectively. ψ f for
rise (second peak, around Vgb = −0.5 V) in the second derivative the condition | vg | < 10−7 ·ξ is obtained by ignoring the back
′′
(ψf ) of surface potential for Veb = +5 V indicates that the device gate contribution in (1) and then performing the third-order
operates dynamically. Around flat-band voltage, Vgb = Vgfb , and the Taylor expansion on the deduced equation’s right-hand side.
′′
second derivative from gate surface potential (ψf ) shows discontinuity
−7 The solution for | vg | < 10−7 · ξ condition helps prevent the
if the condition |Vg |1 mm < 10 · ξ term is not used. The discontinuity
is resolved (orange curve) in the presence of |Vg |1 mm < 10−7 · ξ. numerical discontinuities in the derivatives of surface potential
(b) Front gate surface potential versus front gate voltage for different around flat-band voltage as shown in Fig. 4(a). Fig. 4(a)
substrate bias values, the steep increase in surface potential for Veb = 0 depicts that ψ f solution has discontinuity in the second-order
and 5 V indicates that the device has DD operation, and around
Vgb = 0 it transits from PD-to-FD region. NA = 5 × 1017 cm−3 , Tbox = derivative ( f ′′ ) if the solution for condition | vg | < 10−7 · ξ is
200 nm, Tsi = 40 nm, Tox = 2 nm, Vgfb = −1 V, Vefb = 0 V, Vsb = 0 V. not used. The derivative continuity is very much essential to
Potentials and biases are on an absolute scale. obtain correct higher order harmonic balance (HB) simulations
for RF designs. With three iterations to final coupled Poisson’s
equation solution, the accuracy of nano-volts order is achieved
3) Combined PD–FD Initial Guess: If | vg |< vgFD , then
compared with the numerical solution as shown in Fig. 4(b).
PD initial guess ψ f = ψ finit (BULK-MOSFET solution [29]) The inset plot in Fig. 4(b) shows that the error between the
will be applicable; otherwise, FD initial guess ψ f = ψ finit numerical simulation and proposed model peaks up when
as described in Section II-C2 will be applicable. Here, vg = PD–FD transition is encountered for the given bias and doping
vgb − vgfb and vgFD is the critical gate potential, which decides conditions.
at what gate bias device transits from the PD to FD regime.
In inversion condition under the depletion approximation and D. Drain Current and Terminal Charge Calculations
using potential balance equation [30], the critical gate potential
at which device enters from PD to FD is given by The drain current expression, without velocity saturation,
q is derived as follows:
vgFD = ψc∗ + γ0 e−ψc + ψc∗ − 1
∗
(23) Ids0 = Idrift + Idiff (26)
dψ f dqi
where ψc∗ represents the critical surface potential at which the Ids0 = −Weff · qi · µ0 · Cox + W · µ0 · Cox · Vt (27)
device transitions from PD to FD and is obtained as follows. dy dy
When the device enters the FD regime, the back potential ψb , y is the position along the channel length, qi is the front chan-
which is coupled to ψ f , is calculated using (6). But for PD nel inversion charge density [18], L eff and Weff are the effective
operation, the independent back potential (ψb0 ) is as described channel length and effective channel width of device [14],
in [Section II-C1]. The unified back surface potential for initial respectively, and µ0 is the low-field mobility. After integration
guess is obtained using the relationship given in (8). When (8) Z ψfd !
Weff
begins to satisfy the condition (ψ f −ψc′ ≫ 1), it reduces to FD Ids0 = − · Cox · µ0 qi · dψ f + Vt · (qis − qid )
L eff ψfs
operation given by (6), and the value of the surface potential
at that transition point is given as PD–FD transition surface (28)
potential, ψc∗ . So, using the constraint (ψ f − ψc′ ≫ 1), in (6),
where qis and qid are the values of qi at the source and drain
ψc∗ to achieve an initial guess of vgFD is given by (23), with
ends of the channel, respectively. Using the symmetric charge
the assumption that 1/(1+RC) = 1, which is true for large
linearization method by the PSP model [18], and defining
BOX thickness devices
midpoint potential ψm = ((ψ f s + ψ f d )/2) (ψ f s and ψ f d are
RC the source end and drain end surface potential, respectively),
ψc∗ = ψc − · ve . (24)
1 + RC using the inversion charge at the potential middle point is given
The above-combined PD–FD initial guess for front gate sur- by [18]
face potential (ψ finit ) provides smooth derivatives for coupled qi = qim − αDD · u (29)
surface potential expression.
where qim |ψ f =ψm is the inversion charge at the surface potential
4) Halley’s Algorithm for Error Correction: The following
middle point, u = ψ f − ψm , and the linearization coefficient
procedure further improves the accuracy of the coupled initial
is given by
guess:
qis − qid
αDD = . (30)
if | vg | < 10−7 · ξ : ψfd − ψfs
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6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 5. (a) Gummel symmetry test for Vgb = 1.2 V. Ix versus Vx where Vx = Vsb - Vdb /2, and Vsb and Vdb are swept in the opposite direction. (b) HB
simulation results for the DDSOI model with default parameters, it shows correct slopes up to fifth harmonic. (c) AC symmetry test results: first and
second derivatives of δcg around Vx = 0 V, source and drain are swept in the opposite direction. (d) AC symmetry test results for: first and second
derivatives of δcsd around Vx = 0 V, source and drain are swept in the opposite direction. (e) AC symmetry test results: δcb and its derivatives.
(f) Slope ratio test for model smoothness and robustness. Vb = 0 V.

Substituting (29) and (30) in (28), and performing integration,

the drain current expression is given by
Weff
· Cox · µ0 (qim + Vt · αDD ) · ψ f d − ψ f s . (31)


Ids0 = −
L eff
The effect of velocity saturation is derived in a similar
manner as given in [31]; following symmetric charge lineariza-
tion [31], it is possible to arrive at the following velocity
saturation factor:
Dmob · D1L  p 
Dvsat = · 1 + (1 + 2 · Z sat ) (32) Fig. 6. (a) Cgg versus Vgb for different substrate biases, the PD-to-
2 FD transition is clearly visible around Vgb = 0 V. (b) Cgd versus Vgb for
where Dmob is the mobility degradation factor [14], and D1L different substrate biases, the curve related to Veb = 5 V shows the PD-
to-FD transition around Vgb = 0 V, and also has increased capacitance
and Z sat are the channel length modulation and velocity satu- for weak to strong inversion, because body charges are fixed for FD
ration effect factors, respectively [31]. Drain current including operation; Vsb = 0 V, Vds = 0 V. Symbols: Measurement data, line:
velocity saturation is given by model.

Weff ψfd − ψfs

in the developed compact model. AC symmetry plots shown
Ids = − · Cox · µ0 (qim + Vt · αDD ) · · Moc in Fig. 5(c) and (d) show higher order derivative continuity
L eff Dvsat
for δcg and δcsd , respectively [32]. Fig. 5(e) also shows conti-
(33) nuity for δcb . Slope ratio test in Fig. 5(f) shows smooth and
where Moc = MDIBL · MDITS · MSCBE is the out- monotonic trends as bias varies from weak to strong inversion
put conductance factor [14]. Terminal charges (source/drain [31], [32].
charge, gate charge, and bulk charge) derivation is the same
as given in [31]. The short-channel effects are similar to F. Model Validation and Discussions
BSIM-BULK, and the parameter list and names are the same This section aims to verify the model hardware correlation
as in [15]. (MHC), meaning to verify the accuracy of the developed
model with industry hardware data for nanoscale SOI-FETs.
E. Model Robustness and Quality Tests The model is compared with large set of device measurement
Apart from good physical nature, good convergence, and data for a wide range of geometry and bias conditions, and the
computational efficiency, the compact model is expected to dc (IV) and dynamic (CV) operation of the model are verified.
or designed to pass the symmetric tests [32], i.e., Gummel At the end, the model is also verified with RF data for high-
symmetry and ac symmetry tests. These have been tested frequency applications. Model evaluation has been carried
by EDA companies and BSIM Group while evaluating the out by preparing one global model card covering: 1) all the
model during development. These are very essential features geometries of the device technology; 2) valid range of biases,
for any compact model because the MOS device is intrinsi- from linear to saturation and subthreshold to strong inversion;
cally symmetric, which means source and drain terminals are 3) temperature range of the device technology; and 4) correct
indistinguishable and of critical importance for applications dc and ac behavior of the device. The next step is to use the
such as a bidirectional switch. Our industry partners have prepared model card to fit IV and CV data of RF device under
verified the model’s robustness and convergence by simu- test (DUT), with fine-tuning of parameters. This is required
lating large ring oscillators and test circuits. All the tests because RF DUT has additional parasitic capacitances and
described in this section fall under the model quality tests. The resistances surrounding the device’s intrinsic channel, and their
DDSOI model has been tested for dc symmetry, usually called contributions are significant at high frequencies. The parameter
Gummel symmetry, and the results are shown in Fig. 5(a); extraction is done to validate the model, considering a well-
it shows the continuity of higher order derivatives around optimized procedure, as given below.
Vx = 0 V. HB simulation in Fig. 5(b) depicts the correct 1) Parameters related to specific physical effects are
harmonic slopes up to fifth-order harmonics, which further extracted by observing its features on measured data for
confirms the continuity and smoothness of expressions used long-wide channel devices of technology.

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DABHI et al.: SYMMETRIC BSIM-SOI—I 7

Fig. 7. (a) Transfer characteristics for different body bias (Vb ) values, for Vb = 0 V device is in PD state and it becomes Vb = −0.5, −1 V, the
fully grown depletion pushes devices in the FD regime. Long-channel device data used for fitting. (b) Output characteristics for different values
of substrate bias (Veb ), model captures PD (Veb = −5 and −10 V) to FD (Veb = 5 V) transition smoothly. Vsb = 0 V. (c) Transfer characteristic
considering linear and saturation region fitting for short-channel device, including GIDL. Vsb = 0 V, and Ve = 0 V. (d) Transconductance versus
Vgb model captures gm behavior very well for short-channel device. Vsb = 0 V, Ve = 0 V. (e) Output characteristics for different body bias values.
Model and measured data show that the body bias sensitivity is negligible, meaning the device operates in the FD regime for a short-channel length,
Ve = 0 V. The fitting of model with data depicts that the model captures DD based on applied body bias values. Symbols: Measurement data, line:
model.

Fig. 8. (a) Output conductance versus Vd , corresponding to Fig. 7(d), Vs = 0 V, and Ve = 0 V. (b) Transfer characteristic considering different
temperatures of the device technology, data are for short-channel device. Vsb = 0 V, and Ve = 0 V. (c) Transconductance (gm ) versus Vgb for
different temperatures. Vsb = 0 V, and Ve = 0 V. (d) Drain current versus Vdb for T = −40 ◦ C. Vsb = 0 V, and Ve = 0 V. (e) Drain current versus
Vdb for T = 25 ◦ C. Vsb = 0 V, and Ve = 0 V. The measurement reported in (d) and (e) is for the long channel. The model captures broad range of
temperature dependence very well. Symbols: measurement data, line: model.

2) Parameters related to the short-channel effect (with The transfer characteristic in Fig. 7(a) depicts the model
different channel lengths starting from long to short and correctness to accurately capture the PD-to-FD transition
constant wide width) are extracted. observed in measured data of long-channel device for different
3) Effects of narrow width are extracted considering con- body biases, i.e., for Vb = 0 V, device is completely in PD
stant long-channel device with a wide to a narrow range mode, and for Vb = −0.5, −1 V, the device exhibits FD opera-
of the width of the technology. tion (the increased subthreshold slope (SS), compared with Vb
4) Finally, the parameters related to the narrow width-short- = 0 V case), and excellent fitting of model with measured data
channel device are extracted. is obtained. The output characteristics of long-channel device
Up to this stage, all the extraction is carried out at a nominal in Fig. 7(b) show dynamic device operation by exercising the
temperature, and as a last step, the parameters related to a substrate bias (Veb ). For Veb = −5, −10 V device is in PD
temperature range of the technology are extracted. operation across Vdb value. It operates in the FD regime for
1) CV Validation: The developed model is validated with the Veb = 5 V, the model accurately fits the data for different
measured data from the foundry for the state-of-the-art SOI Veb . Fig. 7(c) and (d) shows transfer and transconductance
technology. As shown in Fig. 6(a), for high negative substrate characteristics, respectively, for short-channel device consid-
bias (Veb = −20 V), the device remains in PD across the gate ering linear and saturation operation; the developed model
bias (Vgb ), from accumulation to strong inversion. However, captures data very well including the GIDL current. For
when Veb = +5 V, the device switches from the PD to the short-channel device, Vb sensitivity is very much negligible
FD regime (around Vgb = 0 V), and the total capacitance as shown in Figs. 7(e) and 8(a). This is because the device
drops even more sharply (around Vgb = 0 V) because the enters in FD regime for short-channel lengths due to the
BOX capacitance (Cbox ), Cox , and the Si body capacitance drain–channel coupling effect. To explore the static operation
(Cb = (ϵsi /Tsi )) appear in series. In addition, as Vgb increases of the model at its full potential, it has been validated across
further (during weak to strong inversion operation), the FD device technology temperature range, from −40 ◦ C to 125 ◦ C.
condition enhances the capacitive coupling. This is because Fig. 8(b) and (c) validates the model with experimental data
the applied gate voltage is now fully used to invert the channel for short-channel devices at different temperatures. Figs. 8(d)
rather than to grow depletion further, which results in a steep and 9(b), Figs. 8(e) and 9(c), and Figs. 9(a) and 9(d) shows
increase in capacitance (compared with Veb = 0 V case). validation of the model for long-channel device output char-
The same behavior is reflected in transcapacitance (Cdg ) as acteristics (output conductances), the model matches data
shown in Fig. 6(b). The developed model accurately captures for different temperatures. The accuracy of the self-heating
the dynamic behavior of DD operation. model is tested in Fig. 9(e), which clearly shows that with
2) IV Validation: Once the dynamic operation is verified, the the self-heating effect, the model accurately captures the
next step is to have extended validation of static (dc) operation. data. The purpose of Fig. 10(a) is to validate leakage current

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8 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 9. Drain current versus Vdb for (a) T = 125 ◦ C. Vb = 0 V, the measurement is for the long channel. Output conductance versus Vdb for
(b) T = −40 ◦ C. (c) T = 25 ◦ C. (d) T = 125 ◦ C. The measurement reported in (a)–(c) is for the long channel. Model agrees well with the short-channel
device data as well (not shown here for brevity). (e) Id versus Vdb plotted with and without self-heating effect. Model captures self-heating effect
very well; Vsb = 0 V, and Ve = 0 V. Symbols: measurement data, line: model.

Fig. 10. (a) Leakage results’ validation with the measured data for long-channel devices, model captures substrate current (leakage current)
data (GIDL, Impact Ionization) adequately. Model also agrees well with short-channel device data as well (not shown here for brevity). Vsb = 0 V.
(b) Transconductance versus front gate bias for saturation operation, high body bias pushes device into FD operation (Vb = −0.6 and −1 V), and for
Vb = 0 V the device is in PD at low Vgb , but at high Vgb it transits from PD to FD around (Vg = 1.5 V), model captures DD very well for different body
biases, Ve = 0 V. RF data validation for the dynamically depleted devices is performed in (c)–(e). The RF-effect-related parameters are tweaked to
obtain better Y-parameter fitting once the device’s dc performance has been fit correctly; Vsb = 0 V. Symbols: Measurement data, line: model.

Fig. 11. (a) Vtsat and (b) Vtlin versus channel length, the constant current method is used to calculate threshold voltage, PD-to-FD transition is
clearly visible for different body bias values. Negligible Vb sensitivity is observed for short-channel devices, indicating that the devices entered the
FD regime. Vs = 0 V. (c) Vtlin versus channel length plot, the constant current method is used to calculate threshold voltage. The device operates in
the PD regime for negative substrate bias (Veb ), and the device threshold voltage is insensitive to Veb values. For positive Veb values, the threshold
voltage decreases more rapidly because the device enters the FD regime, which indicates the coupling effect of substrate bias (i.e., coupling of the
back surface potential to the front surface potential) for the FD regime; Vs = 0 V.

models (impact ionization and GIDL [7]); the developed of the applied Vb (as no Vb sensitivity observed). In addition to
model captures leakage data well. Fig. 10(b) shows gm fitting the body bias, the substrate bias (Veb ) is an additional knob for
for saturation operation. High body bias pushes device into dynamically tuning the device operation. Fig. 11(c) shows that
FD operation (Vb = −0.6 and −1 V). For Vb = 0 V, the by adjusting the substrate bias from −6 to 6 V in 2-V steps,
device is in PD at low Vgb , but at high Vgb it transits from the device can be moved from the PD regime (Veb = −6, −4,
PD to FD (around Vgb = 1.5 V). The model captures DD −2, 0 V) to the FD regime (Veb = 2, 4, 6 V). Fig. 11(c) shows
very well for different body biases. To describe the ability that the device’s threshold voltage decreases as it enters the
of DDSOI model for length scaling, the threshold voltage FD regime for positive substrate bias, indicating the presence
versus channel length plot, for saturation and linear operation, of substrate coupling.
is shown in Fig. 11(a) and (b) respectively. The threshold 3) RF Validation: The RF performance of the model is eval-
voltage is calculated using the constant current method [33] uated by validating model results with the RF de-embedded
(300 nA ×(W/L) for nMOS and 70 nA ×(W/L) for pMOS). data of the device. The Y -parameters of the model show an
In Fig. 11(a) and (b), the long-channel devices are in PD excellent match with the measured data for the frequency range
state for low body bias and enter the FD state for high up to 10 GHz as shown in Fig. 10(c)–(e); the device remains in
Vb value. Short-channel devices exhibit dynamic operation, linear region for RF switch application [34], and the measure-
i.e., for linear region, a PD-to-FD transition occurs if Vb is ment has been done for long channel and Vb = 0 V, implying
increased from 0 to −1 V (no sensitivity observed for Vb = the device is operating in the PD regime. The RF parameter
−0.5, −1 V, meaning device entered in the FD regime), and extraction method is the same as reported in [35]. Overall, the
for saturation region, it remains in the FD regime irrespective DDSOI model is adequately fitting with the RF measured data.

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DABHI et al.: SYMMETRIC BSIM-SOI—I 9

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