Parallel Computing Platforms

Lecture (2)
Chapter 2. Parallel Programming
Platforms
 Topic Overview

• Implicit Parallelism: Trends in Microprocessor Architectures

• Limitations of Memory System Performance
• Dichotomy of Parallel Computing Platforms
• Communication Model of Parallel Platforms
• Physical Organization of Parallel Platforms
• Communication Costs in Parallel Machines
• Messaging Cost Models and Routing Mechanisms
• Mapping Techniques
• Case Studies
 Scope of Parallelism

• Conventional architectures coarsely comprise of a processor, memory system, and the

datapath.
• Each of these components present significant performance bottlenecks.
• Parallelism addresses each of these components in significant ways.
• Different applications utilize different aspects of parallelism - e.g., data intensive applications
utilize high aggregate throughput, server applications utilize high aggregate network
bandwidth, and scientific applications typically utilize high processing and memory system
performance.
• It is important to understand each of these performance bottlenecks.
 Implicit Parallelism: Trends in
Microprocessor Architectures
• Microprocessor clock speeds have posted impressive gains over the
past two decades (two to three orders of magnitude).

• different types of processors are microprocessor, microcontroller,

embedded processor, digital signal processor and the processors
can be varied according to the devices.

• Different of types of CPU are classified as single-core, dual-core,

Quad-core, Hexa core, Octa-core, and Deca core processor

• Higher levels of device integration have made available a large

number of transistors.

• The question of how best to utilize these resources is an important

one.

• Current processors use these resources in multiple functional units

and execute multiple instructions in the same cycle.
 Pipelining and Superscalar Execution

• Pipelining overlaps various stages of instruction execution to achieve

performance.
• At a high level of abstraction, an instruction can be executed while the next
one is being decoded and the next one is being fetched.
• This is akin to an assembly line for manufacture of cars.
 Pipelining and Superscalar Execution

• Pipelining, however, has several limitations.

• The speed of a pipeline is eventually
• For this reason, conventional processors rely on very deep pipelines (20
stage pipelines in state-of-the-art Pentium processors).
• However, in typical program traces, every 5-6th instruction is a conditional
jump!
• The penalty of a misbehavior grows with the depth of the pipeline, since a
larger number of instructions will have to be flushed.
 Pipelining and Superscalar Execution

• One simple way of alleviating these bottlenecks is to use multiple pipelines.

• Then, it becomes one of pumps for these instructions.
Superscalar Execution: An Example
 Superscalar Execution

• Scheduling of instructions is determined by a number of factors:

– True Data Dependency: The result of one operation is an input to the next.
– Resource Dependency: Two operations require the same resource.
– Branch Dependency: Scheduling instructions across conditional branch statements
cannot be done deterministically a-priori.
– The scheduler, a piece of hardware looks at a large number of instructions in an
instruction queue and selects appropriate number of instructions to execute concurrently
based on these factors.
– The complexity of this hardware is an important constraint on superscalar processors.
 Superscalar Execution:
Issue Mechanisms
• In the simpler model, instructions can be issued only in the order in which
they are encountered. That is, if the second instruction cannot be issued
because it has a data dependency with the first, only one instruction is issued
in the cycle. This is called in-order issue.
• In a more aggressive model, instructions can be issued out of order. In this
case, if the second instruction has data dependencies with the first, but the
third instruction does not, the first and third instructions can be co-scheduled.
This is also called dynamic issue.
• Performance of in-order issue is generally limited.
 Superscalar Execution:
Efficiency Considerations
• Not all functional units can be kept busy at all times.
• If during a cycle, no functional units are utilized, this is referred to as vertical
waste.
• If during a cycle, only some of the functional units are utilized, this is referred
to as horizontal waste.
• Due to limited parallelism in typical instruction traces, or the inability of the
scheduler to extract parallelism, the performance of superscalar processors
is eventually limited.
 Very Long Instruction Word (VLIW) Processors

• The hardware cost and complexity of the superscalar scheduler is a major

consideration in processor design.
• To address this issues, VLIW processors rely on compile time analysis to
identify and bundle together instructions that can be executed concurrently.
• These instructions are packed and dispatched together, and thus the name
very long instruction word.
• This concept was used with some commercial success in the Multiflow Trace
machine (circa 1984).
• Variants of this concept are employed in the Intel IA64 processors.
• Typical VLIW processors are limited to 4-way to 8-way parallelism.
 Limitations of
Memory System Performance
• Memory system, and not processor speed, is often the bottleneck for many
applications.
• Memory system performance is largely measured by two parameters, latency
and bandwidth.
• Latency is the time from the issue of a memory request to the time the data is
available at the processor.
• Bandwidth is the rate at which data can be pumped to the processor by the
memory system.
Memory System Performance: Bandwidth and Latency

• It is very important to understand the difference between latency and

bandwidth.
• Consider the example of a fire-hose. If the water comes out of the hose two
seconds after the hydrant is turned on, the latency of the system is two
seconds.
• Once the water starts flowing, if the hydrant delivers water at the rate of 5
gallons/second, the bandwidth of the system is 5 gallons/second.
• If you want immediate response from the hydrant, it is important to reduce
latency.
• If you want to fight big fires, you want high bandwidth.
 Memory Latency: An Example

• Consider a processor operating at 1 GHz (1 ns clock) connected to a DRAM

with a latency of 100 ns (no caches). Assume that the processor has two
multiply-add units and is capable of executing four instructions in each cycle
of 1 ns. The following observations follow:
– The peak processor rating is 4 GFLOPS(floating point operations per second ,is a
measure of computer performance, useful in fields of scientific computations .)

– Since the memory latency is equal to 100 cycles and every time a memory request is
made, the processor must wait 100 cycles before it can process the data.
 Memory Latency: An Example

• On the above architecture, consider the problem of computing a dot-product

of two vectors.
– A dot-product computation performs one multiply-add on a single pair of vector elements,
i.e., each floating point operation requires one data fetch.
– It follows that the peak speed of this computation is limited to one floating point operation
every 100 ns, a very small fraction of the peak processor rating!
 Improving Effective Memory
Latency Using Caches
• Caches are small and fast memory elements between the processor and
DRAM.
• This memory acts as a low-latency high-bandwidth storage.
• If a piece of data is repeatedly used, the effective latency of this memory
system can be reduced by the cache.
• The fraction of data references satisfied by the cache is called the cache hit
ratio of the computation on the system.
• Cache hit ratio achieved by a code on a memory system often determines its
performance.
 Impact of Caches: Example

Consider a processor operating at 1 GHz (1 ns clock) connected to a DRAM

with a latency of 100 ns (no caches). Assume that the processor has two
multiply-add units and is capable of executing four instructions in each cycle
of 1 ns. The following observations follow

Consider the architecture from the previous example. In this case, we

introduce a cache of size 32 KB which takes approximately 200 µs with a
latency of 1 ns or one cycle. We use this setup to multiply two matrices A and
B of dimensions 32 × 32. We have carefully chosen these numbers so that
the cache is large enough to store matrices A and B, as well as the result
matrix C.
Impact of Caches: Example (continued)

• The following observations can be made about the

problem:
– The following observations can be made about the problem:
– Fetching the two matrices into the cache corresponds to fetching
32KBs. which takes approximately 200 µs
– Multiplying two n × n matrices takes 32n32 operations. For our
problem, this corresponds to 64K operations, which can be
performed in 16K cycles (or 16 µs) at four instructions per cycle.
– The total time for the computation is therefore approximately the
sum of time for load/store operations and the time for the
computation itself, i.e., 200 + 16 µs.
– This corresponds to a peak computation rate of 64K/216 or
296.29 FLOPS.