Streamlined SiC

Development With a Total

System Solution
Marching toward a
new paradigm

by Kevin Speer,
Nitesh Satheesh,
Avinash Kashyap, and
Serge Bontemps

T
oday, multiple silicon carbide (SiC) device Introduction
suppliers update their growing product cata- Great capabilities bring great responsibilities. The power
logs every few months. As options increase, electronics community has heard for decades about the
the next challenge facing the widespread promise of SiC to revolutionize the industry; the time has
adoption of SiC is the design-in process. Using come for industry to accept the responsibilities that come
these fast-switching components requires a multifaceted, with realizing this potential. What is holding back the adop-
holistic solution involving the semiconductor die, pack- tion of this disruptive semiconductor technology?
age, gate driver, and the interactions of all three technol- The adoption of SiC hinges not just on price, but also on
ogies. This article shows one such solution. Following a suppliers’ emphasis on providing design solutions rather
discussion of the subject SiC MOSFET’s performance than design challenges. After all, engineers have been suc-
and ruggedness, an optimized power module package ceeding with IGBT technologies for decades, and few are
and innovative gate driver solution are described in keen to fix something that is not broken. Hopeful suppliers
detail. It is then shown how these three key pieces may of SiC must face three realities: First, the robustness of SiC
be seamlessly integrated into a total system solution, MOSFETs must be demonstrated, as there is no surer way
simplifying the design process of SiC while maintaining a to halt a debate about whether to use SiC or silicon. Second,
march toward a new paradigm in power electronics. much of SiC’s value proposition hinges on the optimization
of system-wide parasitic inductance; rightfully, then, the
burden to minimize parasitic inductance of SiC power pack-
Digital Object Identifier 10.1109/MPEL.2020.3011276
aging rests on the shoulders of component-makers. Third,
Date of current version: 15 September 2020 faster switching devices necessitate more sophisticated

Authorized 28 IEEEuse
licensed POWER ELECTRONICS
limited to: University of WesternzAustralia.
MAGAZINE September 2020
Downloaded 2329-9207/20©2020IEEE
on August 15,2023 at 14:58:00 UTC from IEEE Xplore. Restrictions apply.
 Pre-and Post-Stress HTGB; VGS = 20 V, Pre-and Post-Stress HTGB; VGS = –8 V,
TA = 175 °C, 1,000 h, 1,200 V, 40 mΩ SiC MOSFET TA = 175 °C, 1,000 h, 1,200 V, 40 mΩ SiC MOSFET
3.2 3.2
3.17
3.12
3.1 3.1
3.05 3.04
3 3
2.92 2.89

Vth (V)
Vth (V)

2.87
2.9 2.86 Post-Stress 2.9 Pre-Stress Post-Stress
Pre-Stress
2.8 2.8

2.7 2.71 2.7 2.71 2.72

2.67
2.6 2.6
(a) (b)

FIG 1 Box plots showing the stability of threshold voltage before and after 1,000 hours of (left) positive HTGB and (right) negative
HTGB. (Source: Microchip Technology; used with permission.)

testing done on 1200 V SiC MOSFETs in the commonly used

QBC for 1,200 V SiC MOSFETs qualification vehicle, a standard TO-247-3L package.
3
2 Pre-Stress Stable Threshold Voltage
1 + –10 V for 48 h To verify the long-term stability of Vth for the SiC MOSFETs
In(–In(1–F))

0 –20 V for 59 h used in the total system solution, positive and negative high-
–1 temperature gate bias (p- and n-HTGB) stresses were
–2 applied, respectively, to independent sets of sixty-four (64)
–3 1200 V SiC MOSFETs (Figure 1). The applied stress con-
–4 d i tions were TA = 175 cC, VDS = 0 V, and VGS = + 20 V
–5 (p-HTGB) or −8 V (n-HTGB) for a duration of 1000 hours.
10 100 1,000
Among these populations, the average pre- to post-stress
QBD (C/cm2)
deviation observed in Vth was +59.6 millivolts following
FIG 2 QBD results for 1200 V SiC MOSFETs revealing no extrin- p-HTGB and −22.8 millivolts following n-HTGB, indicating a
sic failure modes before or after HTGB stress. (Source: Micro- well-anchored, predictable threshold voltage around which
chip Technology; used with permission.) tighter, longer-term design choices may be made.

gate driver techniques with enhanced flexibility and intel- Reliable Gate Oxide
ligence. This article shows precisely one such example of a Figure 2 shows charge-to-breakdown (QBD) data taken
total SiC system solution—complete with MOSFET die, a from three populations of Microchip 1200 V SiC MOSFETs,
low-inductance package, and innovative digital gate driver. having been subjected to either 1) no n-HTGB, 2) 48 h
The Augmented Switching Accelerated Development o f n-HTGB at VGS = - 10 V, or 3) 59 h of n-HTGB at
Kit (ASDAK) is a SiC half-bridge solution fully opti- VGS = - 20 V. All observed failures are intrinsic. Separately,
mized to streamline development and expedite a confident data taken from a broader population of 192 devices
field deployment. revealed a FIT rate and MTTF (T j = 90 cC) for p-HTGB of 20
and 5,618 years, respectively; for n-HTGB, FIT rate and
SiC MOSFET Characteristics MTTF were 93 and 1,233 years. These encouraging oxide
Historically, SiC MOSFETs have faced similar challenges as integrity results with Microchip’s SiC MOSFETs are consis-
the silicon MOSFET: Extrinsic defects (impurities, charge tent with time-dependent dielectric breakdown (TDDB)
states, and other material defects) near the oxide-semicon- reports from other vendors. High-integrity gate oxides such
ductor interface precipitate a variety of device instabilities as these are crucial for use in applications where long ser-
and degradation mechanisms [1]. To make an effective sys- vice lifetimes are critical.
tems solution, a production-grade SiC MOSFET must dem-
onstrate robustness against these flaws. Specifically, it must Robust Body Diode
have a stable threshold voltage [2], a reliable gate oxide [3], Another reliability challenge that has haunted SiC is a phe-
a robust intrinsic body diode [4], and ruggedness under ava- nomenon wherein the forward voltage drop across a SiC p-n
lanche and short-circuit conditions [5]. This section reports junction is found to increase over time of operation [6]. This

Authorized licensed use limited to: University of Western Australia. Downloaded on August 15,2023September UTC z
2020
at 14:58:00 fromIEEE POWER
IEEE ELECTRONICS
Xplore. MAGAZINE
Restrictions apply. 29
 is a threatening long-term issue for SiC MOSFETs, as it other vendors. The gate oxide from Microchip exhibits the
increases both the on-state resistance and the voltage drop best long-term reliability in this study.
across the diode during current commutation. Thankfully,
today’s materials have matured, and the density of preexist- Advanced Packaging Technology
ing dislocations in production-grade materials has fallen; With confidence established in the performance and reliabil-
nonetheless, there remain differences among SiC vendors. ity of the SiC MOSFET, next up in the creation of a total sys-
Figure 3 shows recent research from Ohio State University tem solution (TSS) is an advanced power package. Though
[7], in which third-quadrant data was measured on ten (10) the final integration of a power discrete or module will for-
of Microchip’s 1200 V SiC MOSFETs and ten parts each from ever be a task for the end user, it is nonetheless the compo-
two other vendors. With pre- and post-stress data overlap- nent supplier’s responsibility to innovate and offer low-
ping, Microchip’s SiC MOSFETs show no body diode degra- inductance power packaging so that designers may take full
dation following 100 hours of stress at full-rated current. advantage of SiC’s fast switching speeds.
External module connections may appear simple, but
Avalanche Ruggedness internal layout issues are both sophisticated and crucial for
A relevant test for verifying avalanche ruggedness is system performance. Due to their comparatively small die
unclamped inductive switching (UIS). In UIS testing, the size, many SiC MOSFET die must be paralleled to achieve
MOSFET is in its OFF state when it is suddenly asked to low on-state resistances for the module. All die must switch
swallow a power surge. Since the MOS channel is not with nearly identical timing and uniform current sharing,
enhanced, all current must avalanche in the die’s periph- so die interconnection schemes must balance priorities
ery—a much smaller area than, say, a short-circuit test in of symmetry and low inductance. In response to these
which the current is uniformly distributed across the requirements, the company has released the SP6LI power
device’s entire active area (in short circuit withstand tests, module package format, which inserts only 2.9 nH of stray
the MOSFET is in the ON state). inductance into the power loop. For comparison, the para-
Even more meaningful as a field ruggedness measure is sitic inductance of standard module packages is around
submitting the device to repetitive UIS pulses, or (R-UIS) [8] 20 nH. Optimal timing and current sharing are achieved
[9] [10] [11] [12]. Figures 4 and 5 compare the device’s para- in the SP6LI package with independent series gate resis-
metric stability and oxide integrity before and after 100,000 tor slots for each of the twelve available die spaces in the
repetitive pulses at two-thirds rated current (per MIL- high and low side switch positions. These independent gate
STD-750). The data shown in Figure 4 indicate excellent resistance paths also minimize the inductance inserted into
avalanche ruggedness. Figure 4a reveals some oxide dam- the gate-source loop, which is known to increase switching
age (due to the high field in the JFET region during UIS), losses and make the system vulnerable to shoot-through.
but the gate leakage current remains below a few nano- To minimize power loop inductance, internal dc link con-
amperes. Minor deviations were observed in drain leak- nections are made using bus bars arranged in strip lines.
age and on-state resistance but are viewed as insignificant Substrate connections are symmetrically distributed and
since VBR, Vth, and the body diode’s V F were unaffected by as close as possible to the semiconductor die.
R-UIS. Figure 5 compares pre- and post-R-UIS stress TDDB The company offers a family of half-bridge products
measurements on SiC MOSFETs from Microchip and three in the SP6LI at 700 V, 1200 V, and 1700 V classes with

0 0 0
VG = – 5 V VG = – 5 V VG = – 5 V
–1 –1 –1

–2 –2 –2
ID (A)

ID (A)

ID (A)

–3 –3 –3

–4 –4 –4

–5 –5 –5
–5 –4 –3 –2 –1 0 –5 –4 –3 –2 –1 0 –5 –4 –3 –2 –1
VDS (V) VDS (V) VDS (V)
(a) (b) (c)

Pre Stress Post Stress 10 A After 10 h Post Stress 10 A After 20 h Post Stress 10 A After 100 h

FIG 3 Third-quadrant SiC MOSFET data from SiC MOSFETs, illustrating differences in body diode robustness among three leading SiC
MOSFET suppliers. No degradation is observed in Microchip devices, part a. (Source: Microchip Technology; used with permission.)

Authorized 30 IEEEuse
licensed POWER ELECTRONICS
limited to: University of WesternzAustralia.
MAGAZINE September 2020
Downloaded on August 15,2023 at 14:58:00 UTC from IEEE Xplore. Restrictions apply.
 nominal currents from 210 to 754 A [13]. Standard SP6LI SiC Gate Driver Technology
products offer AlN ceramic substrates and Cu baseplate, With high-performance SiC MOSFETs in a low-inductance
with options to upgrade the ceramic to Si 3 N 4 and the package, the final remaining piece to assemble a TSS is the
baseplate to AlSiC for improved thermal conductivity and control. New gate driver technology is required for SiC
power-cycling. Figure 7 shows output characteristics and MOSFETs, as high-speed switching makes the entire system
switching energy for a 1200 V, 2.5 mX half-bridge module more susceptible to EMI failure and voltage spikes. In addi-
in the SP6LI package. Switching such high currents at high tion, the gate driver must quickly detect and respond to
speed is clearly possible, but only practical with low pack- short circuit conditions, as SiC MOSFETs have shorter with-
age inductance. stand times than most silicon IGBTs. These challenging
requirements have motivated the design of Microchip’s
AgileSwitch family of software-configurable, digital gate
drivers. By reducing transient voltage spikes and switching
Gate-Source Leakage
oscillations, the patented technique of Augmented Switch-
VGS = 20 V
2.5 ing enables the use of SiC MOSFETs at the speeds for which
they were intended [14].
2

1.5 Augmented Switching

(nA)

1 Rather than taking VGS directly from the on-state level to

the off-state level, one approach is to use augmented switch-
0.5
ing (AS) to pause at a user-specified, intermediate VGS for a
0 user-specified duration to discharge the Miller capacitance
1 2 3 4 5
Part Number
(a)
Off-State Drain-Source Leakage TDDB for 1,200 V SiC MOSFETs
VGS = –5 V, VDS = 1,200 V IGS = 50 mA
180 80,000
160 70,000 Pre-R-UIS R-UIS
140
120 60,000
100 50,000
(nA)

80
(s)

40,000
60
40 30,000
20 20,000
0
1 2 3 4 5 10,000
Part Number 0
(b) Microship Comp. A Comp. B Comp. C

ON-State Resistance
FIG 5 TDDB measurements of 1200 V SiC MOSFETs. Competitor
VGS = 20 V, IDS = 40 A
47 A’s results suggest UIS-related oxide damage, while Microchip’s
expected lifetime is more than twice as long before and after
45 R-UIS. (Source: Microchip Technology; used with permission.)

43
(mΩ)

41

39

37

35
1 2 3 4 5
Part Number
(c)

Pre-R-UIS Post-R-UIS

FIG 4 Microchip’s SiC MOSFET dc characteristics measured

before and after 100,000 R-UIS pulses of 100 mJ each, reveal- FIG 6 The SP6LI module package, featuring a low parasitic
ing the stability of each parameter. (Source: Microchip Tech- inductance of 2.9 nH. (Source: Microchip Technology; used
nology; used with permission.) with permission.)

Authorized licensed use limited to: University of Western Australia. Downloaded on August 15,2023September UTC z
2020
at 14:58:00 fromIEEE POWER
IEEE ELECTRONICS
Xplore. MAGAZINE
Restrictions apply. 31
 before proceeding to the off-stage VGS . Slight modifications Reconfigure With a Click
in levels and duration result in dramatic tradeoffs between Changes to turn-off profiles are set through an Intelligent
voltage overshoot and efficiency, allowing rapid experimen- Configuration Tool (ICT) which is supplied with the driver
tation to achieve optimal design choices across all develop- (Figure 9). On a separate ICT page are protection settings
ment stages. While this two-level turn-off method is not new for short circuit conditions, another area where the Agile-
in principle [15], the AgileSwitch family of gate driver prod- Switch family of gate drivers offers enhanced intelligence.
ucts has fully digitized the technique, opening an unprece- During a short circuit event, the gate driver triggers a turn-
dented range of design flexibility for system optimization. off profile different from that of normal turn-off; this can
To illustrate the impact of AS, Figure 8 shows turn-off include additional software-configurable voltage step-down
waveforms using two AS profiles and a 1200 V SiC MOSFET levels and durations. Incorporating AS methods into short
module from Microchip in a D3 package. It is evident how circuit protection reinforces the use of a low R g, as well as
a lower intermediate voltage level reduces switching losses guiding the MOSFET through a softer, more controlled
(where efficiency is a priority), while using an intermediate transition to the off state with reduced likelihood of ava-
voltage above the Miller plateau softens oscillations on all lanche. Still more configurable features include real-time
three waveforms and dampens the overshoot on VDS . At the diagnostic measures, such as dc link voltage and tempera-
click of a mouse, a designer can fine-tune these settings at ture monitoring. With the ICT, the designer can experiment
all stages along the development path. with a variety of gate driver settings using a computer
mouse instead of a soldering iron, saving enormous
amounts of time and resources.
Output Characteristics
1,200 Total System Solution: ASDAK
Tj = 25 °C
Microchip’s ASDAK is a total system solution (TSS),
1,000 complete with SiC MOSFET, power package, and com-
IDS, Drain Source Current (A)

panion gate driver. It is common for today’s SiC custom-

800 ers to source these components from three different ven-
Tj = 175 °C dors, placing the burden of making sure they play nicely
600 together on the end user. Technological solutions must
then be chased down with multiple parties whose timing
400 and priorities rarely sync; making matters worse, the
VGS = 18 V parties may not be willing to discuss key technology
200 VGS = 20 V details. This leaves many loose ends in the power system
due to oversight, mistakes, or unnecessary compro-
0 mises. A unified, one-stop solution is much preferred by
0 0.5 1 1.5 2 2.5 3
VDS, Drain Source Voltage (V) the design community.
(a) From an electrical standpoint, the package’s intercon-
nections to both the MOSFET die (internal) and gate driver
Switching Energy Versus Drain Current
12
(external) must be tailored for the lowest inductance and
Tj = 150 °C greatest symmetry. With in-house design and co-develop-
10 ment of all three components, the ASDAK solution achieves
performance like that shown in Figure 10 right out of the
8 box. With AS, the use of an intermediate VGS = 0 V for
Losses (mJ)

Eon 50 nanoseconds slashes the turn-off losses by 42%, from

6 14.97 mJ to only 8.73 mJ, while overshoot voltage fell 40%
(to 920 V) using VGS = 2.2 V for 100 ns. As discussed here
4 [14], the reconfigurable gate driver parameters allow the
Eoff user to fine-tune a compromise between switching losses
2 and overshoot voltage, effects whose optimization become
even more crucial upon insertion into the end system (e.g.,
0 bus bars).
0 200 400 600
Figure 11 shows the Microchip 2ASC-12A1HP gate driver
IDS, Drain Current (A)
core tightly coupled with the SP6LI module through an
(b)
adapter board. (Adapter boards are also available for other
common package types for use with Microchip’s Agile-
FIG 7 (Top) Output characteristics and (bottom) switching ener-
gies of 1200 V, 2.5 mX SiC MOSFET half-bridge module in SP6LI Switch family of gate drivers.) The use of a finely-tuned,
power package. (Source: Microchip Technology; used with per- ready-to-mount solution such as this enables designers
mission.) to fully optimize their thermal and mechanical systems,

Authorized 32 IEEEuse
licensed POWER ELECTRONICS
limited to: University of WesternzAustralia.
MAGAZINE September 2020
Downloaded on August 15,2023 at 14:58:00 UTC from IEEE Xplore. Restrictions apply.
 whether a more elegant connection to capacitor banks exert more effort creating design solutions rather than
and current sensors or the wiring simplicity offered by dc design challenges. Present-day SiC solutions—while tech-
link and temperature monitoring through the gate driver. nologically impressive—tend to emerge from partnerships
A complete three-phase deployment concept of the ASDAK among corporate, academic, and government circles, which
system solution is illustrated in Figure 12. prove cumbersome to implement due to a variety of techni-
cal and commercial hurdles. In this article, a total system
Summary solution is shown that combines a top performing SiC MOS-
If power electronics designers are to transition away from FET with an ultra-low inductance power package and a
silicon IGBTs to SiC MOSFETs, component suppliers must sophisticated SiC gate driver. With the ASDAK, the c­ ompany

VSoff = 1 V, t = 250 ns VSoff = 4 V, t = 650 ns

VDS = 600 V, IDS = 400 A, Rg,ext = 1.1 Ω VDS = 600 V, IDS = 400 A, Rg,ext = 1.1 Ω

20 V 744 V 20 V 704 V
750 20 750 20
600 600
VDS (V), IDS (A)

VDS (V), IDS (A)

10 10
450 400 A 450 400 A Eoff = 11.89 mJ
VGS (V)

VGS (V)
Eoff = 8.67 mJ
300 0 300 0
150 150
–10 –10
0 0
–150 –20 –150 –20
1.20E–05 1.25E–05 1.30E–05 1.35E–05 1.40E–05 1.17E–05 1.22E–05 1.27E–05 1.32E–05 1.37E–05
(a) (b)

VDS IDS VGS

FIG 8 Turn-off waveforms showing the impacts of augmented switching on switching performance of a SiC MOSFET module. (Left)
VDC = 600 V, IDS = 400 A, Rg = 1.1 X, Vovershoot = 144 V; (Right) VDC = 600 V, IDS = 400 A, Rg = 1.1 X, Vovershoot = 104 V. (Source: Microchip
Technology; used with permission.)

FIG 9 Gate driver parameters may be easily reconfigured with the Intelligent Configuration Tool (ICT). (Source: Microchip Technol-
ogy; used with permission.)

Authorized licensed use limited to: University of Western Australia. Downloaded on August 15,2023September UTC z
2020
at 14:58:00 fromIEEE POWER
IEEE ELECTRONICS
Xplore. MAGAZINE
Restrictions apply. 33
 VSoff = 0 V, t = 50 ns
VDS = 800 V, IDS = 650 A, Rg,ext = 1.1 Ω
20 V 968 V
1,000 20
VDS (V), IDS (A)

800 V
800 650 A
10

VGS (V)
600
Eoff = 8.73 mJ
400 0
200
–10
0
–200 –20
6

6
–0

–0

–0

+0

–0

–0
E

0E

0E
0E
.5

.0

.0

5.

1.
0.
–1

–1

–5

VDS IDS VGS

FIG 10 Turn-off waveform of the 1200 V, 2.5 mX ASDAK total FIG 12 A complete three-phase implementation of the ASDAK
SiC system solution. (Source: Microchip Technology; used with system solution. (Source: Microchip Technology; used with per-
permission.) mission.)

Table 1. SiC MOSFET modules offered

in the SP6LI package.
RDSon ID
Microchip PN VBR (Tj = 25 °C ) (TC = 80 °C)
MSCSM70AM025CT6LIAG 700 2.5 mX 538 A
MSCSM120AM042CT6LIAG 1200 4.2 mX 394 A
MSCSM120AM03CTLIAG 1200 2.5 mX 641 A
MSCSM120AM02CT6LIAG 1200 2.1 mX 754 A

diode device design and processing, and advanced power

packaging. He has held strategic technical marketing roles
with SemiSouth Laboratories, Infineon, and Littelfuse. Just
FIG 11 A package-specific adapter board is used to tightly cou-
ple the gate driver core to the SP6LI package. (Source: Micro- prior to joining Microchip, he founded Speer Semiconduc-
chip Technology; used with permission.) tor, a business aimed at empowering stakeholders across
the value chain through product development and road-
has unified these three components into the development mapping, customer outreach, strategy and investment dili-
kit customers have been requesting for years to streamline gence, and market analysis. He holds a Bachelor of Science
their SiC journey from initial evaluation to a confident field in Electrical Engineering (BSEE) from the University of
deployment. Arkansas, a Master of Science in engineering from Case
Western Reserve University (CWRU), and a Ph.D. in electri-
Acknowledgments cal engineering from CWRU as a NASA Research Fellow.
The authors gratefully acknowledge the valuable contribu- Nitesh Satheesh is a technical staff engineer in Micro-
tions of our colleagues Albert Charpentier, Charles Christ- chip Technology’s Discrete and Power Management Busi-
man, Jason Chiang, Orlando Esparza, Adam Fender, Mat- ness Unit, responsible for customer design-in and other
thew Fisher, Mark Gabler, Reenu Garg, Aaron Heine, Mike activities. Prior to his current role, Satheesh was general
Innab, Bruce Odekirk, Sally Scott, Colin Shephard, Laird manager for AgileSwitch India Pvt. Ltd., leading engineering
Thornhill, Rob Weber, Derek Wilson, and Glenn Wright. and product development, development of a state-of-the-art
high-power test lab for SiC devices, and overall facility man-
About the Authors agement. Earlier Satheesh worked for Fuji Electric Corpora-
Kevin Speer ([email protected]) joined Micro- tion of America as semiconductor applications engineer for
chip Technology in 2020 as senior manager of SiC Solutions, industrial and automotive modules. He holds a Bachelor of
Discrete and Power Management Business Unit, where he Engineering, Electronics and Communications from Anna
develops SiC product strategies and total systems solutions University in Chennai, India, and later was an EMECW
needed by Microchip’s power semiconductor clientele. Scholar – European Union, with a concentration in electron-
Since 1999, Speer has published a range of SiC research ics, systems and networks, at the Ecole Nationale Supéri-
spanning materials science to applications, including crystal eure d’Ingénieurs des Systèmes Avancés et Réseaux,
growth, defect-related device degradation, SiC MOSFET and France. He holds a Master of Science degree in electrical

Authorized 34 IEEEuse
licensed POWER ELECTRONICS
limited to: University of WesternzAustralia.
MAGAZINE September 2020
Downloaded on August 15,2023 at 14:58:00 UTC from IEEE Xplore. Restrictions apply.
 engineering, solid state electronics, from Rutgers University. [5] L. Yang, A. Fayyaz and A. Castellazzi, “Characterization of high-voltage
He holds patents in gate drive control systems for SiC and SiC MOSFETs under UIS avalanche stress,” in Proc. 7th IET Int. Conf.
IGBT power devices, with additional patents pending relat- Power Electronics, Machines, and Drives, Manchester, U.K., 2014.
ed to gate drive technology. He has published several arti- [6] J. Bergman, H. Lendenmann, P. Nilsson, U. Lindefelt and P. Skytt, “Crystal
cles in industry publications. defects as source of anomalous forward voltage increase of 4H-SiC diodes,”
Avinash Kashyap is the director of SiC Technology & Mater. Sci. Forum, vols. 353–356, pp. 299–302, 2001. doi: 10.4028/www
Development and Head of R&D for power discretes at Micro- .scientific.net/MSF.353-356.299.
chip Technology. Kashyap leads multiple groups ranging from [7] A. Agarwal and M. Kang, private communication., 2020.
device design, process integration and test. He is responsible [8] K. Fischer and K. Shenai, “Dynamics of power MOSFET switching under
for creating product roadmaps and execution of various criti- unclamped inductive loading conditions,” IEEE Trans. Electron. Devices,
cal silicon and wide bandgap programs including SiC FETs vol. 43, no. 6, 1996. doi: 10.1109/16.502137.
and diodes, silicon low voltage FETs, rad-hard FETs and RF [9] S. Liu, C. Gu, J. Wei, Q. Qian, W. Sun, and A. Huang, “Repetitive
power switches. He has been involved in the development of unclamped-inductive-switching-induced electrical parameters degradations
SiC technology since its infancy for more than 17 years, and simulation optimizations for 4H-SiC MOSFETs,” IEEE Trans. Electron.
including device design, SPICE modeling, applications engi- Devices, vol. 63, no. 11, pp. 4331–4338, 2016. doi: 10.1109/TED.2016.2604253.
neering, business development and commercialization. He [10] X. Zhou et al., “A deep insight into the degradation of 1.2-kV 4H-SiC
has authored more than 35 peer-reviewed publications and MOSFETs under repetitive unclamped inductive switching stresses,” IEEE
has over 20 patents granted or pending. Kashyap holds a PhD Trans. Power Electron., vol. 33, no. 6, pp. 5251–5261, 2018. doi: 10.1109/
in electrical engineering from the University of Arkansas, TPEL.2017.2730259.
Fayetteville. He is a senior member of the IEEE. [11] J. Wei, S. Liu, S. Li, J. Fang, T. Li and W. Sun, “Comprehensive investiga-
Serge Bontemps is a senior manager of Research and tions on degradations of dynamic characteristics for SiC power MOSFETs
Development in Microchip’s Discrete and Power Manage- under repetitive avalanche shocks,” IEEE Trans. Power Electron., vol. 34,
ment Business Unit. Prior to his current role for several no. 3, pp. 2748–2757, 2019. doi: 10.1109/TPEL.2018.2843559.
years, Bontemps held the position of Research and Develop- [12] A. Gendron-Hansen, D. Sdrulla, A. Kashyap, B. Odekirk, W. Brower, and
ment Director in the Power Module Products Group at L. Thornhill, “4H-SiC junction barrier Schottky diodes and power MOSFETs
Microsemi, which was acquired in 2018 by Microchip. He with high repetitive UIS ruggedness,” in Proc. IEEE Energy Conversion
developed a range of power modules introduced in the com- Congr. & Expo., 2019.
pany’s standard catalogue, and actively developed rugge- [13] “Silicon carbide semiconductor products,” Microchip, Inc. Accessed:
dized versions for extreme environments. He developed the May 3, 2020. [Online]. Available: http://ww1.microchip.com/downloads/en/
first power module dedicated to electromechanical actua- DeviceDoc/00002868B.pdf
tors on the A380 aircraft, and developed high power mod- [14] N. Satheesh, “Silicon carbide MOSFETs: Handle with care,” in Proc.
ules for race cars, energy recovery systems for Formula One Applied Power Electronics Conference (APEC), San Antonio, TX, 2018.
vehicles, and Formula E power trains. Prior to Microsemi, [15] A. Volke and M. Hornkamp, IGBT Modules: Technologies, Driver and
he was Research and Development Manager at Advanced Application, 1st ed., Munich, DE: Infineon Technologies AG, 2011, pp. 276–278.
Power Technology Europe. He started his career at startup [16] S. Buetow, R. Herzer, G. Koenigsmann, M. Rossberg, and A. Maul, “High
Power Compact as Research and Development Engineer. power, high frequency SiC-MOSFET system with outstanding performance,
Bontemps holds a degree in engineering from the Ecole power density, and reliability,” in Proc. Int. Symp. Power Semiconductor
Nationale Superieure d’Electronique et de radio-electricite Devices and ICs (ISPSD), Sapporo, JP, 2017.
de Bordeaux (ENSERB), and a degree in electronics and [17] P. Losee et al., “SiC MOSFET design considerations for reliable high
automation from Diplôme Universitaire de Technologie, voltage operation,” in Proc. IEEE International Reliability Physics Symp.
France. He has authored more than 40 articles and papers (IRPS), Monterey, CA, 2017.
presented at international conferences. [18] K. Matocha and V. Tilak, “Understanding the inversion-layer properties
of the 4H-SiC/SiO2 interface,” Mater. Sci. Forum, vols. 679–680, pp. 318–325,
References 2011. doi: 10.4028/www.scientific.net/MSF.679-680.318.
[1] H. Tsuya, “Silicon materials science and technology,” in Proc. 8th Int. [19] Z. Chbili et al., “Modeling early breakdown failures of gate oxide in SiC
Symp. Silicon Materials Science and Technology, 1998. power MOSFETs,” IEEE Trans. Electron Devices, vol. 63, pp. 3605–3613,
[2] A. Lelis et al., “Time dependence of bias-stress-induced SiC MOSFET 2016. doi: 10.1109/TED.2016.2586483.
threshold-voltage instability measurements,” IEEE Trans. Electron. Devices, [20] K. Cheung, “SiC power MOSFET gate oxide breakdown reliability: Current
vol. 55, no. 8, p. 1835, 2008. doi: 10.1109/TED.2008.926672. status,” in Proc. IEEE Int. Reliability Physics Symp., Burlingame, CA, 2018.
[3] L. Yu, G. Dunne, K. Matocha, K. Cheung, J. Suehle, and K. Sheng, “Reli- [21] M. Miao, S. Limpijumnong and W. Lambrecht, “Stacking fault band struc-
ability issues of SiC MOSFETs: A technology for high-temperature environ- ture in 4H-SiC and its impact on electronic devices,” Appl. Phys. Lett., vol.
ments,” IEEE Trans. Device Mater. Reliab., vol. 10, no. 4, p. 418, 2010. doi: 79, no. 26, pp. 4360–4362, 2001. doi: 10.1063/1.1427749.
10.1109/TDMR.2010.2077295. [22] I. Ji et al., “Highly rugged 1200 V 80 mOhm 4-H SiC power MOSFET,” in
[4] A. Agarwal, H. Fatima, S. Haney, and S.-H. Ryu, “A new degradation Proc. Int. Symp. Power Semiconductor Devices and ICs, 2017.
mechanism in high-voltage SiC power MOSFETs,” IEEE Electron Device [23] N. Satheesh, “The state of intelligent SiC MOSFET gate drivers,” EE
Lett., vol. 28, no. 7, p. 587, 2007. doi: 10.1109/LED.2007.897861. Power, Apr. 2, 2018.

Authorized licensed use limited to: University of Western Australia. Downloaded on August 15,2023September UTC z
2020
at 14:58:00 fromIEEE POWER
IEEE ELECTRONICS
Xplore. MAGAZINE
Restrictions apply. 35