TPS54329E

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4.5V to 18V Input, 3-A Synchronous Step-Down Converter with Eco-Mode™

Check for Samples: TPS54329E

1FEATURES DESCRIPTION
23 • D-CAP2™ Mode Enables Fast Transient The TPS54329E is an adaptive on-time D-CAP2™
Response mode synchronous buck converter. The TPS54329E
enables system designers to complete the suite of
• Low Output Ripple and Allows Ceramic Output various end-equipment power bus regulators with a
Capacitor cost effective, low component count, low standby
• Wide VIN Input Voltage Range: 4.5 V to 18 V current solution. The main control loop for the
• Output Voltage Range: 0.76 V to 7.0 V TPS54329E uses the D-CAP2™ mode control that
provides a fast transient response with no external
• Highly Efficient Integrated FETs Optimized compensation components. The adaptive on-time
for Lower Duty Cycle Applications control supports seamless transition between PWM
– 100 mΩ (High Side) and 74 mΩ (Low Side) mode at higher load conditions and Eco-mode™
• High Efficiency, less than 10 μA at shutdown operation at light loads. Eco-mode™ allows the
TPS54329E to maintain high efficiency during lighter
• High Initial Bandgap Reference Accuracy
load conditions. The TPS54329E also has a
• Adjustable Soft Start proprietary circuit that enables the device to adopt to
• Pre-Biased Soft Start both low equivalent series resistance (ESR) output
• 650-kHz Switching Frequency (fSW) capacitors, such as POSCAP or SP-CAP, and ultra-
low ESR ceramic capacitors. The device operates
• Cycle By Cycle Over Current Limit from 4.5-V to 18-V VIN input. The output voltage can
• Auto-Skip Eco-mode™ for High Efficiency at be programmed between 0.76 V and 7 V. The device
Light Load also features an adjustable soft start time. The
TPS54329E is available in the 8-pin DDA package,
APPLICATIONS and designed to operate from –40°C to 85°C.
• Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)

VOUT (50 mV/div)

TPS54329EDDA
IOUT (1 A/div)

100 μs/div
G006

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 D-CAP2, Eco-mode are trademarks of Texas Instruments.
3 Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1)

TRANSPORT
TA PACKAGE (2) (3)
ORDERABLE PART NUMBER PIN
MEDIA
TPS54329EDDA Tube
–40°C to 85°C DDA 8
TPS54329EDDAR Tape and Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN, EN –0.3 20
VBST –0.3 26
VBST (10 ns transient) –0.3 28
Input voltage range VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5
SW –2 20
SW (10 ns transient) –3 22
VREG5 –0.3 6.5
Output voltage range V
GND –0.3 0.3
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Human Body Model (HBM) 2 kV
Electrostatic discharge
Charged Device Model (CDM) 500 V
Operating junction temperature, TJ –40 150
°C
Storage temperature, Tstg –55 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION
TPS54329E
THERMAL METRIC (1) UNITS
DDA (8 PINS)
θJA Junction-to-ambient thermal resistance 42.1
θJCtop Junction-to-case (top) thermal resistance 50.9
θJB Junction-to-board thermal resistance 31.8
°C/W
ψJT Junction-to-top characterization parameter 5
ψJB Junction-to-board characterization parameter 13.5
θJCbot Junction-to-case (bottom) thermal resistance 7.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 4.5 18 V
VBST –0.1 24
VBST (10 ns transient) –0.1 27
VBST(vs SW) –0.1 5.7
SS –0.1 5.7
VI Input voltage range EN –0.1 18 V
VFB –0.1 5.5
SW –1.8 18
SW (10 ns transient) –3 21
GND –0.1 0.1
VO Output voltage range VREG5 –0.1 5.7 V
IO Output Current range IVREG5 0 10 mA
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
IVIN Operating - non-switching supply current 800 1200 μA
VFB = 0.8 V
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 4.3 10 μA
LOGIC THRESHOLD
EN high-level input voltage EN 1.6 V
VEN
EN low-level input voltage EN 0.45 V
REN EN pin resistance to GND VEN = 12 V 220 440 880 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA, Eco-
773 mV
mode™ operation
VFBTH VFB threshold voltage
TA = 25°C, VO = 1.05 V, continuous mode
749 765 781 mV
operation
IVFB VFB input current VFB = 0.8 V, TA = 25°C 0 ±0.1 μA
VREG5 OUTPUT
TA = 25°C, 6.0 V < VIN < 18 V,
VVREG5 VREG5 output voltage 5.5 V
0 < IVREG5 < 5 mA
(1)
IVREG5 Output current VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 60 mA
MOSFET
High side switch resistance 25°C, VBST - SW = 5.5 V (1) 100 mΩ
RDS(on)
Low side switch resistance 25°C (1) 74 mΩ
CURRENT LIMIT
Iocl Current limit L out = 1.5 μH (1) 3.5 4.2 5.7 A

(1) Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
(2)
Shutdown temperature 165
TSDN Thermal shutdown threshold (2)
°C
Hysteresis 35
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 1.05 V 150 ns
tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V (2) 260 ns
SOFT START
SS charge current VSS = 1 V 4.2 6.0 7.8 μA
ISS
SS discharge current VSS = 0.5 V 0.1 0.2 mA
UVLO
Wake up VREG5 voltage 3.75
UVLO UVLO threshold V
Hysteresis VREG5 voltage 0.33

(2) Not production tested.

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DEVICE INFORMATION

DDA PACKAGE
(TOP VIEW)

1 VBST SS 8

TPS54329E
2 VIN DDA EN 7

(HSOP8)

3 SW Power PAD VREG5 6

4 GND VFB 5

PIN FUNCTIONS
PIN
DESCRIPTION
NAME NO.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
VBST 1
pins. An internal diode is connected between VREG5 and VBST.
VIN 2 Input voltage supply pin.
SW 3 Switch node connection between high-side NFET and low-side NFET.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
GND 4
a single point.
VFB 5 Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND. VREG5 is not
VREG5 6
active when EN is low.
EN 7 Enable input control. EN is active high and must be pulled up to enable the device.
SS 8 Soft-start control. An external capacitor should be connected to GND.
Exposed Thermal Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
Back side
Pad GND.

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FUNCTIONAL BLOCK DIAGRAM

EN EN VIN
7
Logic
VIN
2

VREG5
VBST
Control Logic 1
Ref +

SS + PWM
1 shot
VFB SW VO
5 - 3

XCON
ON
VREG5
VREG5 Ceramic
6 Capacitor

SGND
SS SS 4
8 Softstart
+ SW GND
PGND ZC
- PGND

SGND
+ SW
OCP
- PGND

VIN

VREG5 UVLO Protection

TSD Logic
UVLO

REF Ref

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OVERVIEW
The TPS54329E is a 3 A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation
The main control loop of the TPS54329E is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54329E uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54329E runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Auto-Skip Eco-Mode™ Control

The TPS54329E is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1
1 (VIN - VOUT )×VOUT
I OUT ( LL ) = ×
2 × L × fsw VIN (1)

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 μA.
CSS (nF) x VREF ´1.1 CSS (nF) x 0.765 ´1.1
t (ms) = =
SS I (mA) 6
SS (2)
The TPS54329E contains a unique circuit to prevent current from being pulled from the output during startup if
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft
start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.

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Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54329E constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.

UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54329E is shut off. This protection is non-latching.

Thermal Shutdown
TPS54329E monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.

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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
1200 20
SS = 7 V VIN = 12 V
18
1000
16

Shutdown Current (µA)

Supply Current (µA)

14
800
12
600 10
8
400
6
4
200
2
0 0
−50 0 50 100 150 −50 0 50 100 150
Junction Temperature (°C) G001
Junction Temperature (°C) G002

Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE Figure 2. VIN SHUTDOWN CURRENT vs

JUNCTION TEMPERATURE

100 1.100
VIN = 18 V L = CLF7045
90
80
1.075
EN Input Current (µA)

Output Voltage (V)

70
60
50 1.050
40
30
1.025
20 VIN = 5 V
VIN = 12 V
10
VIN = 18 V
0 1.000
0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0
EN Input Voltage (V) G003
Output Current (A) G004

Figure 3. EN CURRENT vs EN VOLTAGE Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT

1.08

1.07 VOUT (50 mV/div)

Output Voltage (V)

1.06
IOUT (1 A/div)
1.05

1.04

1.03 IOUT = 10 mA
IOUT = 1 A
1.02
0 5 10 15 20 100 μs/div
Input Voltage (V) G005
G006

Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE

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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
100
L = CLF7045
EN (10 V/div) 90

80

Efficiency (%)
VREG5 (5 V/div)
70

VOUT (0.5 V/div) 60

VOUT = 1.8 V
50 VOUT = 2.5 V
VOUT = 3.3 V
40
400 μs/div 0.0 0.5 1.0 1.5 2.0 2.5 3.0
G007 Output Current (A) G008

Figure 7. START-UP WAVE FORM Figure 8. EFFICIENCY vs OUTPUT CURRENT

100 900
L = CLF7045 IOUT = 1 A
90 850

Switching Frequency (kHz)

80 800
70 750
Efficiency (%)

60 700
50 650 VOUT = 1.05 V
40 600 VOUT = 1.2 V
VOUT = 1.5 V
30 550 VOUT = 1.8 V
20 VOUT = 1.8 V 500 VOUT = 2.5 V
VOUT = 2.5 V VOUT = 3.3 V
10 450
VOUT = 3.3 V VOUT = 5.0 V
0 400
0.001 0.01 0.1 0 5 10 15 20
Output Current (A) G009
Input Voltage (V) G010

Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE

800 0.780
VIN = 12 V IO = 1 A
700
0.775
Switching Frequency (kHz)

600
VFB Voltage (V)

0.770
500

400 0.765

300 0.760
200
VOUT = 1.05 V 0.755
100 VOUT = 1.8 V
VOUT = 3.3 V
0 0.750
0.01 0.1 1 10 −60 −40 −20 0 20 40 60 80 100 120
Output Current (A) Junction Temperature (°C) G012
G011

Figure 11. SWITCHING FREQUENCY vs OUTPUT Figure 12. VFB VOLTAGE vs JUNCTION TEMPERATURE
CURRENT

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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).

VOUT = 1.05 V VOUT = 1.05 V

VOUT (10 mV/div) VIN (50 mV/div)

SW (5 V/div) SW (5 V/div)

400 ns/div 400 ns/div

G013 G014

Figure 13. OUTPUT VOLTAGE RIPPLE (IO = 3 A) Figure 14. INPUT VOLTAGE RIPPLE (IO = 3 A)

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DESIGN GUIDE

Step-By-Step Design Procedure

To begin the design process, the user must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple

U1
TPS54329EDDA

Figure 15. Shows the schematic diagram for this design example.

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ R1÷ ö
V = 0.765 x çç1 + ÷
OUT çè R2 ÷ø (3)

Output Filter Selection

The output filter used with the TPS54329E is an LC circuit. This LC filter has double pole at:
1
F =
P 2p L x COUT
OUT (4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54329E. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1

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Table 1. Recommended Component Values

Output Voltage (V) R1 (kΩ) R2 (kΩ) C4 (pF) (1) L1 (µH) C8 + C9 + C10 (µF)
1 6.81 22.1 1.5 20 - 68
1.05 8.25 22.1 1.5 20 - 68
1.2 12.7 22.1 1.5 20 - 68
1.5 21.5 22.1 1.5 20 - 68
1.8 30.1 22.1 5 - 22 2.2 20 - 68
2.5 49.9 22.1 5 - 22 2.2 20 - 68
3.3 73.2 22.1 5 - 22 2.2 20 - 68
5 124 22.1 5 - 22 3.3 20 - 68
6.5 165 22.1 5 - 22 3.3 20 - 68

(1) Optional

Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (5)
I
lpp
I =I +
Ipeak O 2 (6)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (7)
For this design example, the calculated peak current is 3.49 A and the calculated RMS current is 3.01 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3 A and an RMS current rating of 4.9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54329E is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 8
to determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(8)
For this design three TDK C3216X5R0J106M 10µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.

Input Capacitor Selection

The TPS54329E requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) is required to provide additional high frequency filtering and insure accurate current limit operation.
This capacitor must be placed as close to the IC pins 2 (VIN) and 4 (GND) as possible. The capacitor voltage
rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.

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VREG5 Capacitor Selection

A 0.47 µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.

THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 16. Thermal Pad Dimensions

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LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the analog ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground
trace.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to
the device.
14. Performance based on four layer printed circuit board.

Copyright © 2011–2012, Texas Instruments Incorporated 15

Product Folder Link(s) :TPS54329E
TPS54329E
SLVSAZ5A – SEPTEMBER 2011 – REVISED MARCH 2012 www.ti.com

VIA to Power Ground Plane

VIA to SW Copper Pour on Bottom
or Internal Layer ANALOG
VIN GROUND
VIN VIN TRACE
BOOST
INPUT HIGH FREQENCY
CAPACITOR
BYPASS BYPASS
CAPACITOR CAPACITOR
VBST SS
TO ENABLE
VIN EN CONTROL

SW VREG5

GND VFB

BIAS SLOW
CAP START
CAP
EXPOSED
POWER THERMAL PAD
AREA
GROUND FEEDBACK
RESISTORS
OUTPUT
INDUCTOR
SW node copper pour
area on internal or
bottom layer POWER
GROUND Connection to
POWER GROUND
on internal or
bottom layer

OUTPUT
VOUT FILTER
CAPACITOR

Figure 17. PCB Layout

16 Copyright © 2011–2012, Texas Instruments Incorporated

Product Folder Link(s) :TPS54329E

 TPS54329E
www.ti.com SLVSAZ5A – SEPTEMBER 2011 – REVISED MARCH 2012

REVISION HISTORY

Changes from Original (September 2011) to Revision A Page

• Removed SWIFT™ from the data sheet title ........................................................................................................................ 1

• Deleted from ELECTRICAL CHARACTERISTICS table, VLN5 and VLD5, deleted VVREG5 MIN and MAX values .................. 3
• Added in ELECTRICAL CHARACTERISTICS table, IVREG5 and RDS(on) footnote references ............................................... 3
• Added in ELECTRICAL CHARACTERISTICS table, tOFF(MIN) footnote reference and deleted MAX value .......................... 4
• Deleted from ELECTRICAL CHARACTERISTICS, UVLO MIN and MAX values ................................................................ 4
• Added TYPICAL CHARACTERISTICS Condition ................................................................................................................ 9

Copyright © 2011–2012, Texas Instruments Incorporated 17

Product Folder Link(s) :TPS54329E
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54329EDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54329E

TPS54329EDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54329E

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54329EDDA DDA HSOIC 8 75 507 8 3940 4.32
TPS54329EDDA DDA HSOIC 8 75 517 7.87 635 4.25

Pack Materials-Page 1
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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