INDERPRASTHA ENGINEERING COLLEGE,GHAZIABAD

Question Bank- Unit 5

Subject Name : COA Code KCS 302

1. What are the different modes of transfer

Ans. Each I/O device communicates with a computer through I/O interface. The communication
between I/O device and processor can be controlled in three ways
a. Programmed I/O- Each I/O device connected to the computer is continually checked for
inputs by the CPU. Once it receives an input signal from a device, it carries out that
request until it no longer receives an input signal. Programmed I/O operations are the
result of computer programs
b. Interrupt based I/o- It allows the CPU to continue to process other work instead and
will be interrupted only when it receives an input signal from an I/O device. For
example, if you strike a key on a keyboard, the interrupt I/O will send a signal to the CPU
that it needs to pause from its current task and carry out the request from the keyboard
stroke.
c. Direct Memory Access (DMA)- The data transfer between a fast storage media such as
magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow
the peripherals directly communicate with each other using the memory buses,
removing the intervention of the CPU. This type of data transfer technique is known as
DMA or direct memory access. During DMA the CPU is idle and it has no control over the
memory buses. The DMA controller takes over the buses to manage the transfer directly
between the I/O devices and the memory unit.
2. Where is IOP used in computer system?
Ans. The computer that has separate set of data , address and control buses , one for accessing
memory and other for I/O uses IOP. IOP is input output processor,It is a processor separate
from the CPU designed to handle only input/output processes for a device or the computer. It is
used to provide an independent pathway for the transfer of information between external
devices and internal memory
3. Write down difference between isolated and memory mapped I/O . Discuss their advantages
Ans.

In isolated I/O –one common bus is used to transfer information between memory or I/O and
the CPU.The distinction between memory transfer and I/O is made through separate read and
write lines. The CPU specifies whether the instruction is for memory word or for an I/O
interface.Seperate memory and input/Output addresses are used here. Separate instruction
sets are used for input output operations.

Fig. Isolated I/O

In memory-mapped I/O, both memory and I/O devices use the same address space. We assign
some of the memory addresses to I/O devices. The CPU treats I/O devices like computer
memory. The CPU either communicates with computer memory or some I/O devices depending
on the address. In the case of memory-mapped I/O, all the buses are the same for both
memory and I/O devices. Therefore, building a CPU that uses memory-mapped I/O is easier and
cheaper. Additionally, such CPUs consume less power due to reduced complexity. One
advantage of memory-mapped I/O is that we don’t need separate instruction sets for accessing
I/O devices. Instructions used for accessing memory can be easily used for accessing I/O devices.
But the availability of address space will be less in this case as compared to isolated I/O

Fig. memory mapped I/O

4. What is the significance of having I/O interface

 Ans. It Provides a method for transferring information between internal storage (such as
memory and CPU registers) and external I/O devices
It Resolves the following differences between the computer and peripheral devices.Peripherals
are Electromechanical/Electromagnetic Devices .CPU or Memory are Electronic Device
,Conversion of signal values are required

Data Transfer Rate

• Peripherals - Usually slower

• CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed

Unit of Information

• Peripherals – Byte, Block, …

• CPU or Memory – Word

Data representations and operating modes may differ

5. What is an I/O interface?

Ans. The I/o bus consists of data lines control lines and address lines. Each peripheral device has
associated with it an interface unit. Each interface decodes the address and control recived
from the I/O bus, interprets them for peripheral and provides signal for the peripheral
controller. It synchronizes the data flow and supervises the transfer between peripheral and
processor. The processor places the devise address on the address lines. Each interface attached
to the I/O bus contains an address decoder that monitors address lines. When the interface
detects its own address it activates the path between the bus lines and the device that it
controls. At the same time processor provides a function code also through control lines. These
codes are called as I/O commands.

6. What is I/O command and how many types of commands I/O are there.
Ans. Whenever there is I/O transfer, processor provides a function code also through control
lines to i/o interface. These codes are called as I/O commands.
 There are are four types of I/O command that an interface may receive from processor and
execute it-
a. Control- this is used to activate the peripheral and inform it what to do
b. Status-it is to test the status condition in the interface and peripheral.for example, the
computer may wish to check the status before it initiates transfer
c. Data output- This causes the interface to respond by transferring the data on the data
bus into the peripheral
d. Data input- This command places the data from the peripheral onto the databus from
where it is accepted by the processor
7. Discuss the design of typical input or output interface
Ans.
Input/output Interface provides a method for transferring information between processor and
external input/output devices i.e., peripherals. Peripherals connected to computer need special
communication links for interfacing them with CPU.
An I/O consists of two data registers called ports, a control register , a status register, bus
buffers and timing and control unit. The interface communicates with the CPU through data bus.
The chip select and register select inputs determines the address assigned to the interface. The
I/O read write are two control lines that specify an input or output. The four registers
communicate directly with the I/O device attached to the interface

8. Discuss different types of data transfer

Ans.There are two modes of data transfer- Synchronous and Asynchronous
If the registers in the I/O interface share a common clock with the CPU register , then the
transfer between the I/O and CPU or any other two units is said to be synchronous data
 transfer. But if the internal timings of each unit is independent of each other i.e. every unit uses
its own clock for internal registers, then it is Asynchorous data transfer.
9. What do you mean by asynchronous data transfer. Explain strobe control and hand shaking
mechanism
Ans. Asynchronous data transfer between two independent units requires that the control
signals be communicated between the communicating units to indicate the time at which the
data is being transmitted. One way of achieving this is through strobe pulse supplied by one of
the units to indicate when the transfer has to occur. In another way, the unit receiving the data
item responds with another control signal to acknowledge the receipt of the data. This type of
agreement between independent units is referred as handshaking.
Strobe Control
The strobe control method of data transfer employs a single control line to time each transfer.
Strobe line informs the destination unit when valid data is available in the bus. It may be
activated by either source or destination unit. Destination unit can also activate the strobe ,
informing the source to provide data, the source unit responds by placing the data on the data
bus.

Handshaking.
The disadvantage of strobe method is that the source unit/ destination unit that initiates the
transfer has no way of knowing whether the other unit has actually received the data or
placed the data on bus. The handshake method solves this problem by introducing a second
control signal that provides a reply to the unit that initiates the transfer. The two handshaking
lines are data valid and data accepted.
Two way handshaking can be employed in two ways
a. Source initiated transfer using handshake
 b. Destination initiated transfer using handshake

10. What is DMA . Describe how DMA is used to transfer data from peripherals
Ans. The transfer of data between the fast device such as magnetic disk and memory is often
limited by the speed of the CPU. Removing the CPU from the memory path and letting the
peripheral device manage the memory buses directly would improve the speed of transfer. This
technique is called as Direct memory access(DMA). During DMA transfer the CPU is idle and has
no control on memory buses. A DMA controller takes over the buses to manage the transfer
directly between I/O device and memory.
 Fig. CPU bus signals for DMA transfer
As shown in the above fig, the bus request signal is used by the DMA controller to request the
CPU to relinquish control of the buses. When this input is active , the CPU terminates the
execution of the current instruction and places the address bus, data bus, and read write lines
into high impedance state(high impedance means open circuit).
The CPU activates bus grant output to inform the external DMA that the buses are in high
impedance state. When the DMA terminates the transfer, it disables the bus request line and
CPU disables bus grant and takes control of buses.

11. What are interrupts? how they are handled?

Ans. Interrupts are generally called signals which are generated by the software or hardware
when a particular event or process requires immediate attention. So, the signal informs the
processor about a high priority and urgent information demand causing an interruption in the
current working process of the processor.
Thus, whenever an interruption occurs the processor finishes the current instruction execution
and starts the execution of the interrupt known as interrupt handling.
An interrupt cycle is followed by the CPU to handle any interrupt , as shown below.

In interrupt cycle, the return address available in the PC is stored in a specific location where it
can be found later when the program returns to the instruction at which it was interrupted. In
the above figure memory location at address 0 is the place for storing return address . Control
then inserts address 1 into PC and clears IEN and R so that no more interruptions can occur until
interrupt request from flag has been serviced.

12. What do you mean by vectored and non vectored interrupt

Ans. The CPU responds to the interrupt signal by storing the return address from the program
counter into memory stack and then control branches to a service routine that processes the
 required I/O transfer. In non vectored interrupt, the branch address of service routine is
assigned to a fixed location in memory. In a vectored interrupt, the source that interrupts
supplies the branch information to the computer.

13. Draw and explain block diagram of DMA controller

Ans.

Ans. The DMA controller needs the usual circuit of an interface to communicate with the CPU
and I/O device. In addition, it needs an address register , a word count register and a set of
address lines.The address register and the address lines are used for direct communication with
the memory. The word count register specifies the number of words that must be
transferred.The data transfer may be done directly between device and memory under the
control of DMA.
The unit communicates with the CPU via data bus and control lines.The registers in the DMA are
selected by CPU through the address bus by enabling DS(DMA select) and RS(register select)
inputs. The read(RD) write(WR) inputs are bidirectional. When the BG(bus grant) input is 0, the
cpu can communicate with DMA registers through data bus to read from or write to the DMA
registers. When BG=1 , the CPU has relinquished the buses and the DMA can communicate
directly with the memory by specifying an address in the address bus and activating RD or WR
control.
The CPU initializes the DMA by sending the given information through the data bus.
 The starting address of the memory block where the data is available (to read) or where data
are to be stored (to write).
 It also sends word count which is the number of words in the memory block to be read or write.
 Control to define the mode of transfer such as read or write.
 A control to begin the DMA transfer.

14. Explain burst transfer and cycle stealing modes of DMA transfer
Ans. When DMA takes control of the bus system , it communicates directly with memory. The
transfer can be made in two ways-
 a. Burst Transfer- In this a block sequence consisting of words is transferred in continuous
burst. This mode of transfer is needed for fast devices such as magnetic disk etc. where
data transmission cannot be stopped or slowed down until an entire block is transfered
b. Cycle stealing- It allows the DMA controller to transfer one data word at a time after
which it must release the control of the buses to CPU

15. Explain the DMA transfer in a computer system

Ans.
 The CPU communicates with the DMA through the address and data buses as with any interface
unit.The DMA has its own address when CPU sends this address through address bus it activates
DS and RS lines. The CPU initializes the DMA through data bus. Once the DMA receives start
control command it starts the transfer between peripheral and memory
When the peripheral device sends a DMA request , the DMA controller activates the BR (bus
request) line, informing CPU to relinquish the buses. The CPU responds with BG (bus grant)line,
informing the DMA that its buses are disabled. The DMA then puts the current value of its
address register into address bus, initiates the RD, WR signal and sends a DMA acknowledge to
the peripheral. When peripheral device receives a DMA acknowledge it puts a word in data bus
or receives a word from the data bus.
The read(RD) write(WR) inputs are bidirectional. When the BG(bus grant) input is 0, the cpu can
communicate with internal DMA registers through data bus to read from or write to the DMA
registers. When BG=1 , the CPU has relinquished the buses and the DMA can communicate
directly with the RAM memory by specifying an address in the address bus and activating RD or
WR control
16. What is IOP processor
Ans.
An Input Output processor may be classified as a processor with direct memory access capability
that communicates with the I/O devices.Unlike DMA controller that must be set up entirely by
the CPU, IOP can fetch and execute its own instructions. In this configuration the computer
system can be divided into CPU and one or more IOPs. The IOP is similar to CPU except that it is
designed to handle I/O processing. Apart from I/O transfers , it can perform arithmetic logic ,
branching and code translation.

17. Draw the block diagram for CPU-IOP communication

Ans. The communication between CPU and IOP can take different forms, the sequence of
operations may be carried out as follows-
 CPU sends an instruction to test the IOP path
 The IOP responds by inserting status word in memory for CPU to check. The status word
may indicate the condition of IOP as overload, device busy or device ready
 When IOP is ready the CPU sends the instruction start I/O transfer. The memory address
received with this instruction tells the IOP where to find its program
 The CPU is now busy with another program, the IOP is busy with I/O program
 IOP terminates the execution of its program , it sends an interrupt request to CPU
 CPU responds by issuing an instruction to read status of IOP
 IOP gives out its status
 From the inspection of status word bits , the CPU determines if the I/O operation was
completed satisfactorily without errors