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Final Exa1

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Badr Bouhsina
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8 views

Final Exa1

Uploaded by

Badr Bouhsina
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Final Exam

Monday 21st 2013

1)

- Assume the input frequency (fin) is 256 Hz. The output frequency (fout) will be

a. 16 Hz

b. 1 kHz

c. 65 kHz

d. none of the above

- If the SHIFT/LOAD line is HIGH, data


a. is loaded from D0, D1, D2 and D3 immediately

b. is loaded from D0, D1, D2 and D3 on the next CLK

c. shifted from left to right on the next CLK

d. shifted from right to left on the next CLK

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2) You wish to detect only the presence of the codes 0110, 1110, 0101, 0010, and 1011.
An active LOW output is required to indicate their presence. Develop the minimum
decoding logic with a single output that will indicate when any one of these codes is
on the inputs. For any other code, the output must be HIGH.

3)

a- Implement the logic function in the truth table by using the 74LS151

A3 A2 A1 A0 Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

a- Derive the SOP expression from the truth table and use Karnaugh map to simplify it.
b- Draw the final logic circuit by using only NANDs.
4) Use the following IC 74121 to design a retriggerable one-shot. Determine
the pulse widthif the external resistor is 6.6 KΩ and the external capacitor is
1000pF.

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5) Use the 555 timer to design an astable and determine the values of the
external resistors to get a signal with a frequency of 40KHz, the external
capacitor is 2nF and the duty cycle is to be approximately 50%.

6) Design a synchronous counter to produce the following binary sequence. Use J-


K flip- flops.
0,2,4,6,1,3,5,7,0,.

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