6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Features
• Infineon Thin-Film-SOI technology Product summary
• Fully operational to +1200 V • VOFFSET ≤ 1200 V
• Integrated Ultra‐fast Bootstrap Diode • VCC = 13 V - 20 V
• Floating channel designed for bootstrap operation • IO+/- (typ.) = 0.35 A/0.65 A
• Output source/sink current capability +0.35 A/‐0.65 A
• ton/off (typ.) = 700 ns/650 ns
• Tolerant to negative transient voltage up to -100 V
• Deadtime (typ.) = 460 ns
(Pulse width is up 700 ns) given by SOI-technology
• Undervoltage lockout for both channels
• 3.3 V, 5 V, and 15 V input logic compatible Package
• Over current protection with ±5% ITRIP threshold
• Fault reporting, automatic Fault clear and
Enable function on the same pin (RFE)
• Matched propagation delay for all channels
• Integrated 460 ns deadtime protection
• Shoot-through (cross-conduction) protection DSO-24 (DSO-28 with 4 pins removed)
Typical applications
• Industrial Drives
• Embedded inverters for Motor Control in Pumps, Fans.
• Commercial and Lite Commercial Air Conditioning

Description
The 6ED2230S12T is a high voltage, high speed IGBT with three independent high side and low side referenced
output channels for three phase applications. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is compatible with standard CMOS or TTL outputs, down to
3.3 V logic. An over‐current protection (OCP) function which terminates all six outputs can also be derived from
this resistor. An open drain FAULT signal is provided to indicate that an over-current or undervoltage shutdown
has occurred. Fault conditions are cleared automatically after a delay programmed externally via an RC network.
The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The
floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which
operates up to 1200 V. Propagation delays are matched to simplify the HVIC’s use in high frequency applications.

DC BUS +

Vcc
VB1,2,3
(Refer to Lead Assignments for Hin1,2,3
correct pin configuration). Lin1,2,3
HO1,2,3
RFE
This diagram shows electrical
ITRIP
connections only. Please refer to VS1,2,3 To load
Application Notes & Design Tips
for proper circuit board layout. LO1,2,3

Vss COM

DC BUS -

Figure 1 Typical connection diagram

Datasheet Please read the Important Notice and Warnings at the end of this document <Revision 1.3>
www.infineon.com/SOI 2020‐03‐10
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Device information

Device information
Base part number Package type Standard pack Orderable part pumber
Form Quantity
1)
6ED2230S12T DSO-24 Tape and Reel 1000 6ED2230S12TXUMA1

1 Also available for die sales as ‘Sawn Wafer on Film’ with part number 6ED2230S12C. Please contact Infineon for
more information.
Datasheet 2
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Table of contents

Table of contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Lead configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Application information and additional details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 IGBT/MOSFET gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 Switching and timing relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
6.2.1 Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2.2 Matched propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.3 Input logic compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Undervoltage lockout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.5 Shoot-Through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.6 Enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7 Fault reporting and programmable fault clear timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.8 Over-Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.9 Truth table: Undervoltage lockout, ITRIP, and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.10 Advanced input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6.11 Short-Pulse / Noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.12 Integrated bootstrap diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.13 Tolerant to negative VS transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.14 PCB layout tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.15 Additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Package information DSO-24 (DSO-28 4 pins removed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Qualification Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9 Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Datasheet 3
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Block diagram

1 Block diagram
VB1
S
Input
VSS/COM Latch
HIN1 Noise
Level
HV Level
& Driver HO1
filter Shifter
Deadtime & Shifter UV Detect
Shoot-Through
Prevention R
Input VS1
LIN1 Noise
filter

VB2
S
Input
VSS/COM Latch
HIN2 Noise HV Level
filter Level
Shifter
& Driver HO2
Deadtime & Shifter UV Detect
Shoot-Through
Prevention R
Input
LIN2 Noise VS2
filter

VB3
S
Input
VSS/COM Latch
HIN3 Noise HV Level
filter
Level
Shifter
& Driver HO3
Deadtime & Shifter UV Detect
Shoot-Through
Prevention R
Input VS3
LIN3 Noise
filter

VSS UV
Detect VCC

ITRIP ITRIP
Noise
filter VSS/COM
Level Delay Driver LO1
Shifter

RFE Noise
filter
VSS/COM
Level Delay Driver LO2
Shifter

VSS/COM
Level Delay Driver LO3
Shifter

COM

Figure 2 Functional block diagram

Datasheet 4
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Lead configuration

2 Lead configuration
Table 1 Lead definitions
Symbol Description
HIN1,2,3 Logic input for high side gate driver output (HO), in phase
LIN1,2,3 Logic input for low side gate driver output (LO), in phase
VB1,2,3 High side floating supply
HO1,2,3 High side gate drive output
VS1,2,3 High side floating supply return
VCC Low side and logic fixed supply
LO Low side gate drive output
COM Low side return
VSS Logic ground
ITRIP Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates RFE
low. When ITRIP becomes inactive, RFE stays active low for an externally set time tFLTCLR, then
automatically becomes inactive (open-drain high impedance).
RFE Integrated fault reporting function like over-current (ITRIP), or low-side undervoltage lockout and
the fault clear timer. This pin has negative logic and an open-drain output. The use of over-current
protection requires the use of external components.

HIN1 1 28 VB1

HIN2 2 27 HO1
HIN3 3 26 VS1
LIN1 4 25
LIN2 5 24
LIN3 6 23 VB2

ITRIP 7 22 HO2

RFE 8 21 VS2

VCC 9 20
VSS 10 19
COM 11 18 VB3

LO1 12 17 HO3

LO2 13 16 VS3

LO3 14 15 NC

Figure 3 Lead Assignments

Datasheet 5
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Absolute maximum ratings

3 Absolute maximum ratings

Table 2 Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Parameter Symbol Values Unit Note or Test
Condition
Min. Max.
Low side supply voltage VCC -0.3 25 V —
Logic input voltage (LIN, HIN, RFE, ITRIP) VIN VSS - 5 VCC + 0.3 V —
High-side floating well supply voltage VB1,2,3 -0.3 1225 V —
High-side floating well supply return VS1,2,3 VB1,2,3 - VB1,2,3 V —
voltage 25 + 0.3
Floating gate drive output voltage VHO1,2,3 VS1,2,3 - VB1,2,3 V —
0.3 + 0.3
Low-side output voltage VLO1,2,3 - 0.3 VCC + 0.3 V —
Logic ground VSS VCC - 25 VCC + 0.3 V —
Allowable VS offset supply transient dVS/dt — 50 V/ns —
relative to COM
Package power dissipation PD — 1.3 W TA +25ºC
Thermal resistance, junction to ambient RthJA — 75 °C/W —
Junction temperature TJ — 150 °C —
Storage temperature TS -55 150 °C —
Lead temperature (soldering, 10 seconds) TL — 300 °C —

Datasheet 6
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Recommended operating conditions

4 Recommended operating conditions

Table 3 Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with
supplies of (VCC - COM) = (VB - VS) = 15 V.
Parameter Symbol Values Unit Note or Test
Condition
Min. Max.
Low-side supply voltage VCC 1ϯ 20 V —
Logic input voltage (LIN, HIN, ITRIP) VIN VSS VSS + 5 V —
RFE logic input voltage VRFE VSS VCC V —
High-side floating well supply voltage VB1,2,3 VS1,2,3 VS1,2,3 V —
+ 12 + 20
High-side floating well supply offset VS1,2,3 COM – 8 900 V 1)

voltage
Transient High-side floating well supply VSt -100 1000 V 2)

offset voltage
Floating gate drive output voltage VHO1,2,3 VS1,2,3 VB1,2,3 V —
Low-side output voltage VLO1,2,3 0 VCC V —
Logic ground VSS -5 5 V —
Ambient temperature TA -40 125 °C —

1 Logic operation for VS of –8 V to 1200 V. Logic state held for Vs of –8 V to –VBS

2 In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC
and VBx. Insensitivity of bridge output to negative transient voltage up to –100 V is not subject to production
test – verified by design / characterization.
Datasheet 7
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Electrical characteristics

5 Electrical characteristics

5.1 Static electrical characteristics

Table 4 Static electrical characteristics
(VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective
output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to
VS.
Parameter Symbol Values Unit Note or Test
Condition
Min. Typ. Max.
VBS supply under voltage positive VBSUV+ 9.2 10.4 11.6 V —
threshold
VBS supply under voltage negative VBSUV- 8.3 9.4 10.5 V —
threshold
VBS supply under voltage hysteresis VBSUVHY — 1 — V —
VCC supply under voltage positive VCCUV+ 10.2 11.4 12.6 V —
threshold
VCC supply under voltage negative VCCUV- 9.3 10.4 11.5 V —
threshold
VCC supply under voltage hysteresis VCCUVHY — 1 — V —
High level output voltage drop, VBIAS- VOH — 0.35 — V Io = 20 mA
VO
Low level output voltage drop, VO VOL — 0.15 — V Io = 20 mA
Logic “1” input voltage VIH 2.3 — — V —
Logic “0” input voltage VIL — — 0.7 V —
RFE positive going threshold VRFE+ 1.7 1.9 2.3 V —
RFE negative going threshold VRFE- 0.7 0.9 1.1 V —
ITRIP positive going threshold VITRIP+ 0.475 0.500 0.525 V —
ITRIP negative going threshold VITRIP- 0.425 0.450 0.475 V —
ITRIP hysteresis VITRIP HYS — 0.050 — V —
High-side floating well offset supply ILK — — 50 µA VB = VS = 1200
leakage V
Quiescent VBS supply current IQBS — 175 250 µA VIN = 0 V or 5 V
Quiescent VCC supply current IQCC — 1000 1500 µA VIN = 0 V or 5 V
Mean output current for load capacity IO+ mean 200 300 — mA C = 22 nF
charging from 3 V (20%) to 6 V (40%)

Datasheet 8
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Electrical characteristics

Table 4 Static electrical characteristics (continued)

(VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective
output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to
VS.
Parameter Symbol Values Unit Note or Test
Condition
Min. Typ. Max.
Mean output current IO- mean 400 600 — mA C = 22 nF
for load capacity discharging from
10.5 V (70%) to 7.5 V (50%)Mean
Output current for load capacity
charging from 3V (20%) to 6 V (40%)
supply current
Output high short circuit pulsed IO+ — 350 — mA VO = 0 V
current PW ≤ 1 µs
Output low short circuit pulsed IO- — 650 — mA VO = 15 V
current PW ≤ 1 µs
Logic “1” Input bias current (RFE) IRFE+ — 0 1 µA VRFE = 3.3 V
Logic “0” Input bias current (RFE) IRFE- 1 0 — µA VRFE = 0 V
Logic “1” Input bias current (LIN, IIN+ — 1000 1250 µA VIN = 5 V
HIN)
Logic “0” Input bias current (LIN, IIN- — — 1 µA VIN = 0 V
HIN)
Logic “1” Input bias current (ITRIP) IITRIP+ — 15 25 µA VIN = 1 V
Logic “0” Input bias current (ITRIP) IITRIP- — — 1 µA VIN = 0 V
Bootstrap diode on resistance RBS — 120 150 Ω —
Bootstrap diode forward voltage VFBSD — 0.9 — V Io = 0.3 mA
drop
RFE mos resistance RON, RFE — 40 60 Ω —

Please refer to Application Section for integrated bootstrap diode description.

5.2 Dynamic electrical characteristics

Table 5 Dynamic electrical characteristics
VCC = VB = 15 V, VS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Parameter Symbol Values Unit Note or Test
Condition
Min. Typ. Max.
Turn-on propagation delay tON 500 700 900 ns
Turn-off propagation delay tOFF 450 650 850 ns
Turn-on rise time tR — 35 — ns

Datasheet 9
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Electrical characteristics

Table 5 Dynamic electrical characteristics (continued)

VCC = VB = 15 V, VS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Parameter Symbol Values Unit Note or Test
Condition
Min. Typ. Max.
Turn-off fall time tF — 20 — ns
Dead time, LO turn-off to HO turn-on & DT 300 460 700 ns
HO turn-off to LO turn-on
Delay matching time (tON, tOFF) MT — — 130 ns
Enable low to output shutdown tEN — 600 — ns
propagation delay
Input filter time (LIN, HIN, EN) TFIL,IN 200 350 500 ns
FAULT clear time TFLTCLR — 1.9 — ms VDD = 3.3V
(R = 2 MΩ, C = 1 nF)
ITRIP to output shutdown propagation TITRIP — 750 1250 ns VITRIP = 1 V
delay
ITRIP blanking time TBL — 500 — ns
ITRIP to FAULT propagation delay TFLT 450 650 900 ns

Datasheet 10
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

6 Application information and additional details

Information regarding the following topics are included as subsections within this section of the datasheet.
• IGBT/MOSFET gate drive
• Switching and timing relationships
• Deadtime
• Matched propagation delays
• Input logic compatibility
• Undervoltage lockout protection
• Shoot-Through protection
• Enable input
• Fault reporting and programmable fault clear timer
• Over-Current protection
• Truth table: Undervoltage lockout, ITRIP, and ENABLE
• Advanced input filter
• Short-Pulse / Noise rejection
• Integrated bootstrap diodes
• Negative VS transient SOA
• PCB layout tips
• Additional documentation

6.1 IGBT/MOSFET gate drive

The 6ED2230S12T HVICs are designed to drive MOSFET or IGBT power devices. Figure 4 and Figure 5 illustrate
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC,
used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external
power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this
parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side
or low-side output voltage.

VB
(or V CC )

IO+
HO
(or LO)
+
VHO (or VLO)
VS -
(or COM)

Figure 4 HVIC sourcing current

Datasheet 11
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

VB
(or V CC )

HO
(or LO)
IO-

VS
(or COM)

Figure 5 HVIC sinking current

6.2 Switching and timing relationships

The relationships between the input and output signals of the 6ED2230S12T are illustrated below in Figure 6.
From these figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR,
and tF) associated with this device.
PW IN

50% 50%
LIN, HIN

ton toff
tr tf
PWOUT

90% 90%

LO, HO 10% 10%

Figure 6 Switching time waveformsInput/output timing diagram

Figure 7 an Figure 8 illustrate the timing relationships of some of the functionality of the 6ED2230S12T; this
functionality is described in further detail later in this document.
During interval A of Figure 7, the HVIC has received the command to turn-on both the high- and low-side
switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition.
HVIC is keeping on output channel that is already on ignoring the 2nd input signal.
Interval B of Figure 7 an Figure 8 shows that the signal on the ITRIP input pin has gone from a low to a high
state; as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state;
LO is also held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has
returned to the low state, the output will remain disabled and the fault condition reported until the voltage on
the RFE pin charges up to VRFE+ threshold; the charging characteristics are dictated by the RC network attached
to the RFE pin. After fault clear time HVIC is waiting for a new input signal on LIN/HIN before activate the output
stage (LO/HO).
During interval C of Figure 7 an Figure 9, we can see that the RFE pin has been pulled low (as is the case when
the driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and
LO) being held in the low state until the RFE pin is pulled high. After an enable event HVIC will wait for a new
input signal on LIN/HIN before activate the output stage (LO/HO).

Datasheet 12
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

A A B C B C

Figure 7 Input/output timing diagram

VIT,TH+
VIT,TH-

ITRIP

RFE VRFE+
50%

tFLT
tFLTCLR
tTRIP

90%
HO, LO

Figure 8 Detailed view of B interval

RFE
VRFE-

tEN

90%
LO, HO

Figure 9 Detailed view of C interval

6.2.1 Deadtime
This HVIC features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
Infineon’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature
inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off;
this is done to ensure that the power switch being turned off has fully turned off before the second power

Datasheet 13
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is
shorter than DT; external deadtimes larger than DT are not modified by the gate driver.

6.2.2 Matched propagation delays

The 6ED2230S12T HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF)
for both the low-side channels and the high-side channels; the maximum difference is specified by the delay
matching parameter (MT). The propagation turn-on delay (tON) of the 6ED2230S12T is matched to the
propagation turn-on delay (tOFF).

HIN 50% 50%

LIN

LO HO

10%
MT MT
90%

LO HO

Figure 10 Delay Matching Waveform Definition

6.3 Input logic compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The 6ED2230S12T has been designed
to be compatible with 3.3 V and 5 V logic-level signals. Figure 11 illustrates an input signal to the 6ED2230S12T,
its input threshold values, and the logic state of the IC as a result of the input signal.

V IH
(IRS23364D)
Input Signal

VIL
Input Logic
Level

High

Low Low

Figure 11 HIN & LIN input thresholds

6.4 Undervoltage lockout protection

This HVIC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply
and the VBS (high-side circuitry) power supply. Figure 12 is used to illustrate this concept; VCC (or VBS) is
plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage
protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally,
if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry

Datasheet 14
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will
transition to the low state to inform the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if
the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could
be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is
high; this could result in very high conduction losses within the power device and could lead to power device
failure.

VCC
(or V BS )

V CCUV+
VCCUV - (or V BSUV+)
(or V BSUV- )

Time

UVLO Protection
(Gate Drive Outputs Disabled)
Normal Normal
Operation Operation

Figure 12 UVLO protection

6.5 Shoot-Through protection

The 6ED2230S12T is equipped with shoot-through protection circuitry (also known as cross-conduction
prevention circuitry). Figure 13 shows how this protection circuitry prevents both the high- and low-side
switches from conducting at the same time.

Shoot-through Shoot-through
protection enabled protection enabled

HIN HIN
LIN LIN

HO HO

LO LO

Figure 13 Illustration of shoot-through protection circuitry

6.6 Enable input

The 6ED2230S12T provides an enable functionality that allows it to shutdown or enable the HVIC. When the RFE
pin is in the high state the HVIC is able to operate normally (assuming no other under voltage fault conditions
on Vcc). When the RFE pin is in a low state, the gate drive outputs are pulled low until the enable condition is

Datasheet 15
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

restored. The enable circuitry of the 6ED2230S12T features an input filter; the minimum input duration is
specified by tFIL, IN. Please refer to the RFE pin parameters VRFE+, VRFE-, and IRFE for the details of its use.

6.7 Fault reporting and programmable fault clear timer

The 6ED2230S12T provides an integrated fault reporting output and an adjustable fault clear timer. There are
two situations that would cause the HVIC to report a fault via the RFE pin. The first is an undervoltage condition
of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the RFE pin is
internally pulled to Vss and the fault clear timer is activated. The RFE output stays in the low state until the fault
condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on
the RFE pin will return to its external pull-up voltage.
The length of the fault clear time period (tFLTCLR) is determined by a fix time constant added to exponential
charging characteristics of the capacitor where the time constant is set by RRFE and CRFE. Figure 14 shows that
RRFE is connected between the external supply (VDD) and the RFE pin, while CRFE is placed between the RFE
and Vss pins.

VCC
HIN U HIN
LIN U LIN
HIN V
LIN V
uC HIN W
LIN W
VDD HO
GK RRFE VS
RFE
CRFE LO
Vss
ITRIP

DC - BUS R

Figure 14 Programming the fault clear timer

The design guidelines for this network are shown in Table 6.

Table 6 Design guidelines

CRFE ≤1 nF
Ceramic
RRFE 0.5 MΩ to 2 MΩ
>> RON,REF

The length of the fault clear time period can be determined by using the formula below.
uC(t) = Vf*(1-e-t/RC)
tFLTCLR = -(RRFE*CRFE)*ln(1-VRFE+ /VDD) + 160 µs
The voltage on the RFE pin should not exceed the VDD of the uC power supply.

Datasheet 16
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

6.8 Over-Current protection

The 6ED2230S12T HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-
current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs
are shutdown, and RFE is pulled to Vss.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e.,
R0, R1, and R2) connected to ITRIP as shown in Figure 15, and the ITRIP threshold (VITRIP+). The circuit designer
will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that
the voltage at node VX reaches the over-current threshold (VITRIP+) at that current level.
VITRIP+ = R0*IDC-(R1/(R1+R2))

DC BUS +
Vcc
VB
Hin
Lin
HO
RFE
ITRIP
VS To load

LO

VSS COM
R1 R2

DC BUS - Vx

R0 IDC-
Figure 15 Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed
to exceed 5 V; if necessary, an external voltage clamp may be used.

6.9 Truth table: Undervoltage lockout, ITRIP, and ENABLE

Table 7 provides the truth table for the 6ED2230S12T. The first line shows that the UVLO for VCC has been
tripped; the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in
this case and when VCC is greater than VCCUV, the FAULT output returns the driver is functional.
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have
been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new
rising transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that
the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled. This condition is
stored in the external RC network waiting for fault clear time. The last case shows when the HVIC has received
an enable command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled.

Table 7 Truth table

VCC VBS ITRIP RFE LO HO
UVLO VCC <VCCUV — — 0 0 0

Datasheet 17
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

Table 7 Truth table (continued)

VCC VBS ITRIP RFE LO HO
UVLO VBS 15 V <VBSUV 0V HIGH LIN 0
Normal operation 15 V 15 V 0V HIGH LIN HIN
ITRIP fault 15 V 15 V >VITRIP+ 0 0 0
Enable command 15 V 15 V 0V 0 0 0

6.10 Advanced input filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to
reject noise spikes and short pulses. This input filter has been applied to the HIN ans LIN inputs. The working
principle of the new filter is shown in Figure 17.
Figure 16 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer than tFIL,IN; the resulting output is
approximately the difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2)
show an input signal with a duration slightly longer than tFIL,IN; the resulting output is approximately the
difference between the input signal and tFIL,IN.
Figure 17 shows the advanced input filter of the 6ED2230S12T and the symmetry between the input and
output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer than
tFIL,IN; the resulting output is approximately the same duration as the input signal. The lower pair of
waveforms (Example 2) show an input signal with a duration slightly longer than tFIL,IN; the resulting output is
approximately the same duration as the input signal.

IN tFIL,IN
Example 1

OUT

IN tFIL,IN
Example 2

OUT

Figure 16 Typical input filter

IN tFIL,IN
Example 1

OUT

IN tFIL,IN
Example 2

OUT

Figure 17 Advanced input filter

Datasheet 18
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

6.11 Short-Pulse / Noise rejection

This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration
of the input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 18 shows the input
and output in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change
states. Example 2 of Figure 18 shows the input and output in the high state with negative noise spikes of
durations less than tFIL,IN; the output does not change states.

Example 1 IN tFIL,IN

OUT

IN tFIL,IN
Example 2

OUT

Figure 18 Noise rejecting input filters

6.12 Integrated bootstrap diodes

The 6ED2230S12T embeds three integrated ultra-fast bootstrap diodes that allow an alternative drive of the
bootstrap supplies for a wide range of applications. The resistance of the diode (RBS) helps to avoid high inrush
currents when charging the bootstrap capacitance.
The bootstrap diode is connected between the floating supply VB and VCC (see Figure 19).

RBS Diode
Vcc Vb

Figure 19 Simplified bootstrap diode connection

The bootstrap diode is suitable for all PWM modulation schemes, including trapezoidal control, and can be used
either in parallel with the external bootstrap network (diode+ resistor) or as a replacement of it.

6.13 Tolerant to negative VS transients

A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase
inverter circuit is shown in Figure 20; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figure 21 and Figure 22) switches off, while the U phase current is
flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in
parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings
from the positive DC bus voltage to the negative DC bus voltage.

Datasheet 19
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

DC+ BUS

Q1 D1 Q3 D3 D5
Q5

W
V VS3 To
Input U VS2
Voltage VS1 Load

Q2 D2 Q4 D4 D6
Q6

DC- BUS

Figure 20 Three phase inverter

DC+ BUS

Q1
ON

IU
VS1

D2
Q2
OFF

DC- BUS

Figure 21 Q1 conducting

DC+ BUS

D1
Q1
OFF

V S1
IU

D2
Q2
OFF

DC- BUS

Figure 22 D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figure 23 and Figure 24),
and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage
node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage.

Datasheet 20
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

DC+ BUS

D3
Q3
OFF

IV
V S2

D4
Q4
OFF

DC- BUS

Figure 23 D3 conducting

DC+ BUS

D3
Q3
OFF

V S2
IV

Q4
ON

DC- BUS

Figure 24 Q4 conducting
However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but
instead swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figure 26 and Figure 27 show a
simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the
power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the
high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and
the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily
flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in
these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load
and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher
potential than the VS pin).

Datasheet 21
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

DC+ BUS

LC1

Q1 D1

LE1
VS1
LC2

Q2 D2

LE2

DC- BUS

Figure 25 Parasitic elements

DC+ BUS
+
V LC1
-

Q1
ON
+
VLE1 IU
-
VS1

D2
Q2
OFF

DC- BUS

Figure 26 VS positive

DC+ BUS

D1
Q1
OFF

V S1 -
VLC2 IU
+
-
Q2
V D2
OFF +

-
VLE2
+

DC- BUS

Figure 27 VS negative

Datasheet 22
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS
transient voltage can exceed this range during some events such as short circuit and over-current shutdown,
when di/dt is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications.
An indication of the 6ED2230S12T’s robustness can be seen in Figure 28, where the 6ED2230S12T Safe
Operating Area is shown at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage
falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional
anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside the SOA.

Figure 28 Negative VS transient SOA for 6ED2230S12T @ VBS=15V

Even though the 6ED2230S12T has been shown to be able to handle these large negative VS transient
conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much
as possible by careful PCB layout and component use.

6.14 PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied
to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the
Case Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the
high voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
29). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Datasheet 23
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

VBX IGC
(or VCC)
CGC
HOX RG

(or LOX)
Gate Drive
Loop
VGE
VSX
(or COM)

Figure 29 Antenna loops

Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A
ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as close as
possible to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients
at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such
conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)
minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain
excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between
the VS pin and the switch node (see Figure 27), and in some cases using a clamping diode between COM and VS
(see Figure 31). See DT04-4 at http://www.infineon.com for more detailed information.

DC+ BUS
DBS

VCC VB

CBS

HO

VS RVS
To
HVIC

Load
LO

COM

V SS

DC- BUS

Figure 30 VS resistor

Datasheet 24
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

DC+ BUS
DBS

VCC VB

CBS

HO

VS RVS
HVIC To
DVS
Load
LO

COM

VSS

DC- BUS

Figure 31 VS clamping diode

6.15 Additional documentation

Several technical documents related to the use of HVICs are available at http://www.infineon.com; use the Site
Search function and the document number to quickly locate them. Below is a short list of some of these
documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs

Datasheet 25
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Package information

7 Package information

7.1 Package information DSO-24 (DSO-28 4 pins removed)

Figure 32 Package outline

Figure 33 Tape and Reel details

Figure 34 Marking information PG-DSO-24 (DSO-28 4 pins removed)

Datasheet 26
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Qualification information

8 Qualification information
Table 8 Qualification information 1)
Qualification Level Industrial 2)

Note: This family of ICs has passed JEDEC’s

Industrial qualification. Consumer
qualification level is granted by extension
of the higher Industrial level.

Moisture Sensitivity Level DSO-24 MSL3 3), 260 °C

(per IPC/JEDEC J-STD-020)
ESD Human Body Model Class 2
(per JEDEC standard JESD22-A114)
Charged Device Model Class C4
(per JEDEC standard JS-022-2014)
IC Latch-Up Test Class II Level A
(per JESD78)
RoHS Compliant Yes

1 Qualification standards can be found at Infineon’s web site www.infineon.com

2 Higher qualification ratings may be available should the user have such requirements. Please contact your
Infineon sales representative for further information.
3 Higher MSL ratings may be available for the specific package types listed here. Please contact your
Infineon sales representative for further information.
Datasheet 27
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Related products

9 Related products
Table 9 Related products
Product Description
Gate Driver ICs
IR2214SS 1200 V Half-bridge gate driver with integrated dead-time, desaturation detection
(DESAT), soft over-current shutdown, synchronized shutdown, two-stage turn-on
for di/dt control, separate pull-up/pull-down output drive pins, matched
propagation delays, and independent UVLO with hysteresis.
IR2213S 1200 V High and Low side gate driver with cycle by cycle shutdown logic,
independent UVLO with hysteresis, matched propagation delays, and separate logic
and power grounds.
IR2238Q 1200 V Three-phase motor controller with integrated programmable dead-time,
desaturation detection (DESAT), brake chopper driver with protection, soft over-
current shutdown, synchronized shutdown, hard shutdown, two-stage turn-on for
dI/dt control, separate pull-up/pull-down output drive pins, matched propagation
delays, and independent UVLO with hysteresis.
Power Switches
IKW15N120BH6 High Speed 1200 V, 15 A/40 A/75 A hard-switching TRENCHSTOP™ IGBT6 co-packed
IKW40N120CS6 with a very soft and fast recovery anti-parallel diode in a TO247
package/TO247PLUS 3pin package
IKW08T120 The 1200 V, 8 A/15 A/25 A/40 A hard-switching TRENCHSTOP™ IGBT3 co-packed
IKW15N120T2 with free-wheeling diode in a TO247 package, provides significant improvement of
IKW25N120T2 static as well as dynamic performance of the device, due to combination of trench-
IKW40N120T2 cell and fieldstop concept.
IKQ40N120CT2 Infineon introduces the new package TO-247PLUS for 1200 V IGBT with increasing
amounts of silicon in smaller, space saving packages with 40 A/50 A/75 A.
Power Modules
FP15R12W1T4 EasyPIM™ 1B/2B 1200 V, 15 A/35 A PIM IGBT module with fast Trench/Fieldstop IGBT4,
FP15R12W2T4 Emitter Controlled 4 diode and NTC.
FP35R12W2T4
FP15R12W1T4_B11 EasyPIM™ 1B 1200 V, 15 A PIM IGBT module with fast Trench/Fieldstop IGBT4, Emitter
Controlled 4 diode, NTC and PressFIT Contact Technology.
FS25R12W1T4 EasyPACK™ 1B 1200 V, 25 A/35 A sixpack IGBT module with Trench/Fieldstop IGBT4,
FS35R12W1T4 Emitter Controlled 4 diode and NTC.
FS25R12W1T4_B11 EasyPACK™ 1B 1200 V, 25 A sixpack IGBT module with Trench/Fieldstop IGBT4,
Emitter Controlled 4 diode, NTC and PressFIT Contact Technology.
iMOTIONTM Controllers
IRMCK099 iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field
Oriented Control (FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T High performance Motor Control IC for variable speed drives based on Field
Oriented Control (FOC) of permanent magnet synchronous motors (PMSM).

Datasheet 28
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Revision history

Revision history
Document Date of Description of changes
version release
1.0 2018-03-27 First Release Version
1.1 2018-12-14 Update the ITRIP to output shutdown propagation delay Max. value
1.2 2019-08-05 Editorial change
1.3 2020-03-10 Editorial change

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