Name: Olalekan Isreal Feranmi

Matric No: 23D/7CS/665

Level: 200L
Course code: CSC 205
Department: Computer science

CSC 205(Assembly Language Programming) Assignment

1a i)Assembly language is a low-level programming language that is closely
related to the machine language of a computer. It is often referred to as a
"symbolic representation" of machine code because it uses mnemonic
instructions and symbols to represent the machine instructions and memory
addresses.

ii) - Label
- opcode
- operands
- comments

iii) 1. Efficiency: Assembly language allows for fine-grained control over the
hardware, enabling programmers to write highly optimized code. It allows direct
access to registers, memory, and other low-level operations, resulting in faster
and more efficient execution.

2. Hardware Interaction: Assembly language provides a direct interface with

the underlying hardware. It allows programmers to access and manipulate
hardware registers, I/O ports, and other hardware-specific features, making it
suitable for tasks that require low-level hardware control.

3. Size and Speed: Assembly language programs tend to be smaller and faster
compared to programs written in higher-level languages. Since assembly
language instructions directly map to machine instructions, there is no overhead
of interpretation or translation, resulting in compact and efficient code.

4. Embedded Systems and Device Drivers: Assembly language is commonly

used in embedded systems and device driver development. These systems often
require precise control over hardware resources and real-time responsiveness,
making assembly language a preferred choice for such applications.

bi) 1. Low-level and complex: Machine language instructions are represented in

binary, which makes them difficult to read and understand for humans. Each
instruction is represented by a sequence of 0s and 1s, making programming and
debugging complex and error-prone.

2. Lack of Abstraction: Machine language instructions directly correspond to

specific hardware operations, such as memory access and arithmetic
calculations. This lack of abstraction makes it challenging to write and maintain
code, as programmers have to deal with the intricacies of the hardware
architecture.

3. Time-consuming Programming: Writing programs in machine language is a

time-consuming process. Since each instruction is represented in binary,
programmers need to manually translate their high-level logic into sequences of
0s and 1s, which is a tedious and error-prone task.

4. Portability Issues: Machine language programs are highly dependent on the

specific hardware architecture they are written for. This lack of portability means
that programs written in machine language may not be compatible with different
computer systems or require significant modifications to run on different platforms.

bii) 1. Compiler: A compiler is a language translator that converts the entire

source code written in a high-level programming language into machine code or
executable code in one go. It goes through several stages, such as lexical
analysis, syntax analysis, semantic analysis, code optimization, and code
generation. The resulting compiled code can be executed directly by the
computer's hardware.

2. Interpreter: An interpreter is a language translator that converts and executes

the source code line by line, without creating a separate compiled output. It reads
each line of the source code, translates it into machine code, and immediately
executes it. Interpreters are often used in scripting languages and provide a more
interactive and dynamic programming environment.

3. Assembler: An assembler is a language translator specifically designed for

assembly language. It converts assembly language code, which uses mnemonic
instructions and symbols, into machine code. Unlike compilers and interpreters,
assemblers directly convert assembly language instructions into their
corresponding machine instructions, without any high-level language constructs.
2ai) Registers in the CPU are small, high-speed storage areas that hold data and
instructions that the CPU needs to access quickly. They are like temporary
storage spaces within the CPU itself.

ii) 1. Accumulator: The accumulator is a general-purpose register that stores

intermediate results during arithmetic and logical operations. It

2. Program Counter (PC): The program counter is a special-purpose register

that keeps track of the memory address of the next instruction to be executed.

3. Instruction Register (IR): The instruction register holds the current

instructions being executed by the cpu.

4. Memory Address register(MAR): it hold the memory address of data or

instructions that the cpu needs to access..

5. Memory Data register(MDR): it holds the actual data being read from or
written to memory.

2b i) 1. Instruction Set Complexity: CISC processors have a complex instruction

set, meaning they support a wide variety of instructions that can perform complex
operations in a single instruction. RISC processors, on the other hand, have a
reduced instruction set and focus on simpler, more basic instructions.
 2. Instruction Length: CISC instructions tend to be variable in length, ranging
from a few bytes to several bytes long. RISC instructions, on the other hand, are
typically fixed in length and are usually shorter than CISC instructions, which helps
in simplifying the decoding process.

3. Execution Time: Due to the complexity of CISC instructions, they often

require more clock cycles to execute. RISC instructions, being simpler and more
streamlined, can be executed in fewer clock cycles, resulting in potentially faster
execution times.

4. Register Usage: CISC processors often have a larger number of general-

purpose registers, allowing for more flexible programming. RISC processors
typically have a smaller number of registers, which promotes a simpler and more
efficient design.

5. Memory Access: CISC processors often emphasize memory access

instructions, allowing operations to be performed directly on memory. RISC
processors, on the other hand, encourage the use of load-store architectures,
where data must be loaded into registers before operations can be performed on
them.

ii) 1. Random Access Memory (RAM): RAM is a type of primary memory that
provides temporary storage for data that the CPU needs to access quickly. It is
volatile memory, meaning its contents are lost when the power is turned off.

2. Read-Only Memory (ROM): ROM is a type of primary memory that stores

permanent data that cannot be modified or erased. It contains firmware or
instructions that are permanently written during manufacturing and cannot be
changed by normal computer operations.

3a i) 8 nibbles
ii) 8 bytes
iii) 1,024 kilobytes
iv) 65,536 bytes or 64 kilobytes
v) 24,576 bytes
vi) little
vii) 0110110
viii) 9593

b) i) the physical address would be DS:offset, which is 3499H:2500H.

ii) the logical address of the data being fetched would be 2500H.

iii) the lower range of the data segment would be 3499H.

iv) we can't determine the upper range in this case.

4a i) A system bus is a communication pathway that connects the different

components of a computer system. It allows for the transfer of data and
instructions between the CPU, memory, and other peripherals.
ii) Address bus, Data bus
iii) Pipelining is a technique used in computer processors to improve their
performance and execute instructions faster. It involves breaking down the
instruction execution process into smaller stages and allowing multiple
instructions to be processed simultaneously in different stages of the pipeline.
Here's how it works: Instead of waiting for one instruction to complete before
starting the next one, pipelining allows multiple instructions to overlap and
progress through different stages of the pipeline simultaneously. Each stage
performs a specific task, such as instruction fetch, decode, execute, and write
back. This overlapping of instructions in different stages allows for better utilization
of the CPU's resources and improves overall efficiency.

bi) 1) 16-bit architecture: The 8086 introduced a 16-bit architecture, which

allowed for larger memory addressing and increased data processing capabilities
compared to the 8-bit architecture of the 8080/8085.

2) Segmented memory model: The 8086 introduced a segmented memory

model, which allowed for more efficient memory addressing and management. It
divided the memory into segments, each with a maximum size of 64KB, providing
greater flexibility and addressing capabilities.

3) Enhanced instruction set: The 8086 had an expanded instruction set

compared to the 8080/8085, with additional instructions for arithmetic, logical
operations, and string manipulation.
bii) The major difference between the 8080 and 8086 microprocessors is the
architecture. The 8080 is an 8-bit microprocessor, while the 8086 is a 16-bit
microprocessor.

biii) The 8086 has a larger queue. The 8086 microprocessor has a queue size of
6, while the 8080 microprocessor does not have a built-in queue.

5a i) 7C416 + 3BE16 = B7A16

(ii) 59F16 - 2B816 = 2E716
(iii) 23D916 + 94BE16 = B80816
(iv) 11112 + 10102 = 110002
(v) 1110112 + 1010112 = 11010112
(vi) 6A216 + 49A16 = B3C16
(vii) 9FF2516 - 4DD9916 = 520C816
(viii) 106616 + ABCD16 = B33216

b (i) 16-bit general-purpose registers:

- AX (Accumulator Register)
- BX (Base Register)
- CX (Count Register)
- DX (Data Register)

(ii) Pointer registers:

- SP (Stack Pointer)
- BP (Base Pointer)

(iii) Index registers:

- SI (Source Index)
- DI (Destination Index)

(iv) Segment registers:

- CS (Code Segment)
- DS (Data Segment)
- SS (Stack Segment)
- ES (Extra Segment)

6a i) MOV CS, 23AB: In the 8088/86 assembly language, the MOV instruction
cannot be used to directly load a value into the CS (Code Segment) register. The
CS register is automatically set by the processor and cannot be modified directly.

(ii) MOV BL, AX: The MOV instruction in 8088/86 assembly language can only
move data between registers of the same size. The AX register is a 16-bit register,
while the BL register is an 8-bit register. Therefore, direct copying from AX to BL
is not possible.

(iii) MOV AL, 3CB5: The MOV instruction in 8088/86 assembly language can
only move immediate values that fit within the size of the destination register. In
this case, the immediate value 3CB5 is 16 bits, but the AL register is an 8-bit
register. Therefore, it is not possible to directly move this immediate value into AL.

(iv) MOV AX, 36DE5: The MOV instruction in 8088/86 assembly language can
only move immediate values that fit within the size of the destination register. In
this case, the immediate value 36DE5 is 20 bits, but the AX register is a 16-bit
register. Therefore, it is not possible to directly move this immediate value into
AX.

b i) To add the values 16H and ABH and store the result in register AX, you can
use the following assembly language instructions:
MOV AX, 16H
ADD AX, ABH
This will load the value 16H into AX and then add the value ABH to it.

(ii) If AX = 24F6H and the instruction "MOV [1450], AX" is executed, the contents
of the memory locations at offsets 1450 and 1451 will be:

Memory location at offset 1450: F6H

Memory location at offset 1451: 24H

The value in AX is stored in memory in little-endian format, so the lower byte (F6H)
is stored at offset 1450 and the higher byte (24H) is stored at offset 1451.
(iii) Assuming DS = 1120, SI = 2498, and AX = 17FE, the execution of the
instruction "MOV [SI], AX" will store the contents of AX (17FE) in the memory
location pointed to by SI (2498). Therefore, the contents of the memory location
at offset 2498 will be:

Memory location at offset 2498: FEH

Memory location at offset 2499: 17H

Again, the value in AX is stored in memory in little-endian format.

7a i) A stack is a data structure in a computer system that stores information in a

last-in, first-out (LIFO) manner. It is needed in a computer system because it
allows for efficient memory management and helps in organizing and tracking the
execution of programs.

(ii) Decremented, incremented

(iii) PUSH AX:

- SP = 1234
- Contents of memory at SP: B6H
- Contents of memory at SP-1: 24H

PUSH BX:
- SP = 1232
- Contents of memory at SP: C2H
- Contents of memory at SP-1: 85H

PUSH DX:
- SP = 1230
- Contents of memory at SP: 93H
- Contents of memory at SP-1: 5FH

(b) i) -9
ii) 6
iii) 16
iv) -6

8a) i) Carry flag (CF): This flag is set when an arithmetic operation generates a
carry or borrow. It is used for multi-byte arithmetic and bitwise operations.

(ii) Parity flag (PF): This flag indicates the parity (even or odd) of the least
significant byte of the result. It is used for error detection and data integrity checks.

(iii) Auxiliary Carry flag (AF): This flag is used for binary-coded decimal (BCD)
arithmetic operations.
(iv) Zero flag (ZF): This flag is set when the result of an operation is zero. It is
used for conditional jumps and comparisons.

(b) i) MOV BH, 38H

ADD BH, 2FH

- CF: Not affected

- PF: Set if the lower 8 bits of the result have an even number of set bits,
otherwise cleared
- AF: Not affected
- ZF: Set if the result is zero, otherwise cleared
- SF: Set if the result is negative (MSB is 1), otherwise cleared

(ii) MOV BX, 94C2H

ADD BX, 323EH

- CF: Set if the result of the addition generates a carry, otherwise cleared
- PF: Set if the lower 8 bits of the result have an even number of set bits,
otherwise cleared
- AF: Set if the addition generates a carry from bit 3 to bit 4, otherwise cleared
- ZF: Set if the result is zero, otherwise cleared
- SF: Set if the result is negative (MSB is 1), otherwise cleared
9 i) 175910
ii) 0.0112
iii) 23410
iv) 1101101102
v) 1001002
vi) 51.7510
vii) 1010011000112
viii) 2210
ix) 5BA16
x) 1A916
xi) 3D16
xii) 1010102
xiii) 0.1001001012
xiv) 59.62510
xv) 6514810

10a) MOV AL, 99H

MOV [3518], AL:

To calculate the physical address, we use the formula:

Physical Address = DS * 10H + Offset Address
Given DS = 1512H and the offset address is 3518, let's calculate the physical
address:
Physical Address = 1512H * 10H + 3518 = 15120H + 3518 = 18638H

Therefore, the physical address of the memory location is 18638H, and it's content
are 99H

bi) 1. ADD AX, BX: This instruction adds the contents of the BX register to the
AX register and stores the result in the AX register.

2. ADD AX, [BX]: This instruction adds the value at the memory location pointed
to by the Bx register to the Ax register and stores the result in the Ax register.

ii) 1. Immediate addressing: The operand is a constant value specified in the

instruction itself.

2. Register addressing: The operand is in one of the general-purpose registers.

3. Direct addressing: The operand is in a memory location specified directly in

the instruction.

4. Indirect addressing: The operand is in a memory location pointed to by a

register.
5. Base addressing: The operand is in a memory location specified by adding an
offset to a base register.

6. Indexed addressing: The operand is in a memory location specified by adding

an offset to an index register.

7. Relative addressing: The operand is in a memory location specified by adding

a displacement to the instruction pointer (IP) register.

11a Given:
DS = 4500H
SS = 2000H
BX = 2100H
SI = 1486H
BP = 7814H
AX = 2512H

(i) MOV [BP] + 12, AX:

To calculate the physical memory location, we add the value of BP (7814H) with
the offset 12.
Physical Address = DS * 10H + (BP + 12)
Physical Address = 4500H * 10H + (7814H + 12)
Physical Address = 45000H + 7826H
Physical Address = 52826H

(ii) MOV [SI] + 10, AX:

To calculate the physical memory location, we add the value of SI (1486H) with
the offset 10.
Physical Address = DS * 10H + (SI + 10)
Physical Address = 4500H * 10H + (1486H + 10)
Physical Address = 45000H + 1496H
Physical Address = 46496H

(iii) MOV [BX] + 20, AX:

To calculate the physical memory location, we add the value of BX (2100H) with
the offset 20.
Physical Address = DS * 10H + (BX + 20)
Physical Address = 4500H * 10H + (2100H + 20)
Physical Address = 45000H + 2120H
Physical Address = 47120H

Therefore, the exact physical memory locations where AX is stored in each of the
instructions are:
(i) MOV [BP] + 12, AX: 52826H
(ii) MOV [SI] + 10, AX: 46496H
(iii) MOV [BX] + 20, AX: 47120H

b i) MOV AX, 32DEH:

This instruction uses immediate addressing mode, where the value 32DEH is
directly loaded into the AX register.

(ii) MOV AL, [BX]:

This instruction uses register indirect addressing mode, where the contents of the
memory location pointed to by the BX register are loaded into the AL register.

(iii) MOV DX, [BP + DI + 4]:

This instruction uses based indexed addressing mode, where the sum of the
values in the BP, DI, and 4 registers is used as an offset to access the memory
location. The value stored in that memory location is then loaded into the DX
register.

(iv) MOV AX, DX:

This instruction uses register-to-register addressing mode, where the contents of
the DX register are directly loaded into the AX register.

(v) MOV CX, [BX + 10]:

This instruction uses based indexed addressing mode, similar to (iii), where the
sum of the value in the BX register and 10 is used as an offset to access the
memory location. The value stored in that memory location is then loaded into the
CX register.
(vi) MOV DL, [2400]:
This instruction uses direct addressing mode, where the memory location with the
address 2400H is accessed directly, and the value stored in that memory location
is loaded into the DL register.

(vii) MOV BL, [SI + 10]:

This instruction uses based indexed addressing mode, similar to (iii) and (v),
where the sum of the value in the SI register and 10 is used as an offset to access
the memory location. The value stored in that memory location is then loaded into
the BL register.