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MT7976DAN Datasheet
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802.11ax Wi-Fi RF Chip

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Version: 1.4
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Release date: 2021/11/15

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Document Revision History
Revision Date Author Description

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V1.0 2021/10/22 TM Chen 1. Initial version.

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V1.1 2021/10/25 TM Chen Correct typo for Pin8, 114,120,126
V1.2 2021/11/05 TM Chen Update the Pin name for PA VDD=1.8V

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1. Update TOP marking to MT7976AN for QFN
V1.3 2021/11/08 TM Chen
2. Update supporting frequency band to 5/6GHz
V1.4 2021/11/15 TM Chen POD modified

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Table of Contents

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Document Revision History .............................................................................................................................. 2

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Table of Contents............................................................................................................................................. 3

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1 System Overview ................................................................................................................................... 5

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Functional Block Diagram .................................................................................................................. 5

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Features............................................................................................................................................. 7

2 Pin Definitions ....................................................................................................................................... 8

Pin Layout .......................................................................................................................................... 8

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F IO Definitions .................................................................................................................................... 9

Pin Definitions ................................................................................................................................. 10

3 Electrical Characteristics ...................................................................................................................... 14

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Absolute maximum rating ............................................................................................................... 14

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Recommended operating range ..................................................................................................... 14

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Power Supply Specifications ........................................................................................................... 14

Digital Logic Characteristics............................................................................................................. 15

MT7976DAN TOP Building Blocks ................................................................................................... 17

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Wi-Fi ................................................................................................................................................ 17

4 XO and Bootstrap ................................................................................................................................ 19

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XTAL oscillator ................................................................................................................................. 19

5 Mechanical Information ...................................................................................................................... 20

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Device Physical Dimension/Part Number........................................................................................ 20

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Ordering Information ...................................................................................................................... 24

Lists of Figures and Tables

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Figure 1-1. MT7976DAN block diagram .................................................................................................................. 6

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Figure 2-1. MT7976DAN pin definition ................................................................................................................... 8
Figure 3-1. Timing diagram conventions ............................................................................................................... 15

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Figure 3-2. Rising and falling times diagram ......................................................................................................... 15
Figure 3-3. 2-wire SPI timing diagram ................................................................................................................... 16
Figure 3-4. Wi-Fi 9-wire SPI access ....................................................................................................................... 16

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Figure 4-1. Physical dimension of MT7976DAN .................................................................................................... 20
Figure 4-2. Physical dimension of MT7976DAN .................................................................................................... 24

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Table 2-1. I/O definitions ........................................................................................................................................ 9

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Table 2-2 MT7976DAN common pin descriptions ................................................................................................ 13
Table 3-1 Absolute maximum rating ..................................................................................................................... 14
Table 3-2 Recommended operating range ............................................................................................................ 14
Table 3-3. AVDD18 specifications ......................................................................................................................... 14

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Table 3-4. AVDD33 specifications ......................................................................................................................... 14
Table 3-5. Operating conditions of digital logics ................................................................................................... 16
Table 4-1 XTAL oscillator requirement .................................................................................................................. 19
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1 System Overview

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Functional Block Diagram

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MT7976DAN is an IEEE WiFi 6 MIMO RF chip which contains 2.4 GHz WI-Fi transceiver front-ends and 5 GHz

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Wi-Fi transceiver front-ends in a DRQFN package. Simplified block diagram and how MT7976DAN is used are
shown in Figure 1-1. The top control logics control each subsystem independently. Each subsystem also has
dedicated LDOs. A thermal sensor and a low-speed ADC (Analog-to-Digital Converter) are provided to monitor

co T
MT7976DAN’s temperature variation. MT7976DAN has its dedicated crystal oscillator (XO) circuit. Besides, XO
circuit provides an external clock source to other chips in the platform.

sz. EN
The transceiver front-ends are on MT7976DAN while the ADC/DAC (Analog-to-Digital Converter/Digital-to-
Analog Converter) is in the companion modem chip. The interface drivers/receiver buffers are designed to

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drive PCB trace loading.
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XO IN
MT7976DA

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555G
G WiFi
WiFi
G2G
WiFi RF
RF
RFRF

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WiFi

LNA
LNA 2G RX
LNA
LNA

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55GG RF
5 G RF
RF
WiFi_2G Tx/ Rx IQ TRx
WIFI
TRx
TRx

sz. EN
PA 2G TX

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F
3-
3-
3-
wire
wire
3- wire
wire
Ctrl
Ctrl
Ctrl
Ctrl
g@ N

555G
G WiFi
WiFi
G5G
WiFi RF
RF
RFRF
WiFi
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LNA
LNA 5G RX
LNA
LNA
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55GG RF
5 G RF
RF
WiFi_5G Tx/ Rx IQ TRx
WIFI
TRx
TRx

PA 5G TX
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Figure 1-1. MT7976DAN block diagram

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Features

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 MT7976DAN is an IEEE WiFi 6 MIMO RF chip which contains 2.4 GHz WI-Fi transceiver front-ends and 5
GHz Wi-Fi transceiver front-ends in a DRQFN package.

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1.2.1 Wi-Fi Transceiver

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WLAN

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 Dual-band (2.4GHz and 5/6GHz) MIMO 802.11 a/b/g/n/ac/ax RF, 20/40/80/160MHz bandwidth
 Built-in calibrations for PVT variation

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 Supports external PA and LNA for WiFi-2.4GHz and WiFi-5/6GHz.

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2 Pin Definitions (draft)

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Pin Layout

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MT7976DAN uses DRQFN package of with 12.5mm x 10mm dimension.

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AVDD18_WF0_TX_GA

AVDD33_WF3_TX_GA
AVDD33_WF0_TOP

AVDD18_WF0_TOP

PDET4/ RCAL

WF2_A_RFIO

WF3_A_RFIO

WF4_A_RFIO
ANTSEL_1

ANTSEL_3

WF2_RXA

WF3_RXA

WF4_RXA
PDET0

PDET2

GND

GND

GND

GND

GND
NC

NC
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sz. EN
AVDD33_WF0_TX_GA

AVDD18_WF3_TX_GA
AVDD18_WF2_PA_A

AVDD18_WF3_PA_A

AVDD18_WF4_PA_A
AVDD18_WF0_DIG

ANTSEL_0

ANTSEL_2

ANTSEL_4
PDET1

PDET3
GND

GND

GND

GND

GND
NC

NC

NC
NC
WF1_RXG
GND
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WF1_TXG_RFIO
F NC
GND
AVDD18_WF1_PA_G
1
2
3
4
5
6
7
8
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104

103
102
101
100
99
98
97
96
GND
AVDD18_WF3_DIG
AVDD18_WF0_SX
NC
AVDD33_WF3_TOP
AVDD18_WF3_TOP
GND
WF0_RXG AVDD18_WF3_SX
NC 9 95 GND
GND 10 94 AVDD33_WF_SX
GND 11 93 ANTSEL_15
12 92
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WF0_TXG_RFIO ANTSEL_14
AVDD18_WF0_PA_G 13 91 ANTSEL_13
90
MT7976DA
GND 14
15 89 ANTSEL_12
AVDD18_WF0_IO ANTSEL_11
PAD_PMU_POR_B_V18 16 88 ANTSEL_10
87
DRQFN 144 Pin
PAD_TOP_CLK 17
18 86 ANTSEL_9
PAD_CBA_RESETB ANTSEL_8
PAD_DIG_RESETB 19 85 ANTSEL_7
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PAD_XO_REQ 20 84 ANTSEL_6
PAD_SLP_CLK 21 83 ANTSEL_5
PAD_TOP_DATA 22 82 GND
PAD_WF_HB1 23 81 GND
PAD_WF_HB2 24 80 AVDD33_XO
PAD_WF_HB3 25 79 XO_IN
PAD_WF_HB4 26 78 XO_INB
AVDD33_XOBUF 27 77 XO_BUF_IN
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AVDD33_ESD 28 76 XO_COCLK
GND 29 75 GND
XO_OUT 30 74 GND
31 73
NC NC
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PAD_WF_HB0_B

PAD_WF_HB10
PAD_WF_HB6

PAD_WF_HB8

WF0_QP

WF1_QP

WF2_QP

WF3_QP

WF4_QP
WF0_IN

WF1_IN

WF2_IN

WF3_IN

WF4_IN
GND

GND

GND

GND

GND
din TE PAD_WF_HB0

PAD_WF_HB5

PAD_WF_HB7

PAD_WF_HB9

WF0_QN

WF1_QN

WF2_QN

WF3_QN

WF4_QN
WF0_IP

WF1_IP

WF2_IP

WF3_IP

WF4_IP
GND

GND

GND

GND

GND

GND
NC

NC
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Figure 2-1. MT7976DAN pin definition

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IO Definitions

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The IO definitions used in Table 2-1 are listed below.

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Table 2-1. I/O definitions

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Pad attribute
AI Analog input (excluding pad circuitry)
AO Analog output (excluding pad circuitry)

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AIO Analog bidirectional (excluding pad circuitry)
DIO Bidirectional digital with CMOS input

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DI Digital input (CMOS)
DO Digital output (CMOS)
Z High-impedance (high-Z) output
NP No internal pull
PU
PD
ADIO
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F Internal pull-high
Internal pull-low
Analog and digital IO (excluding pad circuitry)
Power Voltage supply
g@ N
GND Ground
NC No connection
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Pin Definitions

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Details pin descriptions of MT7976DAN are listed in the following table.

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DRQFN Pin Name Pin description PU/PD I/O Supply domain

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GND pins
4,5,10,11,
14,29,41,42,

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45,48,51,54,
57,60,63,66,
69,74,75,81,

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82,95,98,101, GND GND N/A GND
107,108,
113,114,
119,120,

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125,126,
127,140 F
g@ N

1,3,9,31,
32,72,73,103,
NC NC N/A NC
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104,110,116,
122,144
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79 XO_IN Crystal positive input N/A AI

78 XO_INB Crystal negative input N/A AI

77 XO_BUF_IN external clock input N/A AI

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80 AVDD33_XO XO 3.3v power supply N/A Power

27 AVDD33_XOBUF XO 3.3v power supply N/A Power

76 XO_COCLK XTAL buffered clock output N/A AO

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30 XO_OUT XTAL buffered clock output N/A AO

WIFI Power supply

13 AVDD18_WF0_PA_G RF 1.8v power supply N/A Power

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7 AVDD18_WF1_PA_G RF 1.8v power supply N/A Power

143 AVDD18_WF0_TX_GA RF 1.8v power supply N/A Power

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142 AVDD33_WF0_TX_GA RF 3.3v power supply N/A Power

124 AVDD18_WF2_PA_A RF 1.8v power supply N/A Power

118 AVDD18_WF3_PA_A RF 1.8v power supply N/A Power

112 AVDD18_WF4_PA_A RF 1.8v power supply N/A Power

106 AVDD18_WF3_TX_GA RF 1.8v power supply N/A Power

105 AVDD33_WF3_TX_GA RF 3.3v power supply N/A Power

141 AVDD33_WF0_TOP RF 3.3v power supply N/A Power

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138 AVDD18_WF0_DIG RF 1.8v power supply N/A Power

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139 AVDD18_WF0_TOP RF 1.8v power supply N/A Power

99 AVDD18_WF3_DIG RF 1.8v power supply N/A Power

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100 AVDD18_WF3_TOP RF 1.8v power supply N/A Power

102 AVDD33_WF3_TOP RF 3.3v power supply N/A Power

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97 AVDD18_WF0_SX RF 1.8v power supply N/A Power

96 AVDD18_WF3_SX RF 1.8v power supply N/A Power

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94 AVDD33_WF_SX RF 3.3v power supply N/A Power

15 AVDD18_WF0_IO RF 1.8v power supply N/A Power

sz. EN
28 AVDD33_ESD RF 3.3v power supply N/A Power

WIFI Radio Frequency interface

137 PDET0 External TSSI DC input N/A AI

136

135

134
PDET1

PDET2

PDET3
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F External TSSI DC input

External TSSI DC input

External TSSI DC input

N/A

N/A

N/A
AI

AI

AI

133 PDET4 External TSSI DC input

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123 WF2_A_RFIO RF A-band RF port N/A AIO

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117 WF3_A_RFIO RF A-band RF port N/A AIO

111 WF4_A_RFIO RF A-band RF port N/A AIO

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6 WF1_TXG_RFIO RF G-band RF port N/A AIO

12 WF0_TXG_RFIO RF G-band RF port N/A AIO

8 WF0_RXG G-band External LNA input N/A AI

2 WF1_RXG G-band External LNA input N/A AI

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121 WF2_RXA A-band External LNA input N/A AI

115 WF3_RXA A-band External LNA input N/A AI

109 WF4_RXA A-band External LNA input N/A AI

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WIFI Analog interface

47 WF0_IP WF0 IF TRX IQ signals N/A AIO

46 WF0_IN WF0 IF TRX IQ signals N/A AIO

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44 WF0_QP WF0 IF TRX IQ signals N/A AIO

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43 WF0_QN WF0 IF TRX IQ signals N/A AIO

53 WF1_IP WF1 IF TRX IQ signals N/A AIO

52 WF1_IN WF1 IF TRX IQ signals N/A AIO

50 WF1_QP WF1 IF TRX IQ signals N/A AIO

49 WF1_QN WF1 IF TRX IQ signals N/A AIO

59 WF2_IP WF2 IF TRX IQ signals N/A AIO

58 WF2_IN WF2 IF TRX IQ signals N/A AIO

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56 WF2_QP WF2 IF TRX IQ signals N/A AIO
WF2 IF TRX IQ signals

N
55 WF2_QN N/A AIO

65 WF3_IP WF3 IF TRX IQ signals N/A AIO

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64 WF3_IN WF3 IF TRX IQ signals N/A AIO

62 WF3_QP WF3 IF TRX IQ signals N/A AIO

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61 WF3_QN WF3 IF TRX IQ signals N/A AIO

71 WF4_IP WF4 IF TRX IQ signals N/A AIO

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70 WF4_IN WF4 IF TRX IQ signals N/A AIO

68 WF4_QP WF4 IF TRX IQ signals N/A AIO

sz. EN
67 WF4_QN WF4 IF TRX IQ signals N/A AIO

Digital IOs

Hardware reset from DI

19 PAD_DIG_RESETB PU/PD DVDDIO

18

20
tw ID
PAD_CBA_RESETB
F
PAD_XO_REQ
companion modem
software reset from
companion modem
XO enable control from
PU/PD

PU/PD
DI

DI
DVDDIO

DVDDIO
companion modem
21 PAD_SLP_CLK Sleep CLK input/output PU/PD DIO DVDDIO
g@ N

22 PAD_TOP_DATA TOP 2-wire data signal PU/PD DIO DVDDIO

on O

17 PAD_TOP_CLK TOP 2-wire clock signal PU/PD DI DVDDIO

40 PAD_WF_HB10 WF high speed control bus PU/PD DIO DVDDIO

gy K C

39 PAD_WF_HB9 WF high speed control bus PU/PD DIO DVDDIO

38 PAD_WF_HB8 WF high speed control bus PU/PD DIO DVDDIO

37 PAD_WF_HB7 WF high speed control bus PU/PD DIO DVDDIO

36 PAD_WF_HB6 WF high speed control bus PU/PD DIO DVDDIO

din TE

35 PAD_WF_HB5 WF high speed control bus PU/PD DIO DVDDIO

26 PAD_WF_HB4 WF high speed control bus PU/PD DIO DVDDIO

25 PAD_WF_HB3 WF high speed control bus PU/PD DIO DVDDIO

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24 PAD_WF_HB2 WF high speed control bus PU/PD DIO DVDDIO

23 PAD_WF_HB1 WF high speed control bus PU/PD DIO DVDDIO

34 PAD_WF_HB0_B WF high speed control bus PU/PD DIO DVDDIO

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33 PAD_WF_HB0 WF high speed control bus PU/PD DIO DVDDIO

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Chip enable from companion DVDDIO

16 PAD_PMU_POR_B_V18 PU/PD DI
modem

FEM IOs

83 ANTSEL_5 FEM control PU/PD DIO DVDDIO

84 ANTSEL_6 FEM control PU/PD DIO DVDDIO

85 ANTSEL_7 FEM control PU/PD DIO DVDDIO

86 ANTSEL_8 FEM control PU/PD DIO DVDDIO

87 ANTSEL_9 FEM control PU/PD DIO DVDDIO

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88 ANTSEL_10 FEM control PU/PD DIO DVDDIO
DIO

N
89 ANTSEL_11 FEM control PU/PD DVDDIO

90 ANTSEL_12 FEM control PU/PD DIO DVDDIO

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91 ANTSEL_13 FEM control PU/PD DIO DVDDIO

92 ANTSEL_14 FEM control PU/PD DIO DVDDIO

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93 ANTSEL_15 FEM control PU/PD DIO DVDDIO

128 ANTSEL_4 FEM control PU/PD DIO DVDDIO

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129 ANTSEL_3 FEM control PU/PD DIO DVDDIO

130 ANTSEL_2 FEM control PU/PD DIO DVDDIO

sz. EN
131 ANTSEL_1 FEM control PU/PD DIO DVDDIO

132 ANTSEL_0 FEM control PU/PD DIO DVDDIO

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F
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Table 2-2 MT7976DAN common pin descriptions

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3 Electrical Characteristics

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Absolute maximum rating

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Symbol Parameters Maximum rating Unit

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VDD33 3.3V Supply Voltage -0.3 to 3.6 V
VDD18 1.8V Supply Voltage -0.3 to 1.89 V
TSTG Storage Temperature -40 to +125 °C

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VESD ESD protection (HBM) 2000 V
VESD ESD protection (CDM) +/- 250 V

sz. EN
Table 3-1 Absolute maximum rating

Recommended operating range

Symbol
VDD33
VDD18
tw ID
F Rating
3.3V Supply Voltage
1.8V Supply voltage
MIN
3
1.71
TYP
3.3
1.8
MAX
3.6
1.89
Unit
V
V
Industry junction operating
TJUNCTION -20 25 125 °C
temperature
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TAMBIENT Ambient Temperature -10 - 70 °C
Table 3-2 Recommended operating range
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Power Supply Specifications

The following tables list the power supply requirements for VDD18 and VDD33.
din TE

Table 3-3. AVDD18 specifications

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Test item Min. Typ. Max. Unit Notes

Output voltage, VDD 1.71 1.8 1.89 V
Output current mA
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Table 3-4. AVDD33 specifications

Test Item Min Typ Max Unit Notes
Output voltage 3.0 3.3 3.6 V
Output current mA
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Digital Logic Characteristics

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MT7976DAN’s timing characteristics and interface protocols are shown here, including some
general comments.

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3.4.1 Timing Diagram Convention
Figure 3-1 shows the conventions used with timing diagram throughout this document.

co T
Waveform Description

sz. EN
Signal is changing from low to high

Signal is changing from high to low

tw ID
F X Don’t care or bus is driven

Bus is changing from invalid to valid

g@ N
Bus is changing from high-Z to valid
on O

Denotes multiple clock periods

gy K C

Figure 3-1. Timing diagram conventions

3.4.2 Rising/Falling Time Definition

din TE

Figure 3-2 is the rising and falling timing diagram. The actual signal timing curve is related to the external load
conditions. See 錯誤! 找不到參照來源。 for the operating conditions of digital logics.
ng IA

Specified switch low points

(active terminated load)

Actual switch low point

VDDIO
VOH = 85%
jia D

VOL = 15%
0V
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Specified switch low points Actual switch high point

(active terminated load)

Figure 3-2. Rising and falling times diagram

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Table 3-5. Operating conditions of digital logics

N
Parameter Min. Typ. Max. Unit Notes
VDDIO, supply of IO Power 3 3.3 3.6 V

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VIH, input logic high voltage 0.7*VDD VDD+0.5 V

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VIL, input logic low voltage 0.3*VDDIO V

VOH (DC), DC output high voltage 0.7*VDD VDD+0.5 V VDD=min, IOH=1.5mA

VOL (DC), DC output low voltage 0.3*VDD V VDD=min, IOL=1.5mA

co T
sz. EN
3.4.3 Protocols
There are three main interfaces for MT7976DAN:
 2-wire top control interface: Generally used for all systems (Wi-Fi)

tw ID
12-wire bus: High-speed interface, for Wi-Fi
F
3.4.3.1 2-Wire
g@ N
The 2-wire bus of MT7976DAN is mainly used as below:
 Top control interface, the main interface to access Wi-Fi/TOP command registers
on O

The bit number of SDATA depends on different operating conditions, as shown in Figure 3-3.
gy K C

SCLK

SDATA
din TE

25/33/49-bit data

Figure 3-3. 2-wire SPI timing diagram

ng IA

3.4.3.2 9-bit Bus

MT7976DAN has a dedicated 9-bit bus to control the Wi-Fi radio. The related control definitions depend on
jia D

operating modes and conditions. The protocol is shown in Figure 3-4.

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WRI[0]

WRI[8:1]
6-bit ~ 22-bit data

Figure 3-4. Wi-Fi 9-wire SPI access

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MT7976DAN TOP Building Blocks

N
3.5.1 Thermal ADC

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A low-speed ADC converts the output of thermal sensor. The temperature coverage range is between -40°C
and 120°C. The chip top control may do corresponding adjustment based on such temperature information.

m IA
Wi-Fi

co T
MT7976DAN Wi-Fi is a high performance and highly-integrated dual-band RF transceiver fully compliant with

sz. EN
IEEE 802.11 a/ac/ax/b/g/n standards. MT7976DAN features a self-calibration scheme to compensate the
process and temperature variation to maintain high performance. The calibration is performed automatically
right after the system boot-up.

3.6.1
tw ID
2.4GHz Wi-Fi Tx
F
The 2.4GHz transmitter integrates a PA Driver with on-chip balun. The data are digitally modulated in the
g@ N

baseband processor from the companion chip, then up-converted to 2.4GHz RF channels through the DA
on O

converter, filter, IQ up-converter and PA Driver.

gy K C

3.6.2 2.4GHz Wi-Fi Rx

The 2.4GHz Wi-Fi Rx consists of a high linearity, low noise figure single-ended LNA, a quadrature passive mixer
and a bandwidth-programmable low-pass filter with DC offset cancellation embedded.
din TE

3.6.3 2.4GHz Wi-Fi Sx

A fractional-N frequency synthesizer is implemented to support Wi-Fi LO signal. The frequency synthesizer is
ng IA

capable of supporting various crystal clock frequencies. VCO operates at different freq from RF frequency to
avoid any coupling with RF front-end circuitry. An LO generation is employed to divide the VCO signal and
generate I/Q quadrature signals.
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3.6.4 5/6GHz Wi-Fi Tx

The 5/6GHz transmitter integrates a high performance PA Driver with on-chip balun. The data are digitally
modulated in the baseband processor from the companion baseband chip, then up-converted to 5/6GHz RF
channels through the DA converter, low-pass filter, IQ up-converter and PA Driver
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3.6.5 5/6GHz Wi-Fi Rx

N
The 5/6GHz Wi-Fi Rx consists of a high linearity, low noise figure single-ended LNA, a quadrature passive mixer
and a bandwidth-programmable low-pass filter with DC offset cancellation embedded.

EO
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m IA
3.6.6 5/6GHz Wi-Fi Sx
A-band Sx adopts LO architecture while VCO frequency is different from RF frequency to avoid TX pulling.
Thus, it is composed of PLL, offset LO mixer and a repeater.

co T
sz. EN
tw ID
F
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4 XO and Bootstrap

N
XTAL oscillator

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The table below lists the requirement for the XTAL.

m IA
Item Spec.

Nominal Frequency 40MHz

co T
Size 3.2mmx2.5mm

sz. EN
Operating Temperature Range -40°C to +105°C

Frequency Tolerance (FL) +/- 7 ppm @ 25°C +/- 3°C

Temperature
tw ID
Frequency Stability over Operating

Equivalent Series Resistance (ESR)

F +/- 15 ppm (referred to the value at 25°C) -40°C to +100°C
+/- 20 ppm (referred to the value at 25°C) 100°C to +105°C

15 Ω max.

Drive Level(DL) 400uW max

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Shunt Capacitance (Co) 3.0 pF max

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Load Capacitance (CL) 10 pF

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Trim Sensitivity Over Load(Ts) 10~13 ppm/pF

Table 4-1 XTAL oscillator requirement

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5 Mechanical Information

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Device Physical Dimension/Part Number

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MT7976DAN uses DRQFN package. The physical dimension is shown in Figure 5-1.

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Figure 5-1. Physical dimension of MT7976DAN

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MEDIATEK
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MT7976DAN MT7976DAN: Part

DDDD-XXXXX name
XXXXXXXX DDDD : Date code
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XXXX : Lot number

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Bottom View
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F
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Figure 5-2. Physical dimension of MT7976DAN

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Ordering Information

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Order No. Marking Temperature range Package
MT7976DAN MT7976DAN -10°C ~ 70°C DRQFN

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F ESD CAUTION

MT7976DAN is ESD (electrostatic discharge) sensitive device and may be damaged with ESD or spike voltage.
Although MT7976DAN is with built-in ESD protection circuitry, please handle with care to avoid the permanent
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malfunction or the performance degradation.
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