@shraddha_pawankar Date:25/04/2024

 Assertions are primarily used to validate the behavior of a design.

 As a verification engineer,our primary responsibility is to verify the design and detect
the functional bugs in the design..
 Assertions are used to check design rules or specifications and generate warnings or
errors in case of assertion failures.
 An assertion also provides function coverage that makes sure a certain design
specification is covered in the verification.
 The methodology that uses assertions is commonly known as “Assertion Based
Verification” (ABV).
 Assertions can be written in the design as well as the verification environment.

Advantages of System Verilog Assertion over Verilog assertion :

1) In SV,source code is very compact.No need to write too many lines of codes.
2) No need to write own $display() statement.In case of verilog checker we have to write
$display() statement.
In SV,whenever assertion failed it will automatically print an error message,no need to
write own $display statement.
3) In Verilog,we cant have separate RTL and checker.But in SV ,we can separate them.

4) Checks design specifications and reports errors or warnings in case of failure.

5) It improves debugging time. For example, a bug due to an illegal state transition can
propagate to the output.
6) Writing an assertion helps out to improve debugging time.
7) Can be used in formal verification.
8) Can be re-used across verification testbench or design.
9) Can be parameterized
Can be turned on/off based on the requirement.
Assertion will have white box.
Improving observability,we can easily observe inside the design.

Action Blocks :
 The system verilog language has been developed in such a way that,every time an
assertions check fails,the simulator is expected to print out an error message by
default.
 A user can also print custom error or success message using the “action block” in the
assert statement.
The syntax:
assert property(ppt)
<success message>
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else
<fail_message>

Controllability and Observability :

 Controllability : it is measurement of the ability to activate,stimulate or sensitize a
specific point within the design.

 Observability: it is the measurement of the ability to observe the effects of a

specific,internal,stimulate point within the design.

Assertions improves both observability and controllability so that we can trace the cause of
the bug very quickly.

What are assertions?

 Assertions are the properties,that must be true.
 Gives white box visibility to a black box design.
 During simulations,assertions monitor whether : A specific condition occurs or
specific sequence of event occurs.
 Assertions produce warning or errors when: A specified condition fails,or A specified
sequence does not complete properly.

Why should we adopt Assertions?

 We can detect the bugs sooner.
 We can debug quickly because of white box visibility.
 We can get significant amount of coverage very quickly because we can use ‘Cover
Property’ to cross check whether a particular condition is exercised or not.
 //Assertions
assert property (@(posedge clk) $rose(start) |-> start[*4:$]);

 //cover
cover property (@(posedge clk) $rose(start) |-> start[*4:$]);

 Reusability for future designs by developing parameterized assertions.

Types of Assertions :
1) Immediate Assertions
2) Deferred Immediate assertions
3) Concurrent assertions

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Immediate Assertions:
Defined in a procedural block
 Immediate assertions check for a condition at the current simulation time.
 An immediate assertion is the same as an if..else statement with assertion control.
 These are evaluated immediately.
 Used only with dynamic simulation.
 Unexpected multiple executions(because of glitches in signals)

Examples:
always_comb
begin
a_ia : assert (a && b);
end

The above assertion will be checking for the values a & b if there is an event in either a or b.
The assertion will be failes if a & b are not high at the same time.

Limitations of Immediate Assertions:

 Instantaneous Boolean Check.
 Extra code required around assertion for complex or Non-temporal checks.
 Substential extra code required to check even a simple protocol.
 Requires as much debugging as design.
 Poor readability as design intent is not obvious.

Deferred Immediate Assertions:

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 Can be defined inside and outside of a procedural block.
 Are a type of Immediate Assertions
 Introduced in IEEE 1800-2009 versions of SV.
 Better than immediate assertions and avoids multiple execution of assertions in the
same time slot.
 Can be defined with ‘#0’ of the keyword ‘final’
 Unexpected multiple executions(glitches) in Immediate assertions to avoid this we can
use Deffered Immediate assertions.

Concurrent assertion:
 Can be defined in a procedural block or a module or an interface or a program block.
 Based on clock cycles
 Test expression is evaluated at clock edges based on the sampled values of the variables
involved.
 Sampling of variables is done in the preponed region and
 Evaluation of expression is done in the observed region of the scheduler.
 Can be used with both static(formal) and dynamic verification(simulation) tools.
 The keyword that differentiates the immediate assertion from the concurrent assertion
is “ Property”.
Ex:

c_assert: assert property(@(posedge clk) not(a && b));

The above assertion will be checking for the values of a & b,if there is a posedge in the clk.

The assertion will be failed if a and b are high at the same times

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Building blocks of SVA :

Boolean Expression:
 The functionality is represented by the combination of multiple logical events. These
events could be simple Boolean expressions.

Ex:

c_assert: assert property(@(posedge clk) not(a && b));

The above assertion will be checking for the values of a & b,if there is a posedge in the clk.

The assertion will be failed if a and b are high at the same times.

Sequence :
 In any design model,the functionality is represented by the combination of multiple
logical events.
 These events could be simple Boolean expression that get evaluated on the same clock
edge or could be events that evaluate over a period of time involving multiple clock
cycles.
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 SVA provides a key word to represent these events called “sequence”.
The syntax:

sequence <name_of_sequence>;

……

endsequence

Property :
 A number of sequences can be combined logically or sequentially to create more
complex sequences.
 SVA provides a keyword to represent these complex sequential behaviors called
“property”.
The syntax:

property name_of_property;

< test expression>or

<complex sequence expressions>

endproperty

Assert:
 The property is the one that is verified during a simulation. It has to be asserted to take
effect during a simulation.
 SVA provides a keyword called “assert” to check the property.
The Syntax:

assertion_ name: assert_property( property_name );

SVA Sequence :
 Boolean expression events that evaluate over a period of time involving single/multiple
clock cycles.
 SVA provides a keyword to represent these events called “sequence”.

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SVA Sequence Example :

sequence seq;

@(posedge clk) a==1;

endsequence

 In above example a==1 means a is high on every positive edge of the clock.
 If the signal is not high on any positive clock edge,the assertion will fail.

Code :

module asertion_ex;

bit clk,a;

always #5 clk = ~clk; //clock generation

//generating 'a'

initial begin

a=1;

#10 a=0;

#15 a=1;

#15 a=0;

#15 a=1;

#10;

$finish;

end

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@shraddha_pawankar Date:25/04/2024
//assertion sequence

sequence seq_1;

@(posedge clk) a==1;

endsequence

//calling assert property

a_1: assert property(seq_1);

//wave dump

initial begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule

Eda Playground link: https://www.edaplayground.com/x/3mv6

Waveform:

A sequence with a logical relationship :

Ex:
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@shraddha_pawankar Date:25/04/2024
sequence seq;
@(posedge clk) a || b;
endsequence

From the above example

1) Logical OR operator is used
2) Above sequence, seq checks that on every positive edge of the clock, either signal “a” or
signal “b” is high.
3) If both the signals are low, the assertion will fail.

Code :

module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0;b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

sequence seq;
@(posedge clk) a||b;
endsequence

a_1:assert property(seq);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/Miyh

Sequence with arguments:

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By defining formal arguments in a sequence definition,the same sequence can be reused

on other signals of a design that have similar behaviour.

Sequence seq(a,b);
a && b;
endsequence

The generic sequence seq can be re-used on any two signals as shown below.

sequence sig_34
seq(sig_3,sig_4);
endsequence

sequence sig_12;
seq(sig_1,sig_2);
endsequence

These kind of sequences can be used in one hot state machine checks,parity checks etc.
Since these kind of checks are common in most of the designs.

Sequences with Timing Relationship

 So far,we have seen simple checks that will be evaluated foe each clock cycle.
 But in most of scenarios,we may have to check the events that takes several clock
cycles to complete.
 In SVA,clock cycle delays are represented by “##” sign.
 For example,##3 means 3 clock cycles.

The basic syntax of a sequence is as follows.

sequence <name_of_the_sequence>
<var_1 ##n var_2>;
endsequence

Example:

sequence seq;
@(posedge clk) a ##2 b;
endsequence

From above it is clear that

1) “ a” being high on a positive edge of the clock.
2) If the signal “a” is not high,then the sequence fails.
3) If signal “a” is high on any given posedge of the clock,the signal “b” should be high 2
clock cycles after that.
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4) If signal “b” is not asserted after 2 clock cycles,the assertion fails.

Code:
module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0;b=0;
#10 a=1; b=1;
#10;
$finish;
end

sequence seq;
@(posedge clk) a ##2 b;
endsequence

assert property(seq);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/sj6m

Waveform:

Note:: sequence begins when signal “a” is high on a positive edge of the clock.

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Clock usage in SVA :

 The clock can be specified for properties in several ways.

Rules: The clock for an assertion is determined based on the priority mentioned below.
 Priority 1: Use the explicitly mentioned clock for the assertion.
 Priority 2: Infer clock from code context where it is used.
 Priority 3: Use default specified clock.
Note: It is mandatory to mention the clock in case of concurrent assertion. If a clock is
not used, statements are considered to be illegal.

A sequence or a property does not do anything by itself in a simulation

They have to be asserted to take effect as shown below.

Example : Clock defined in the sequence

sequence seq;
@(posedge clk) a ##2 b;
endsequence

Property ppt;
Seq;
Endproperty

A1: assert property(ppt);

Example: Clock defined in the property

Sequence seq;
a ##2 b;
endsequence

property ppt;
@(posedge clk) seq; //best way as we can reuse sequences with other clocks as well.
endproperty
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A1:assert property(ppt);

 In general, it is a good idea to define the clocks in property definitions and keep the
sequences independent of the clocks.
 This will help increase the re-use of the basic sequence definitions.

Example : clock defined in assert statement

sequence seq;
a ##2 b;
endsequence

a1: assert property (@(posedge clk) seq);

This the best way as we can reuse sequences with other clocks as well.

Example: Clock defined in assert statement when we define sequence and property
separately.

sequence seq;
a ## 2 b;
endsequence

property ppt;
seq;
endproperty

a1: assert property (@(posedge clk) ppt);

Default clocking :
 Painful to specify clock operator for every assertions
 Default clocking block applies to every assertion in the same steps without a
specific clock.
 Only 1 default clock per scope allowed.

Infer clock from clocking block:

clocking cb @(posedge clk);

property p;
a ##2 b;
endproperty
endclocking
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assert property(cb.p);

Infer clock from procedural block

property p;
a ##2 b;
endproperty

always @(posedge clk) assert property (p);

Implication operator:

Why we used Implication Operator ??

Example:

sequence seq;
@(posedge clk) a ##2 b;
endsequence

From the above sequence, We can observe that

1) Sequence starts on every positive edge of the clock .
2) It looks for “a” to be high on every positive edge clock edge.
3) If the signal “a” is not high on any given positive clock edge,an error issued by the
checker.
If we want the sequence to be checked only after “a” is high, this can be achieved by
using the implication operator.

The implication construct can be used only with property definitions.It cannot be used in
sequences.
Syntax
sequence_exp |-> property_exp
sequence_exp |=> property_exp
The LHS operand sequence_exp is called an antecedent
The RHS operand property_exp is called a consequent

Types of Implication:
1) Overlapped Implication
2) Non-overlapped Implication

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Overlapped Implication:
 The overlapped implication operator is denoted by the |-> symbol.
 The evaluation of the consequent starts immediately on the same clock cycle if the
antecedent holds true.
 The consequent is not evaluated if the antecedent is not true.
 Also called as same cycle implication.
 The antecedent is the gating condition.
 The antecedent succeeds then the consequent is evaluated.
 If the antecedent does not succeed,then the property is assumed to succeed by
default.This is called a “Vacuous success”.
 Implication is equivalent to an if-then structure.

Code:

module tb;

bit clk,a,b;

always #5 clk = ~clk;

initial begin

a=1; b=1;

#15 a=0; b=0;

#10 a=1; b=0;

#10 a=0; b=0;

#10 a=1; b=1;

#10;

$finish;

end

property p;

@(posedge clk) a|->b;

endproperty

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a1: assert property(p);

initial begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule

Eda playground link: https://www.edaplayground.com/x/XWNd

Non- Overlapped Implication :

 The non-overlapped implication operator is denoted by the |=> symbol.
 The evaluation of the consequent starts in the next clock cycle if the antecedent holds
true.
 The consequent is not evaluated if the antecedent is not true.
 Also called as next cycle implication.
 If there is a match on the antecedent, then the consequent expression is evaluated in
the next clock cycle.
Example:
property p;
@(posedge clk) a |=> b;
endproperty
A1: assert property(p);

From the above property checks that,

1) If signal “a” is high on a given positive clock edge ,then signal “b” should be high on the
next clock edge.

Code:
module tb;
bit clk,a,b;

always #5 clk = ~clk;

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initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) a |=> b;
endproperty

A1: assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

Eda playground link: https://www.edaplayground.com/x/n9UV

Implication with a fixed delay on the consequent:

Example :
property p;
@(posedge clk) a |-> ##2;
endproperty
a1: assert property(p);

From the above property checks that,if signal “a” is high on a given positive clock edge,then
signal “b” should be high after 2 clock cycles.

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Code:
module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;

property p;
@(posedge clk) a |-> ##2 b;
endproperty

a1: assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/fBRv

Timing Windows in SVA checkers:

Example:
property p;
@(posedge clk) a |-> ##[1:4] b;
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endproperty

A1: assert property(p);

Above property checks that,if signal “a” is high on given positive clock edge,then within 1 yo 4
clock cycles,the signal “b” should be high.

Code :
module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1;b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) a |-> ##[1:4] b;
endproperty

A1: assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

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Eda playground link: https://www.edaplayground.com/x/KjQ2

Overlapping Timing Window:

Example :
property p;
@(posedge clk) a |-> ##[0:4] b;
endproperty

a1: assert property(p);

From the above property checks that, if signal “a” is high on a given positive clock edge,then
signal “b” should be high in the same clock cycle or within 4 clock cycles.

Code:
module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;

#15 a=0; b=0;

#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) a|-> ##[0:4] b;
endproperty

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A1:assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/edeX

Indefinite timing window :

 The upper limit of the timing window specified in the right hand side can be defined
with a “$” sign which implies that there is no upper bound for timing.
 This is called the “eventuality” operator.
 The checker will checking for a match until the end of the simulation.

Example:
property p;
@(posedge clk) a |-> ##[1:5] b;
endproperty
a1: assert property(p);

From above property checks that,if signal “a” is high on a given positive clock edge,then signal
“b” will be high eventually starting from the next clock cycle.

Code:
module tb;
bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1;b=0;
#10 a=0; b=0;
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#10 a=1;b=1;
#10;
$finish;
end

property p;
@(posedge clk) a |-> ##[1:$] b;
endproperty

a1: assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/8T8M

Operators in Assertions:
Clock delays:
 ## : represents cycle delay
 2. ##n – represents “n” clock cycles
 3. ##0 – represents same clock cycle
 4. ## [min:max] represents a range of clock cycles. Where min and max must be 0 or
greater than 0.

Example 1:
sequence seq;
@(posedge clk) a ##[2:6] b;
endsequence

The sequence will be matched if a is true when within clock cycle delay of range 2 to 6,b should
be high.

Example 2:
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sequence seq;
@(posedge clk) a ## [2:$] b;
endsequence

The sequence will be matched if a is true then b can be high at any time before simulation
ends.

Repetition Operator:
 If the sequence of events happens repeatedly for n times and it is represented as [*n]
 Where “n”>0
 “n” can not be $.

Example:
sequence seq;
@(posedge clk) req1 ##1 req2[*3];
endsequence

 In this example,if req1 is true then after 1 clock cycle,req2 must be true for 3
consecutive clock cycles.
 Req1 ##1 req[*3] = req1 ##1 req2 ##1 req2 ##1 req2.

Waveform:

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Example 2:
sequence seq;
@(posedge clk) req1 ##1 req2[*2:4];
endsequence

 The repetition operator can also be used in a certain range using [*m:n]
 Where “m” and “n” >0.
 And n cannot be $.

In this example,if req1 is true then after 1 clock cycle,req2 must be true for a minimum of 2
and maximum of 4 consecutive clock cycles.

Non Consecutive repetitive operator:

Example :
sequence seq;
@(posedge clk) req1 ## req2[=4];
endsequence
 If sequence event repetition has to be detected for n non-consecutive clock cycles
then[=n] can be used.
 where n>0
 n cannot be $

In the above example,once req1 holds true after one clock cycle req2 must be true for 4 clock
cycles but it is not mandatory to consecutive clock cycles.

The non-consecutive repetitive operator with a range

Example :
sequence seq;
@(posedge clk) req1 ##1 req2[=2:4];
endsequence

 The non-consecutive can be mentioned in a range as [=m:n].

 Where minimum “m” and maximum “n” non-consecutive repetition.

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In above example,once req1 holds true after one clock cycle ,req2 must be true for a minimum
of 2 and a maximum of 4 clock cycles but it is not mandatory to be consecutive clock cycles.

SVA Methods:
Sequence with edge Detection:
 SVA also has built-in edge detection mechanism that allows the user monitor the
transition of signal value from one clock cycle to the next.
 The system functions available for detecting edges are
$rose
$fell
$stable

$rose :
 This returns true if LSB of signal/expression is changed to 1 and remains 1 in the current
evaluation point.
 The system task $rose is used to detect a positive edge of the given signal.

Syntax:
$rose(Boolean expression or signal name);

Example:
sequence s1;
@(posedge clk) $rose(a);
endsequence

 $rose of a indicates that a posedge of a is expected to be seen on every posedge of clk

 Sequence seq checks that the signal “a” transitions to a value of 1 on every positive
edge of the clock.
 If the transition does not occur, the assertion will fail.

Code:

module tb;

bit a;

bit clk;

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always #5 clk=~clk;

initial begin

a=1;

#15 a=1;

#10 a=1;

#10 a=1;

#10 a=1;

#10 a=1;

#15 a=0;

#10 a=1;

#10;

$finish;

end

sequence seq;

@(posedge clk) $rose(a);

endsequence

assert property(seq);

initial begin

$dumpfile("dump.vcd");
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$dumpvars;

end

endmodule

Eda playground link: https://www.edaplayground.com/x/DGz2

Waveform:

$fell :
 This returns true if LSB of signal/expression is changed to 0 and remains 0 in the current
evaluation time.
 The system task $fell is used to detect negative edge of the given signal.

Syntax:
$fell(Boolean expression or signal name)
Returns true if the LSB of the expression changed to 0.otherwise,it returns false

Example:
sequence seq;
@(posedge clk) $fell(a);
endsequence

 $fell of a indicates that a negedge of a is expected to be seen on every posedge of clk.

 Sequence seq checks that the signal “a” transitions to a value of 0 on every positive edge
of the clock.
 If the transition does not occur,the assertion will fail.
Code:
module tb;
bit a;
bit clk;

always #5 clk=~clk;

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initial begin
a=1;
#15 a=1;
#10 a=1;
#10 a=1;
#10 a=1;
#10 a=1;
#15 a=0;
#10 a=1;
#10;
$finish;
end

sequence seq;
@(posedge clk) $fell(a);
endsequence

assert property(seq);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/FVB_

Waveform:

$stable:
 This returns true if the value of the expression did not change in the current evaluation
point and previous evaluation point.

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Syntax:
$stable(Boolean expression or signal name)
Returns true if the value of the expression did not change.otherwise,it returns false.

Example:
sequence seq;
@(posedge clk) $stable(a);
endsequence

 Sequence seq checks that the signal “a” is stable on every positive edge of the clock.
 If there is any transition occurs,the assertion will fail.

Code:
module tb;
bit a;
bit clk;

always #5 clk=~clk;

initial begin
a=1;
#15 a=1;
#10 a=1;
#10 a=1;
#10 a=1;
#10 a=1;
#15 a=0;
#10 a=1;
#10;
$finish;
end

sequence seq;

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@(posedge clk) $stable(a);
endsequence

assert property(seq);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/qUjz

Waveform:

$past
It is capable of getting values of signals from previous clock cycles.

Syntax:
$past(signal_name,number of clock cycles)
Provides the value of the signal from the previous clock cycle.

Example:
property p;
@(posedge clk) b |-> ($past(a,2) == 1);
endproperty
A1: assert property(p);

Below property checks that,in the given positive clock edge,if the “b” is high,then 2 cycles
before that,a was high.

Code:
module tb;

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bit clk,a,b;

always #5 clk = ~clk;

initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) b |-> ($past(a,2) == 1);
endproperty

A1: assert property(p);

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/hX_x

$past construct with clock gating

 The $past construct can be used with a gating signal.
 On a given clock edge,the gating signal has to be true even before checking for the
consequent condition.

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Syntax:
$past(signal_name,number of clock cycles,gating signal)

Example:
property p;
@(posedge clk) b|->($past(a,2,c) == 1);
endproperty
a1:assert property(p);
Above the property checks that,in the given positive clock edge,if the “b” is high,then 2 cycles
before that, a was high only if the gating signal “c” is valid on any given positive edge of the
clock.

Code:
module tb;
bit clk,a,b,c;

always #5 clk = ~clk; //clock generation

//generating 'a'
initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) b |-> ($past(a,2,c) == 1);
endproperty

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a_1: assert property(p);

//wave dump
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Eda playground link: https://www.edaplayground.com/x/bdX9

Built-in system functions:

$countones:
Count the number of bits that are high in a vector.

Syntax:
$countones(expression)

Example:
sequence seq;
@(posedge clk) $countones(a);
endsequence

 Returns the number of 1’s in A.

 Any value other than 1 gets ignored.

$isunknown:
Checks if any bit of the expression is X or Z.

Syntax:
$isunknown(expression)

Example:
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sequence seq;
@(posedge clk) $isunknown(a);
endsequence

 Checks whether the vector has a bit with value ‘X’ or ‘Z’.
 Returns a Boolean true if any bit in the argument passed is X or Z.

$onehot:
Returns 1 if only one bit is high in an expression.
Syntax:
$onehot(expression);

$onehot0:
Returns 1 if all the bits are zero or only one bit is 1 in an expression.
Syntax:
$onehot0(expression);

Disable iff:
If certain design condition,we don’t want to proceed with the check if some condition is
true,this can be achieved by using disable iff.
Disables the checker if certain condition is met.

Example:
property p;
@(posedge clk)
disable iff(rst) a |-> ##1 b[->3] ##1 c;
endproperty
a1:assert property(p);

Above the property states that,

1) If the signal “a” is high on given posedge of the clock,
2) The signal “b” should be high for 3 clock cycles followed by “c”.
3) “C” should be high after “b” is high for the third time.
4) During this entire sequence,if reset is detected high at any point,the checker will stop.

Code:

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module tb;
bit clk,a,b,c,reset;

always #5 clk = ~clk; //clock generation

//generating 'a'
initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
@(posedge clk) disable iff (reset) a |-> ##1 b[->3] ##1 c;
endproperty

a: assert property(p);

//wave dump
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

EDA playground link: https://www.edaplayground.com/x/Jj9s

Sequence Composition:

There are some binary operators,that can be used to combine two sequences logically.
a) And
b) Or
c) Intersect
d) Throughout
e) Within
f) First_match

The ‘AND’ construct:

Both the sequences must have same starting point,but they can have different
ending points.
Final property succeeds when both the sequences succeed.
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Syntax:
<seq_exp> and <seq_exp>;

The requirements for AND operation match:

1) Starting Together: Both sequences must start at the same time.
2) Waiting for Match: If one sequence matches, it waits for the other to match.
3) End Time: The end time of the combined sequence is determined by the sequence
that finishes last.

Example for AND of two sequences

(a1 ##1 a2) and (a3 ##1 a4 ##2 a5)

Note:
The two operand sequences need not be matched at the same number of clock ticks.

The ‘Or’ construct

Final property succeds when any one of the sequence succeds.

Syntax:
<seq_exp> or <seq_exp>
The requirement for ‘or’ operation match:
1. Starting Together: Both sequences must start at the same time.
2. At Least One Match: The combined sequence matches if either of the two sequences
(seq1 or seq2) matches.
3. End Time: The end time of the combined sequence is determined by the sequence that
finishes last.

Example for OR of two sequences

(a1 ##1 a2) or (a3 ##1 a4 ##2 a5)

The ‘intersect’ construct:

Both the sequences must have same starting point and ending point.
Final property succeds when any one of the sequence succeeds.

Syntax:

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<seq_exp> intersect <seq_exp>

The requirement for intersect operation match

1. Same Length Requirement: Both sequences must have the same length.
2. Both Sequences Must Match: Both sequences need to match. If one matches, it waits
for the other to match as well.
3. End Time: The end time of the combined sequence is determined by when both
operand sequences finish.

The ‘throughout’ construct:

Property succeeds,when the expression holds true throughout the evaluation of
the entire sequence.

Example:
sequence seq;
@(posedge clk) $rose(en) ##0
(en) throughout (##2 (req && valid)) [*5];
endsequence

From the Above example,

 The sequence seq starts on the rising edge of the clock
 When en rises,then continues with ‘en’ being true.
 The ‘throughput’ part specifies that during evey 2-clock cycles interval where ‘req’
and ‘valid’ are true( req && valid)
 ‘en’ must remain true for all clock ticks within that interval.
 Essentially,it’s ensuring that ‘en’ stays true whenever ‘req’ and ‘valid’ are true
within every 2-clock cycle interval,and it repeats this check for 5 such interval.

The ‘within’ construct:

The within operator is used to check if one sequence is completely contained
within another sequence.
It verifies if one sequence matches within the duration where another sequence is
also matching.
1. Containment Check: It ensures that one sequence occurs entirely within another
sequence.
2. Start and End Point Comparison: It checks if the starting point of the contained
sequence is after or at the same time as the starting point of the containing sequence,
and if the ending point of the contained sequence is before or at the same time as the
ending point of the containing sequence.

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Syntax:
Seq1 within seq2;

The ‘first match’ construct:

The first_match operator matches only for the first match out of all possible
multiple matches.

Syntax:
first_match(<seq_exp>)

Here's how it works:

1. Earliest Match Selection: It selects the first occurrence of the sequence expression that
matches.
2. Evaluation Timing: The evaluation of the sequence expression happens at the same
clock cycle when the first_match operator is evaluated.
3. No Match: If the sequence expression doesn't produce any match, first_match also
doesn't produce a match.

Example:
sequence seq;
first_match(req1 ## [1:4] req2);
endsequence
This sequence seq looks for the earliest occurrence of req1 followed by req2 within a range
of 1 to 4 clock cycles..

Connecting assertion to a design

SVA checkers can be connected to design by different methods.
1) Embed or in-line assertion in the module definition(In-line).
2) Bind the assertion to a module or an instance/multiple instances of a module(binding

Inline :
Assertions can be embedded anywhere in a module definition.
Sometimes unnecessary change in the design in required..

Code:
module tb;
bit clk,a,b,c,reset;

always #5 clk = ~clk; //clock generation

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//generating 'a'
initial begin
a=1; b=1;
#15 a=0; b=0;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=1; b=1;
#10;
$finish;
end

property p;
//------
endproperty

A: assert property(p); // The assertion written inside the design unit.

//wave dump
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

Binding:
In SystemVerilog, the bind directive is used to associate or bind assertions written
in separate testbench files with specific modules or interfaces in the design code.
This allows verification engineers to write assertions independently from the
design code, enhancing modularity and flexibility in the verification process.
By defining assertions separately,re-usability can be increased.
The assertion can be bound to any module or instance in the design.

When using the bind directive, assertions can be bound to:

1. Specific Instances: You can bind assertions to a particular instance of a module or
interface within the design hierarchy. This allows for targeted assertion verification at
specific points in the design.
2. All Instances: Alternatively, you can bind assertions to all instances of a module or
interface present in the design.
This approach ensures that the assertions apply uniformly across all instances,
providing comprehensive verification coverage.

How binding works:

1) Separate assertion files:

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Assertions are typically written in separate files within the testbench
environment,independent of the design code.
2) Bind directive:
Using the ‘bind’ directive,you specify the association between assertion files and the
design modules or interfaces.
3) Flexibility :
This approach provides flexibility, as verification engineers can modify and update
assertions without altering the design code.it also allows for easy reuse of assertions
across different test scenarios.
4) Modularity:
By separating assertions from the design code and binding them as needed,the
verification environment becomes more modular and maintainable,facilitating
efficient verification processes.
Overall,the ‘bind’ directive in system verilog enables seamless integration of
assertions with the design code,promoting better organization,flexibility and
scalability in the verification methodology.

Syntax:
To bind with specific instance
Bind <dut_specific_instance_path><assertion_module><instance>

To bind with all instances:

Bind <dut_module><assertion_module><instance>

Design Unit:
module dut(input logic clk,req,output logic ack);
//dut logic
endmodule

Assertion Module:
module asser_mod(input clk,a,b);

property p1;
@(posedge clk) $rose(a) |=>b;
endproperty

a1:assert property(p1);
endmodule

The top module that binds DUT and Assertion together

module top;

//instantiate design modules

dut d1(clk,req1,ack1);

bind dut asser_mod p1(clk,req,ack);

endmodule
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