Digital System Engineering

Module 4 Timing Conventions

by
Dr. S. D. Ruikar
2015-16
 Syllabus
Module 4 Timing Conventions
• Conventional Synchronous system and closed
loop pipelined system, considerations in
timing design, Timing fundamentals, Timing
properties of combinational logic and clock
storage elements, Eye diagram, Encoding
Timing (Signals and Events), Open loop
synchronous timing, Closed loop timing, Phase
locked loops, Clock Distribution
 Module 5 Synchronization
• Synchronization Fundamentals, Applications
of synchronization (Arbitration of
asynchronous signals, Sampling asynchronous
signals, Crossing clock domains),
Synchronization failure and meta-stability,
Synchronizer Design (Mesochronous,
Plesiochronous, Periodic Asynchronous)
 Module 6 Power Distribution
• The power supply network (Local loads, Signal
loads), Local Regulation, Logic loads and on-
chip power supply distribution (Logic current
profile, IR drops, Area Bonding, On-chip by-
pass capacitor), Power supply isolation
(Supply-supply isolation, Signal-supply
isolation), Bypass capacitors, Power
Distribution System
Timing
 Signals, values, and events
• Signals, values, and events
– at an instant in time a signal holds a value
– over time, a signal carries events (time-value pairs)
– there are many ways of encoding events
Encoding events
Clock Domain
 Clock domains
• Mesochronous
– same frequency but different phases
• Plesiochronous
– slightly different frequencies
• Periodic
– clearly different frequencies, but the phase difference is
periodic
• Asynchronous
– clearly different frequenciens without a periodic phase
difference
Delay and Rise/Fall Times
 Overview
• Timing components
– delay elements
– combinational logic
– clocked-storage elements
• Timing uncertainty
– Skew
• Spatial variations in equivalent clock edges
• Mostly deterministic
– Jitter
• Temporal variations in consecutive clock edges
• Mostly random
• Synchronous Timing
– all signals in one domain
– narrow windows of allowed operating frequency
• Pipeline Timing
– clock forwarded with signal
– operates across wide range of frequencies
 Jitter
• Jitter is movement of signal edges from their ideal position in time. This
movement can lead or lag the ideal positions, and, as system speeds
increase, these edge deviations present a significant problem for system
signal integrity, causing skew, race conditions, and other timing problems.
• Jitter is generally classified into three types: cycle-to-cycle jitter, period
jitter, and phase jitter.
• The diagrams in Figure illustrate these types.
 Jitter
• Cycle-to-cycle jitter is the change in an output’s transition in time in
relation to the transition during the previous cycle.
• Period jitter is the maximum change in a signal transition from the ideal
position in time.
• Phase jitter, also called long-term jitter, in the maximum change in an
output signal transition from its ideal position over many cycles (typically
10 to 20 microseconds).
• The causes of jitter are grouped into two general categories: deterministic
jitter and random jitter.
• Deterministic jitter is caused by power supply fluctuations, cross-talk, and
duty cycle distortion (e.g., asymmetric rising and falling edges).
• Random jitter is caused primarily by device thermal noise.
• Although system designers have little control over the causes of random
jitter, they can reduce the effects of deterministic jitter by minimizing
cross-talk and duty cycle distortion and by ensuring the power network is
adequate for system needs.
 Skew
• Skew is the variation of propagation delay differences between output signals.
Minimizing output skew is a key design criterion in today’s high-speed clocked
systems. Excessive skew, especially for clock signals, can cause race conditions and
other timing errors that result in system data faults. At the very least, poor skew
will force a slower maximum system speed, and this, in turn, will limit system
performance.
• Matching trace lengths, trace impedances, and line loading will minimize system
skew. Clock driving and I/O technology will also play a significant role in overall
system skew.
• Fairchild Semiconductor has developed skew specifications for interface devices.
This section provides an overview of skew types, their definitions, and examples,
as shown in Figure . Without skew specifications, a designer must approximate
timing uncertainties. Skew specifications have been created to help clock designers
define output propagation delay differences within a given device and duty cycle.
Skewed edges
Timing Building Blocks
 Fundamental concepts
• Timing convention governs when a transmitter drivers symbols onto
to signal line and when they are sampled by the receiver. This can
be periodic or a periodic. Symbol arriving time need to be encoded.
In case of periodic convention, changing symbols can provide
information for receiver timing alignment. For aperiodic case,
explicit transition is required to signal the arrival of the new symbol.
• The rate of signaling across line or logic module is limited by the
rise time transmitter and transmission media, the sampling window
(aperture) of the receiver, and the timing noise (uncertainty). Thus
only jitter is a constraint instead of skew. The rise time of the
transmitter defines how best a new symbol can be put on a line.
The signal need to be stable during the sampling window of the
receiver. The minimum bit cell defined above is furthermore
widened by the timing noise such that worst case timing plus a
marginal can be met.
• Optimum timing for sampling is defined at the center of the
received eye diagram (least BER).
 Fundamental concepts
• In global clock based system all signals are synchronized. All signals
change in response to clock and are sampled at aperture time
corresponding the clock transitions. This defines a clock domain.
• Because aperture time is associated to clock changes, non-optimal
sampling can occur in large systems where the clock and signal
skews can cause non optimal detection.
• If signal lines or logic modules have a delay larger than a clock
period, system will operate only over narrow windows of clock
frequencies. The maximum clock frequency is defined thus by the
maximum delay.

Operating rate is limited by 3 factors

– transition (rise) time
– aperture time
– timing uncertainty, skew and jitter
Signal and eye diagram
 Sources of timing uncertainty
• Skew
– between clock line and data line
– fixed differences in flip-flop, transmitter, and receiver delays
– in transmit clock between flip-flops
– aperture offset in receive flip flop
– offset in 90 degree delay line
• Jitter
– in transmit clock
– in delay of flip-flops, transmitters, and receivers
A comparison of two timing
convention
A conventional Synchronous System
Closed loop pipeline timing
Skew and Jitter Analysis
Fig: Nominal timing system
 Consideration in timing Design
• Degree of synchronization
• Periodicity
• Encoding of events
• Open versus closed loop events
Timing elements
 Clock domain
• In a system, those signals whose events are timed using
one specific clock define a clock domain
• Signals within a clock domain can be combined and
sampled by the common clock
• A large system can contain several distinct clock domains
• Interface between two different clock domains must be
carefully designed
– implementation depends on the relationship between the
clocks of the two domains
• Mesochronous
– same frequency but different phases
• Plesiochronous
– slightly different frequencies
• Periodic
– clearly different frequencies, but the phase difference is periodic
• Asynchronous
– clearly different frequenciens without a periodic phase difference
– synchronizer circuit is probably needed at the interface
 Timing fundamentals
• Timing Nomenclature
– Delay and Transition times
– Periodic Signals
– Maximum Absolute value, peak to peak and RMS
 Timing fundamentals
• Timing Nomenclature
– Delay and Transition times

Fig: Rise time, Fall time, pulse width and delay

Pulse width of the signal =
• twhA (twlA ) = high (low) pulse width of A
from a rising (falling) transition to the next falling (rising) transition using 50 % points
• tdAB delay between transitions on the signals A and B from 50 % to 50 %
• trB (tfB ) = rise (fall ) time of B – from 10 % to 90 % (90 % to 10 %)
 Timing
fundamentals
• Timing Nomenclature
– Periodic Signals
Transition Period Fig: Measurement of periodic signals
from a rising (falling) transition to the next rising (falling)
transition using 50 % points
Transition frequency=frequency of A = 1/ tcyA =

Duty factor of periodic signal=

Delay in relative phase

Slow drift phase

 Timing fundamentals
• Timing Nomenclature
– Maximum Absolute value, peak to peak and RMS
 Timing fundamentals
• Timing properties of Delay Elements
– For purpose of timing analysis, we model transmission lines, buffers and delay
lines as delay elements.
– Delay to be composed of three components: nominal delay, the average
variation or skew and the AC variation or jitter
 Timing Uncertainty — Skew and Jitter
• Consider two periodic signals A and B with the same period
• Skew tAB is the delay between corresponding transitions on A and B
– we say that A and B are synchronized signals with the skew tAB
• Jitter tjA of a periodic signal A is the difference between the
expected transition time and the actual transition time
• Timing uncertainty tu,AB between A and B is the sum of the
maximum skew and the maximum jitter

Note that here tAB,max, tjA,max, and tjB,max

are maximum absolute values. This
means that the actual boundaries of the
timing noise are ±tu,AB , and hence the
peak-to-peak value is 2tu,AB
 Timing Uncertainty — Skew and Jitter
• Consider a delay element with the input A and
the output Y
– delay line, transmission line, buffer
• Actual delay tdAY of the element consists of the
nominal delay tnAY, skew tkAY and jitter tjAY
– skew is the average variation in the delay
– jitter is the AC variation in the delay
• Timing uncertainty tuAY of the delay is the sum of
the maximum skew and the maximum jitter

• Minimum and maximum delays of the element

are given as max , max

• Minimum and maximum delays define the early

and late waveforms at the
 Timing Building Blocks
• Delay elements (delay lines, transmission lines,
buffers)
– nominal delay, skew & jitter
• Combinational logic
– contamination delay tc is the minimum time from an
input change to the first output change
– propagation delay td is the maximum time from an
input change to the last output change
• Clocked storage elements (flip-flops & latches)
– setup time ts is the minimum required time from an
input change to the active clock edge
– hold time th is the minimum required time from the
active clock edge to an input change
– aperture time ta is the minimum time the input must
remain stable to be correctly sampled:
ta = ts + th – tr
– aperture offset time tao is the time from the aperture
center to the active clock edge
tao = (ts – th)/2
– Contamination and propagation delays tcCQ and tdCQ
from the clock edge to the output Q
 Timing Properties of Combinational Logic
• propagation delay td is the maximum time from an input
change to the last output change
 It is the maximum over all input states, s
 It is the delay to the last transition caused by an input transition
or equivalently , it is the maximum delay over all active paths in
the circuits
 It is the maximum over process, temperature and voltage
variations
• contamination delay tc is the minimum time from an
input change to the first output change

Fig: Propagation and contamination delays of combinational logic

 Timing Properties of Combinational Logic
• Composition of contamination delay and propagation delay
• Periods when the signal is stable with a known value are denoted
by two parallel lines.
• The two lines cross over to denote a potential transition and a
shaded region is used to indicate that the signal is either unstable
or in an unknown state.
• When combinational logic circuits are composed in series, the
propagation delay of the composite circuit is the sum of the delays
of the individual elements.

Fig: Abstract view and composition of combinational logic delays

 Timing properties of Clocked Storage Elements
• Synchronous sequential logic circuits are composed of
combinational logic circuits and clocked storage elements shown in
fig
Fig: A sequential logic
circuit

• On each rising edge of the clock, the flip-flops sample their input
and update their output with the new value, advancing the state
vector to become the next state vactor.

1. Edge triggered flip flop

2. Level Sensitive Latch
3. Double Edge Triggered Flip flop
Edge-Triggered Flip-Flop
• Conceptually simplest clocked storage
element
•Samples data on rising edge of clock
•data must remain valid during an
aperture time during sampling
•Output is held steady until next clock
•output is steady until a contamination
delay after clock
•output has correct value a propagation
delay after clock

Contamination
 Other Clocked Storage Elements
• Level-sensitive latch
– passes data when enable (clock) is high
– holds data when enable (clock) is low

Fig: An edge triggered flip flop realized

using latches
 Other Clocked Storage Elements
• Dual-edge-triggered flip-flop
– samples data on both edges of the clock
– allows the clock and data to run at the same
frequency
– can be built from two level-sensitive latches and
a multiplexer
 The eye Diagram
• An eye diagram provides a visual indication of the voltage
and timing uncertainty associated with a signal.
• It is easy to generate by synchronizing an oscilloscope.
• Operating rate is limited by 3 factors
– transition (rise) time
– aperture time
– timing uncertainty, skew and jitter
Timing Budget and Maximum Operation Rate
 Encoding Timing: Signals and Events
• Signal has a value at a given instant in time
– ‘0’ or ‘1’ for a binary signal
• Signal has a sequence of events during some
time period
– for example: 01111111001…
– each event is a pair consisting of a value and time
at which the value is assigned to the signal
• (‘0’, 0 ns), (‘1’, 2 ns), (‘1’, 4 ns)..
– hence, an event is a potential transition
• every event does not have to change the signal value !
 Encoding Timing: Signals and Events
• Signaling events can be encoded in several ways
onto a signal line
– periodic encodings define a fixed known delay
between events
• for example 1 or more clock cycles
– aperiodic encodings have a variable delay between
events. If the delay is unknown, each event must be
explicitly defined by a transition
• on the signal itself
• on an auxiliary communication signal (“data valid”).
• Either return-to-zero (RZ) or not-return to-zero
(NRZ) signaling can be used.
Encoding Events
 Open-Loop Synchronous Timing
• Consider a link using synchronous timing
 Open-Loop Synchronous Timing
• Timing convention is open-loop, if the delays or phase
differences between the signals are uncontrolled
– system is designed to tolerate a certain amount of skew and
jitter
• In a synchronous timing convention, all signals are
synchronized with a common clock
• Sources of uncertainty
– skew & jitter of line delays (tdAB)
– jitter of transmitter and receiver delays
– skew & jitter of the global clock
• often quite large, because the fanout of the clock is usually very high
• To maximize performance and reliability, the sampling edge
of the clock must occur in the middle of a bit cell at the
receiver, i.e, the aperture or sampling window must be
centered on the eye diagram
– this means that the line delay should be an odd multiple of the
half clock cycle !!
The problem with Synchronous Timing
• At high speeds and long lines it only operates
over very narrow ranges of clock frequency
– impractical to control delays and frequencies to
precision required
– unable to switch frequency of operation
• can’t margin test system
Global Clock, Edge – Triggered Timing
Delay Constraints in Synchronous Edge-Triggered Timing
Where,
ts,th=flip-flop setup & hold time
tk= clock skew, or the difference
between the earliest and latest clock
(=peak to peak )
tcXX, tdXX = contamination & propagation
delay
Delay Constraints in Synchronous Two-Phase Timing
TWO Phase non overlapping clocks
Synchronous Single-Phase or Zero Nonoverlap Timing
Synchronous Single-Phase or Zero
Nonoverlap Timing
 Pipeline timing
• Delay the clock by the same amount as the data
plus half a bit cell
• System will work from DC to maximum frequency
1/(tr+ta+tu)
• Defines a new clock domain at the far end of the
line
 Open-Loop Pipeline Timing
• Timing of a clocked pipeline can be optimized using the pipeline
timing convention
• Clock of a pipeline stage is a delayed version of the clock used by
the previous stage
• Delay element is usually selected in such a way that the sampling
clock edge at the receiver is centered on the eye diagram of the
received data C :
• tdel = tdCQ + tnBC+ tcy / 2
– delay of the transmitting flip-flop and the combinational logic block CL
plus half a bit period
– transmission lines carrying data and the clock are here considered
identical
Pipeline Timing
Open-Loop Pipeline Timing contd..
• Minimum cycle time constraint:
• tcy,min = tuAC+ tudel + ta + trC
– uncertainty of the path A C and the delay element
(peak-to-peak values), aperture of the receiving flip-flop,
and the rise time of the received data C
– not limited by the absolute delay of the stage!!
• System works from an arbitrarily low frequency upto
the maximum frequency
• fmax = 1/ tcy,min
• Note that dual-edge-triggered flip-flops are used in the
implementation shown above
– new bit is sent with every clock transition
Level Sensitive Pipeline Timing
 Pipeline Timing
• Each stage in a pipeline-timed system is its own clock
domain
• This is not a problem as long as data propagates in one
direction
• Often, however, it is necessary to feed back information
from a late stage to an early stage
• In order to have a reliable and robust feedback, a
synchronizer is needed
– synchronizer retimes data from a clock domain to another
 Pipeline Timing
• Pipeline timing is widely used on communication channels
between chips and circuit boards, where several bits may
be in flight along a single wire at the same time
– delay matching is not that difficult for transmission lines
• Pipeline timing is rarely used for on-chip Logic
– delay of a logic circuit may depend on the input state
• logic circuits operating in parallel can have totally different
delays
– hence, it is difficult to match delays keeping timing uncertainty
low
• On-chip pipelined timing with several bits in flight through
logic is called wave pipelining
Strict two-phase clocking
 Closed-Loop vs Open-Loop Timing
• In open-loop timing, the delays or phase differences between the
signals are uncontrolled
– sources of uncertainty (skew & jitter) are minimized in the design
process
– system is designed to tolerate a certain amount of uncertainty
• In closed-loop timing, the delays between the signals are
dynamically measured and canceled (compensated)
– skew (DC part of the timing noise) can be canceled using a control loop
with a variable (adjustable) delay line
• in the clock or data path
– delay element is adjusted to center the clock edge on the eye diagram
• bit is sampled in the middle of the bit cell
– jitter (AC part of the timing noise ) cannot be compensated
 Closed-loop timing: measure and cancel skew

• All skew can be canceled by a variable delay element

– in clock or data path
• Delay line is adjusted to center the clock on the eye
• To adjust the delay, need to measure the timing
– Usually an iterative process, measure-adjust-measure...
Simple Timing Loop
 Timing loop components
• Phase Comparator
– measures the time difference between two signal
transitions
– for periodic signals measures the phase of one signal with
respect to the other
– the sensor for most timing loops
• Delay Lines
– adjust the delay between two points in a system
– the actuator for most timing loops
• except for PLLs that use VCOs
• Loop Filters
– smooth response of the timing loop
– stabilize the loop (for PLLs)
 Delay- and Phase-Locked Loops

Delay Locked loop DLL Phase locked loop PLL

Phase-locked loop generates a local clock
in its voltage-controlled oscillator (VCO)
and aligns this clock with a reference data
or clock signal D

If an appropriate low-jitter refe-rence

clock signal is available, a DLL
configuration should be used, because
it has lower phase noise and is easier
to control than PLL
 Variable Delay Lines
• Variable delay line is usually a simple chain of inverters
with a possibility to control the propagation delay
• Methods to vary delay
– multiplexing inverter chains of different lengths
• “tapped” delay line
• digital method
 Variable Delay Lines
• Variable delay line is usually a simple chain of inverters with a
possibility to control the propagation delay
• Methods to vary delay
– multiplexing inverter chains of different lengths
• “tapped” delay line
• digital method
– varying the power supply to an inverter chain
• “current-starved” inverters
• analog method
 Variable Delay Lines
• Variable delay line is usually a simple chain of inverters with a possibility
to control the propagation delay
• Methods to vary delay
– multiplexing inverter chains of different lengths
• “tapped” delay line
• digital method
– varying the power supply to an inverter chain
• “current-starved” inverters
• analog method
– varying the capacitance driven by the inverters in a chain
• analog method
 Variable Delay Lines
• Variable delay line is usually a simple chain of inverters with a
possibility to control the propagation delay
• Methods to vary delay
– multiplexing inverter chains of different lengths
• “tapped” delay line
• digital method
– varying the power supply to an inverter chain
• “current-starved” inverters
• analog method
– varying the capacitance driven by the inverters in a chain
• analog method
• Characterized by
– maximum and minimum delay
– stability (jitter)
Ideal Phase Comparator
Ideal Phase Comparator
Flip-Flop Phase Comparator
Dual-Edge Flip-Flop Phase Comparator
Exclusive OR (XOR) Phase Comparator
Sequential Phase Comparators
Bundled Closed-Loop Timing

TX
RX
Per-Line Closed-Loop Timing
 Per-Line Closed-Loop Timing

multiphase
Clock Distribution Problem
Off-Chip Clock Distribution Tree
Round-Trip Distribution
On-Chip Clock Distribution Tree
Reducing On-Chip Clock Jitter
• Thank You