ESP32-S2-MINI-1

ESP32-S2-MINI-1U
Datasheet

NS D
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RN DE EN
2.4 GHz Wi-Fi (802.11 b/g/n) module
Built around ESP32-S2 series of SoC, Xtensa® single-core 32-bit LX7 microprocessor
4 MB flash and optional 2 MB PSRAM in chip package
M
37 GPIOs, rich set of peripherals
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On-board PCB antenna or external antenna connector

NE O
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FO T R

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ESP32-S2-MINI-1 ESP32-S2-MINI-1U

Version 1.4
Espressif Systems
Copyright © 2024

www.espressif.com
1 Module Overview

1 Module Overview
Note:

Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/documentation/esp32-s2-mini-1_esp32-s2-mini-1u_datasheet_en.
pdf

1.1 Features

CPU and On-Chip Memory Note:

* Please refer to ESP32-S2 Series Datasheet for
• ESP32-S2FH4 or ESP32-S2FN4R2 embedded, detailed information about the module peripher-
Xtensa® single-core 32-bit LX7 microprocessor, als.
up to 240 MHz

• 128 KB ROM Integrated Components on Module

• 320 KB SRAM • 40 MHz crystal oscillator

• 16 KB SRAM in RTC
Antenna Options
• 4 MB embedded flash
• On-board PCB antenna (ESP32-S2-MINI-1)
• 2 MB embedded PSRAM (ESP32-S2FN4R2
• External antenna via a connector
only)
(ESP32-S2-MINI-1U)

Wi-Fi Operating Conditions

• 802.11 b/g/n • Operating voltage/Power supply: 3.0 ~ 3.6 V
• Bit rate: 802.11n up to 150 Mbps • Operating ambient temperature:

• A-MPDU and A-MSDU aggregation – 85 °C version: –40 ~ 85 °C

• 0.4 µs guard interval support – 105 °C version: –40 ~ 105 °C

• Operating frequency: 2412 ~ 2484 MHz

Certification

• RF certification: See certificates

Peripherals
• Green certification: RoHS/REACH
• GPIO, SPI, LCD, UART, I2C, I2S, Camera
interface, IR, pulse counter, LED PWM, TWAI®
(compatible with ISO 11898-1, i.e. CAN Test
Specification 2.0), full-speed USB OTG, ADC,
• HTOL/HTSL/uHAST/TCT/ESD
DAC, touch sensor, temperature sensor

1.2 Description
ESP32-S2-MINI-1 and ESP32-S2-MINI-1U are two powerful, generic Wi-Fi MCU modules that have a rich set of
peripherals. They are an ideal choice for a wide variety of application scenarios related to Internet of Things
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1 Module Overview

(IoT), such as wearable electronics and smart home.

ESP32-S2-MINI-1 comes with a PCB antenna (ANT). ESP32-S2-MINI-1U comes with an external antenna
connector (CONN). A wide selection of module variants are available for customers as shown in Table 1 and
Table 2.

Table 1: ESP32-S2-MINI-1 (ANT) Series Comparison1

Chip Chip Ambient Temp.2 Size3

Ordering Code Flash4 PSRAM5
Embedded Revision (°C) (mm)
ESP32-S2-MINI-1-N4 (NRND) — –40 ∼ 85
4 MB ESP32-S2FH4 v0.0
ESP32-S2-MINI-1-H4 (End of life) — –40 ∼ 105 15.4 × 20.0 × 2.4
(Quad SPI)
ESP32-S2-MINI-1-N4R2 (NRND) 2 MB (Quad SPI) ESP32-S2FN4R2 v1.0 –40 ∼ 85
1 This table shares the same notes presented in Table 2 below.

Table 2: ESP32-S2-MINI-1U (CONN) Series Comparison

Chip Chip Ambient Temp.2 Size3

Ordering Code Flash4 PSRAM5
Embedded Revision (°C) (mm)
ESP32-S2-MINI-1U-N4 (NRND) — –40 ∼ 85
4 MB ESP32-S2FH4 v0.0
ESP32-S2-MINI-1U-H4 (End of life) — –40 ∼ 105 15.4 × 15.4 × 2.4
(Quad SPI)
ESP32-S2-MINI-1U-N4R2 (NRND) 2 MB (Quad SPI) ESP32-S2FN4R2 v1.0 –40 ∼ 85
2 Ambient temperature specifies the recommended temperature range of the environment immediately outside the Espressif mod-

ule.
3 For details, refer to Section 7.1 Physical Dimensions.
4 The flash is integrated in the chip’s package.
5 The PSRAM is integrated in the chip’s package.

In this datasheet unless otherwise stated, ESP32-S2-MINI-1 refers to ESP32-S2-MINI-1-N4,

ESP32-S2-MINI-1-H4, and ESP32-S2-MINI-1-N4R2, whereas ESP32-S2-MINI-1U refers to
ESP32-S2-MINI-1U-N4, ESP32-S2-MINI-1U-H4, and ESP32-S2-MINI-1U-N4R2.

The ESP32-S2FH4 chip (chip revision v0.0) and the ESP32-S2FN4R2 (chip revision v1.0) chip at the core of
the two modules fall into the same category, namely ESP32-S2 chip series. ESP32-S2 series of chips have an
Xtensa® 32-bit LX7 CPU that operates at up to 240 MHz. It has a low-power co-processor that can be used
instead of the CPU to save power while performing tasks that do not require much computing power, such as
monitoring of peripherals.

ESP32-S2 series of chips integrate a rich set of peripherals, ranging from SPI, I2S, UART, I2C, LED PWM,
TWAI® , LCD, Camera interface, ADC, DAC, touch sensor, temperature sensor, as well as up to 43 GPIOs. It also
includes a full-speed USB On-The-Go (OTG) interface for USB communication.

For more information on ESP32-S2 series of chips and chip revisions, please refer to

• ESP32-S2 Series Chip Revision v0.0 Datasheet

• ESP32-S2 Series Chip Revision v1.0 Datasheet

• ESP32-S2 Series SoC Errata

• Upgrade Chip Revision of ESP32-S2 Series Products Based on ESP32-S2R2 and ESP32-S2FN4R2

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1 Module Overview

1.3 Applications
• Generic Low-power IoT Sensor Hub • Smart Building

• Generic Low-power IoT Data Loggers • Industrial Automation

• Cameras for Video Streaming
• Smart Agriculture
• Over-the-top (OTT) Devices
• Audio Applications
• USB Devices
• Health Care Applications
• Speech Recognition
• Wi-Fi-enabled Toys
• Image Recognition
• Wearable Electronics
• Mesh Network

• Home Automation • Retail & Catering Applications

• Smart Home Control Panel • Smart POS Machines

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Contents

Contents

1 Module Overview 2
1.1 Features 2
1.2 Description 2
1.3 Applications 4

2 Block Diagram 9

3 Pin Definitions 10
3.1 Pin Layout 10
3.2 Pin Description 10
3.3 Strapping Pins 12
3.4 Strapping Pins 12
3.4.1 Chip Boot Mode Control 13
3.4.2 VDD_SPI Voltage Control 14
3.4.3 ROM Messages Printing Control 14

4 Electrical Characteristics 15
4.1 Absolute Maximum Ratings 15
4.2 Recommended Operating Conditions 15
4.3 DC Characteristics (3.3 V, 25 °C) 15
4.4 Current Consumption Characteristics 16
4.5 Current Consumption in Active Mode 16
4.5.1 Current Consumption in Other Modes 17
4.6 Wi-Fi RF Characteristics 17
4.6.1 Wi-Fi RF Standards 18
4.6.2 Transmitter Characteristics 18
4.6.3 Receiver Characteristics 19

5 Module Schematics 21

6 Peripheral Schematics 23

7 Physical Dimensions and PCB Land Pattern 24

7.1 Physical Dimensions 24
7.2 Recommended PCB Land Pattern 25
7.3 Dimensions of External Antenna Connector 27

8 Product Handling 28
8.1 Storage Conditions 28
8.2 Electrostatic Discharge (ESD) 28
8.3 Soldering Profile 28
8.3.1 Reflow Profile 28
8.4 Ultrasonic Vibration 29
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Contents

9 MAC Addresses and eFuse 30

Related Documentation and Resources 31

Revision History 32

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List of Tables

List of Tables
1 ESP32-S2-MINI-1 (ANT) Series Comparison1 3
2 ESP32-S2-MINI-1U (CONN) Series Comparison 3
3 Pin Definitions 11
4 Default Configuration of Strapping Pins 12
5 Description of Timing Parameters for the Strapping Pins 13
6 Chip Boot Mode Control 14
7 VDD_SPI Voltage Control 14
8 ROM Messages Printing Control 14
9 Absolute Maximum Ratings 15
10 Recommended Operating Conditions 15
11 DC Characteristics (3.3 V, 25 °C) 15
12 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode 16
13 Current Consumption in Modem-sleep Mode 17
14 Current Consumption in Low-Power Modes 17
15 Wi-Fi RF Standards 18
16 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 18
17 TX EVM Test1 18
18 RX Sensitivity 19
19 Maximum RX Level 20
20 Adjacent Channel Rejection 20

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List of Figures

List of Figures
1 ESP32-S2-MINI-1 Block Diagram 9
2 ESP32-S2-MINI-1U Block Diagram 9
3 ESP32-S2-MINI-1 Pin Layout (Top View) 10
4 Visualization of Timing Parameters for the Strapping Pins 13
5 ESP32-S2-MINI-1 Schematics 21
6 ESP32-S2-MINI-1U Schematics 22
7 Peripheral Schematics 23
8 ESP32-S2-MINI-1 Physical Dimensions 24
9 ESP32-S2-MINI-1U Physical Dimensions 24
10 ESP32-S2-MINI-1 Recommended PCB Land Pattern 25
11 ESP32-S2-MINI-1U Recommended PCB Land Pattern 26
12 Dimensions of External Antenna Connector 27
13 Reflow Profile 28

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2 Block Diagram

2 Block Diagram

ESP32-S2-MINI-1
40 MHz ESP32-S2-MINI-1
40 MHz
Crystal
3V3 Crystal Antenna
3V3 Antenna

RF Matching
ESP32-S2FH4 RF Matching
ESP32-S2FN4R2
ESP32-S2FH4
EN GPIOs
ESP32-S2FN4R2
EN FLASH PSRAM(opt.)
GPIOs
(QSPI) (QSPI)
FLASH PSRAM(opt.)
(QSPI) (QSPI)

Figure 1: ESP32-S2-MINI-1 Block Diagram

ESP32-S2-MINI-1U
40 MHz
Crystal ESP32-S2-MINI-1U
3V3 40 MHz Antenna
Crystal
3V3 Antenna

RF Matching
ESP32-S2FH4
RF Matching
ESP32-S2FN4R2
EN ESP32-S2FH4 GPIOs
ESP32-S2FN4R2
FLASH PSRAM(opt.)
EN (QSPI) (QSPI)
GPIOs
FLASH PSRAM(opt.)
(QSPI) (QSPI)

Figure 2: ESP32-S2-MINI-1U Block Diagram

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3 Pin Definitions

3 Pin Definitions

3.1 Pin Layout

The pin diagram below shows the approximate location of pins on the module. For the actual diagram drawn to
scale, please refer to Figure 7.1 Physical Dimensions.

The pin layout is applicable for ESP32-S2-MINI-1 and ESP32-S2-MINI-1U, but the latter has no keepout
zone.

Keepout Zone
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND
Pin 51
Pin 60

Pin 59

Pin 58

Pin 57

Pin 56

Pin 54

Pin 53

Pin 52

Pin 50

Pin 49

Pin 48

Pin 47

Pin 46
Pin 55

Pin 62 Pin 65
GND GND

GND Pin 1 Pin 45 EN

GND Pin 2 Pin 44 IO46

3V3 Pin 3 Pin 43 GND

IO0 Pin 4 Pin 42 GND

IO1 Pin 5 Pin 41 IO45

IO2 Pin 6 GND GND GND Pin 40 RXD0

IO3 Pin 7 Pin 39 TXD0

Pin 61
IO4 Pin 8 GND
GND
GND Pin 38 IO42

IO5 Pin 9 Pin 37 IO41

IO6 Pin 10 GND GND GND Pin 36 IO40

IO7 Pin 11 Pin 35 IO39

IO8 Pin 12 Pin 34 IO38

IO9 Pin 13 Pin 33 IO37

IO10 Pin 14 Pin 32 IO36

IO11 Pin 15 Pin 31 IO35

Pin 21
Pin 16

Pin 17

Pin 18

Pin 19

Pin 20

Pin 22

Pin 23

Pin 24

Pin 26

Pin 27

Pin 28

Pin 29

Pin 30
Pin 25

Pin 63 Pin 64
GND GND
IO21
IO12

GND
IO14

IO20

IO34
IO13

IO16

IO17

IO26

IO33
IO18

IO19
IO15

NC

Figure 3: ESP32-S2-MINI-1 Pin Layout (Top View)

3.2 Pin Description

The module has 65 pins. See pin definitions in Table 3 Pin Definitions.

For peripheral pin configurations, please refer to > Section Peripheral Pin Configurations.

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3 Pin Definitions

Table 3: Pin Definitions

Name No. Type1 Function

1, 2, 30,
GND 42, 43, P Ground
46-65
3V3 3 P Power supply
IO0 4 I/O/T RTC_GPIO0, GPIO0
IO1 5 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
IO2 6 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
IO3 7 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
IO4 8 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
IO5 9 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
IO6 10 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
IO7 11 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
IO8 12 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7
IO9 13 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD
IO10 14 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4
IO11 15 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5
IO12 16 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6
IO13 17 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7
IO14 18 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS
IO15 19 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
IO16 20 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
IO17 21 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1
IO18 2 22 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3
IO19 23 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
IO20 24 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
IO21 25 I/O/T RTC_GPIO21, GPIO21
IO26 3 26 I/O/T SPICS1, GPIO26
NC 27 — NC
IO33 28 I/O/T SPIIO4, GPIO33, FSPIHD
IO34 29 I/O/T SPIIO5, GPIO34, FSPICS0
IO35 31 I/O/T SPIIO6, GPIO35, FSPID
IO36 32 I/O/T SPIIO7, GPIO36, FSPICLK
IO37 33 I/O/T SPIDQS, GPIO37, FSPIQ
IO38 34 I/O/T GPIO38, FSPIWP
IO39 35 I/O/T MTCK, GPIO39, CLK_OUT3
IO40 36 I/O/T MTDO, GPIO40, CLK_OUT2
IO41 37 I/O/T MTDI, GPIO41, CLK_OUT1
IO42 38 I/O/T MTMS, GPIO42
TXD0 39 I/O/T U0TXD, GPIO43, CLK_OUT1
RXD0 40 I/O/T U0RXD, GPIO44, CLK_OUT2
IO45 41 I/O/T GPIO45
Cont’d on next page

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3 Pin Definitions

Table 3 – cont’d from previous page

Name No. Type1 Function
IO46 44 I GPIO46
High: on, enables the chip.
EN 45 I Low: off, the chip powers off.
Note: Do not leave the EN pin floating.
1 P: power supply; I: input; O: output; T: high impedance.
2 For modules with chip revision v0.0 embedded, IO18 on the module is pulled up to VDD33 through
a 10 kΩ resistor. For modules with chip revision v1.0 embedded, the resistor is not populated. For
details, please refer to Chapter 5 Module Schematics.
3 IO26 is used by the embedded PSRAM on the ESP32-S2-MINI-1-N4R2 and ESP32-S2-MINI-1U-N4R2
modules, and cannot be used for other purposes.

3.3 Strapping Pins

Note:
The content below is excerpted from Section Strapping Pins in ESP32-S2 Series Chip Datasheet. For the strapping
pin mapping between the chip and modules, please refer to Chapter 5 Module Schematics.

3.4 Strapping Pins

Note:
The content below is excerpted from ESP32-S2 Series Datasheet > Section Strapping Pins. For the strapping pin
mapping between the chip and modules, please refer to Chapter 5 Module Schematics.

At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to
load the chip, voltage of flash memory, etc. These parameters are passed over via the strapping pins. After
reset, the strapping pins operate as regular IO pins.

The parameters controlled by the given strapping pins at chip reset are as follows:

• Chip boot mode – GPIO0 and GPIO46

• VDD_SPI voltage – GPIO45

• ROM messages printing – GPIO46

GPIO0, GPIO45, and GPIO46 are connected to the chip’s internal weak pull-up/pull-down resistors at chip
reset. These resistors determine the default bit values of the strapping pins. Also, these resistors determine
the bit values if the strapping pins are connected to an external high-impedance circuit.

Table 4: Default Configuration of Strapping Pins

Strapping Pin Default Configuration Bit Value

GPIO0 Pull-up 1
GPIO45 Pull-down 0
GPIO46 Pull-down 0

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3 Pin Definitions

To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If
the ESP32-S2 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by
the host MCU.

All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping
pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in
any other way. It makes the strapping pin values available during the entire chip operation, and the pins are
freed up to be used as regular IO pins after reset.

Regarding the timing requirements for the strapping pins, there are such parameters as setup time and hold
time. For more information, see Table 5 and Figure 4.

Table 5: Description of Timing Parameters for the Strapping Pins

Parameter Description Min (ms)

Setup time is the time reserved for the power rails to stabilize be-
tSU 0
fore the CHIP_PU pin is pulled high to activate the chip.
Hold time is the time reserved for the chip to read the strapping
tH pin values after CHIP_PU is already high and before these pins 3
start operating as regular IO pins.

tSU tH

VIL_nRST
CHIP_PU

VIH

Strapping pin

Figure 4: Visualization of Timing Parameters for the Strapping Pins

3.4.1 Chip Boot Mode Control

GPIO0 and GPIO46 control the boot mode after the reset is released. See Table 6 Chip Boot Mode
Control.

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3 Pin Definitions

Table 6: Chip Boot Mode Control

Boot Mode GPIO0 GPIO46

Default configuration 1 (Pull-up) 0 (Pull-down)
SPI Boot (default) 1 Any value
Download Boot 0 0
Invalid combination 1 0 1
1 This combination triggers unexpected behavior
and should be avoided.

3.4.2 VDD_SPI Voltage Control

Depending on the value of EFUSE_VDD_SPI_FORCE, the voltage can be controlled in two ways.

Table 7: VDD_SPI Voltage Control

EFUSE_VDD_SPI_FORCE GPIO45 eFuse 1 Voltage VDD_SPI power source 2

0 3.3 V VDD3P3_RTC_IO via RSP I
0 Ignored
1 1.8 V Flash Voltage Regulator
0 1.8 V Flash Voltage Regulator
1 Ignored
1 3.3 V VDD3P3_RTC_IO via RSP I
1 eFuse: EFUSE_VDD_SPI_TIEH
2 See ESP32-S2 Series Datasheet > Section Power Scheme

3.4.3 ROM Messages Printing Control

During boot process the messages by the ROM code can be printed to:

• (Default) U0TXD pin. For this, EFUSE_UART_PRINT_CONTROL should be 0.

• DAC_1 pin. For this, EFUSE_UART_PRINT_CONTROL should be 1.

EFUSE_UART_PRINT_CONTROL and GPIO46 control ROM messages printing as shown in Table 8 ROM
Messages Printing Control.

Table 8: ROM Messages Printing Control

eFuse1 GPIO46 ROM Messages Printing

0 Ignored Always enabled
0 Enabled
1
1 Disabled
0 Disabled
2
1 Enabled
3 Ignored Always disabled
1 eFuse: EFUSE_UART_PRINT_CONTROL

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4 Electrical Characteristics

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Stresses above those listed in Table 9 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated under Table 10 Recommended Operating Conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 9: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDD33 Power supply voltage –0.3 3.6 V
TST ORE Storage temperature –40 105 °C

4.2 Recommended Operating Conditions

Table 10: Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VDD33 Power supply voltage 3.0 3.3 3.6 V
IV DD Current delivered by external power supply 0.5 — — A
85 °C version 85
TA Operating ambient temperature –40 — °C
105 °C version 105

4.3 DC Characteristics (3.3 V, 25 °C)

Table 11: DC Characteristics (3.3 V, 25 °C)

Symbol Parameter Min Typ Max Unit

CIN Pin capacitance — 2 — pF
VIH High-level input voltage 0.75 × VDD1 — VDD1 + 0.3 V
VIL Low-level input voltage –0.3 — 0.25 × VDD1 V
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
VOH 2 High-level output voltage 0.8 × VDD1 — — V
VOL 2 Low-level output voltage — — 0.1 × VDD1 V
High-level source current (VDD1 = 3.3 V, VOH
IOH — 40 — mA
>= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1 = 3.3 V, VOL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
RP U Pull-up resistor — 45 — kΩ
RP D Pull-down resistor — 45 — kΩ
VIH_nRST Chip reset release voltage 0.75 × VDD1 — VDD1 + 0.3 V
VIL_nRST Chip reset voltage –0.3 — 0.25 × VDD1 V

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4 Electrical Characteristics

1 VDD is the I/O voltage for pins of a particular power domain.

2 VOH and VOL are measured using high-impedance load.

4.4 Current Consumption Characteristics

Owing to the use of advanced power-management technologies, the module can switch between different
power modes. For details on different power modes, please refer to Section RTC and Low-Power
Management
in ESP32-S2 Series Chip Datasheet.

With continuous upgrades and optimization of the products, ESP32-S2FN4R2 has been upgraded to chip
version v1.0, which has improved the performance compared to the pre-upgrade version. This section lists the
current consumption characteristics of modules with chip revision v1.0 embedded.

4.5 Current Consumption in Active Mode

Table 12: Current Consumption for Wi-Fi (2.4 GHz) in Active Mode

Work Mode RF Condition Description Peak (mA)

802.11b, 1 Mbps, DSSS, @19.0 dBm 328
802.11g, 54 Mbps, OFDM, @17.5 dBm 295
TX
802.11n, HT20, MCS7, @17.0 dBm 276
Active (RF working)
802.11n, HT40, MCS7, @16.0 dBm 254
802.11b/g/n, HT20 75
RX
802.11n, HT40 83

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4 Electrical Characteristics

Note:
The content below is excerpted from Section Power Consumption in Other Modes in ESP32-S2 Series Datasheet.

4.5.1 Current Consumption in Other Modes

The measurements below are applicable to ESP32-S2, ESP32-S2FH2, and ESP32-S2FH4. Since
ESP32-S2FN4R2 and ESP32-S2R2 come with in-package PSRAM, their current consumption might be
higher.

Table 13: Current Consumption in Modem-sleep Mode

Typ
Mode CPU Frequency Description All Peripherals Clocks All Peripherals Clocks
(MHz) Disabled (mA) Enabled (mA)1

CPU is idle 20.0 28.0

240
CPU is running 23.0 32.0
CPU is idle 14.0 21.0
Modem-sleep2,3 160
CPU is running 16.0 24.0
CPU is idle 10.5 18.4
80
CPU is running 12.0 20.0
1 In practice, the current consumption might be different depending on which peripherals are enabled.
2 In Modem-sleep mode, Wi-Fi is clock gated.
3 In Modem-sleep mode, the consumption might be higher when accessing flash. For a flash rated at 80
Mbit/s, in SPI 2-line mode the consumption is 10 mA.

Table 14: Current Consumption in Low-Power Modes

Work mode Description Typ (µA)

Light-sleep1 VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance 750
The ULP co-processor ULP-FSM 170
is powered on2 ULP-RISC-V 190
Deep-sleep ULP sensor-monitored pattern3 22
RTC timer + RTC memory 25
RTC timer only 20
Power off CHIP_PU is set to low level, the chip is powered off 1
1 In Light-sleep mode, with all related SPI pins pulled up, the current consumption of the embedded
PSRAM is 140 µA. Chip variants with in-package PSRAM include ESP32-S2FN4R2 and ESP32-S2R2.
2 During Deep-sleep, when the ULP co-processor is powered on, peripherals such as GPIO and I2C
are able to operate.
3 The “ULP sensor-monitored pattern” refers to the mode where the ULP coprocessor or the sensor
works periodically. When touch sensors work with a duty cycle of 1%, the typical current consump-
tion is 22 µA.

4.6 Wi-Fi RF Characteristics

Not Recommended For New Designs (NRND)
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4 Electrical Characteristics

4.6.1 Wi-Fi RF Standards

ESP32-S2FN4R2 has been upgraded to chip version v1.0, bringing differences in performance data compared
to the pre-upgrade version. This section lists the Wi-Fi RF characteristics of modules with chip revision v1.0
embedded.

Table 15: Wi-Fi RF Standards

Name Description
Center frequency range of operating channel 1 2412 ~ 2484 MHz
Wi-Fi wireless standard IEEE 802.11b/g/n
802.11b: 1, 2, 5.5 and 11 Mbps
20 MHz 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
Data rate
802.11n: MCS0-7, 72.2 Mbps (Max)
40 MHz 802.11n: MCS0-7, 150 Mbps (Max)
Antenna type PCB antenna, external antenna connector
1 Device should operate in the center frequency range allocated by regional regulatory authorities.
The target center frequency range is configurable by software.
2 For the modules that use external antenna connectors, the output impedance is 50 Ω. For other
modules without external antenna connectors, the output impedance is irrelevant.

4.6.2 Transmitter Characteristics

Target TX power is configurable based on device or certification requirements. The default characteristics of
modules with chip revision v1.0 embedded are provided in Table 16.

Table 16: TX Power with Spectral Mask and EVM Meeting 802.11 Standards

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps, DSSS — 19.0 —
802.11b, 11 Mbps, CCK — 19.0 —
802.11g, 6 Mbps, OFDM — 17.5 —
802.11g, 54 Mbps, OFDM — 17.5 —
802.11n, HT20, MCS0 — 17.5 —
802.11n, HT20, MCS7 — 17.0 —
802.11n, HT40, MCS0 — 17.5 —
802.11n, HT40, MCS7 — 16.0 —

Table 17: TX EVM Test1

Min Typ Limit

Rate (dB) (dB) (dB)
802.11b, 1 Mbps, DSSS — –25.0 –10.0
802.11b, 11 Mbps, CCK — –25.0 –10.0
802.11g, 6 Mbps, OFDM — –29.5 –5.0
Cont’d on next page

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4 Electrical Characteristics

Table 17 – cont’d from previous page

Min Typ Limit
Rate (dB) (dB) (dB)
802.11g, 54 Mbps, OFDM — –29.5 –25.0
802.11n, HT20, MCS0 — –28.0 –5.0
802.11n, HT20, MCS7 — –31.0 –27.0
802.11n, HT40, MCS0 — –28.5 –5.0
802.11n, HT40, MCS7 — –30.5 –27.0
1 EVM is measured at the corresponding typical TX power provided
in Table 16 TX Power with Spectral Mask and EVM Meeting 802.11
Standards above.

4.6.3 Receiver Characteristics

Table 18: RX Sensitivity

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps, DSSS — –96.0 —
802.11b, 2 Mbps, DSSS — –93.5 —
802.11b, 5.5 Mbps, CCK — –91.0 —
802.11b, 11 Mbps, CCK — –87.5 —
802.11g, 6 Mbps, OFDM — –91.5 —
802.11g, 9 Mbps, OFDM — –90.0 —
802.11g, 12 Mbps, OFDM — –88.5 —
802.11g, 18 Mbps, OFDM — –86.0 —
802.11g, 24 Mbps, OFDM — –83.5 —
802.11g, 36 Mbps, OFDM — –79.5 —
802.11g, 48 Mbps, OFDM — –75.5 —
802.11g, 54 Mbps, OFDM — –74.0 —
802.11n, HT20, MCS0 — –91.0 —
802.11n, HT20, MCS1 — –88.0 —
802.11n, HT20, MCS2 — –85.5 —
802.11n, HT20, MCS3 — –82.5 —
802.11n, HT20, MCS4 — –78.5 —
802.11n, HT20, MCS5 — –74.5 —
802.11n, HT20, MCS6 — –73.0 —
802.11n, HT20, MCS7 — –71.5 —
802.11n, HT40, MCS0 — –88.0 —
802.11n, HT40, MCS1 — –85.5 —
802.11n, HT40, MCS2 — –83.0 —
802.11n, HT40, MCS3 — –79.0 —
802.11n, HT40, MCS4 — –76.0 —
802.11n, HT40, MCS5 — –71.5 —
Cont’d on next page

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4 Electrical Characteristics

Table 18 – cont’d from previous page

Min Typ Max
Rate (dBm) (dBm) (dBm)
802.11n, HT40, MCS6 — –70.5 —
802.11n, HT40, MCS7 — –69.0 —

Table 19: Maximum RX Level

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps, DSSS — 5 —
802.11b, 11 Mbps, CCK — 5 —
802.11g, 6 Mbps, OFDM — 5 —
802.11g, 54 Mbps, OFDM — 0 —
802.11n, HT20, MCS0 — 5 —
802.11n, HT20, MCS7 — 0 —
802.11n, HT40, MCS0 — 5 —
802.11n, HT40, MCS7 — 0 —

Table 20: Adjacent Channel Rejection

Min Typ Max

Rate (dB) (dB) (dB)
802.11b, 1 Mbps, DSSS — 35 —
802.11b, 11 Mbps, CCK — 35 —
802.11g, 6 Mbps, OFDM — 31 —
802.11g, 54 Mbps, OFDM — 14 —
802.11n, HT20, MCS0 — 31 —
802.11n, HT20, MCS7 — 13 —
802.11n, HT40, MCS0 — 19 —
802.11n, HT40, MCS7 — 8 —

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 Espressif Systems

5 Module Schematics
5 Module Schematics
The schematics in this section apply to modules with chip revision v1.0 embedded.
5 4 3 2 1

GND

VDD33
GND GND
Y1

3
GND

GND XOUT
C3
C1 C4
1uF
D TBD TBD D

XIN
VDD33
GND The values of C1 and C4 vary with

2
the selection of the crystal.
C2
GND The value of R4 varies with the actual
100pF 40MHz(±10ppm) PCB board.
VDD33 CHIP_PU
GND GPIO46
GPIO45
U0RXD
GND
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C5 R3 499 U0TXD
GPIO42

0
0.1uF GPIO41
GPIO40
VDD33 GND GPIO39
GND

R4

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
L1 2.0nH
C C

EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C6 C7 C8 C9 C10 VDD33 62 65

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
GND GND
10uF 1uF 0.1uF 0.1uF 0.1uF VDD33 1 45 CHIP_PU
GND EN

CHIP_PU

VDDA

VDDA
GND

U0RXD
U0TXD
MTMS

MTDO
MTCK
GPIO46

XTAL_P
XTAL_N

GPIO45

MTDI
VDD3P3_CPU
2 44 GPIO46
21

3 GND IO46 43
GND GND GND GND GND GPIO0 4 3V3 GND 42
GPIO1 5 IO0 GND 41 GPIO45
ANT1 50 ohm Impedance Control 1 42 GPIO38 GPIO2 6 IO1 IO45 40 U0RXD
1 RF_ANT L2 TBD LNA_IN 2 VDDA GPIO38 41 GPIO37 GPIO3 7 IO2 RXD0 39 U0TXD
2 3 LNA_IN GPIO37 40 GPIO36 GPIO4 8 IO3 TXD0 38 GPIO42
C11 C12 VDD3P3 GPIO36 IO4 ESP32-S2-MINI-1 IO42
4 39 GPIO35 GPIO5 9 37 GPIO41
TBD GPIO0 5 VDD3P3 GPIO35 38 GPIO34 GPIO6 10 IO5 IO41 36 GPIO40
PCB_ANT TBD
GPIO1 6 GPIO0 GPIO34 37 GPIO33 GPIO7 11 IO6 IO40 35 GPIO39
Not Recommended For New Designs (NRND)

GPIO2 7 GPIO1 GPIO33 36 GPIO8 12 IO7 IO39 34 GPIO38

GPIO3 8 GPIO2 SPID 35 GPIO9 13 IO8 IO38 33 GPIO37
GND GND GND
GPIO4 9 GPIO3 SPIQ 34 GPIO10 14 IO9 IO37 32 GPIO36
GPIO4 SPICLK IO10 IO36
The values of C11, L2 and C12 GPIO5 10
GPIO5 SPICS0
33 GPIO11 15
IO11 IO35
31 GPIO35
GPIO6 11 32
vary with the actual PCB board. GPIO7 12 GPIO6 SPIWP 31 63 64
GPIO7 SPIHD GND GND

GND
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26

IO33
IO34
GPIO8 13 30 VDD33

NC
VDD3P3_RTC_IO
B B
NC: No component. GPIO9 14 GPIO8 VDD_SPI 29 GPIO26
GPIO9 SPICS1
ESP32-S2-MINI-1 & MINI-1U Datasheet v1.4

VDD3P3_RTC

U2
XTAL_32K_N
XTAL_32K_P

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C13 C14 D1
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO19
GPIO20

GPIO21
DAC_1
DAC_2

VDD_SPI ESD

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26

GPIO33
GPIO34
0.1uF 1uF

U1 ESP32-S2FH4 GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28

ESP32-S2FN4R2 GND GND GND

VDD33 VDD33
ESP32-S2-MINI-1(pin-out)
R11 10K(NC)

C15 C16

0.1uF 0.1uF
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

A GND GND A

Figure 5: ESP32-S2-MINI-1 Schematics

5 4 3 2 1
 5 4 3 2 1
Espressif Systems

5 Module Schematics
GND

VDD33
GND GND
Y1

3
GND

GND XOUT
C3
C1 C4
1uF
D TBD TBD D

XIN
VDD33
GND The values of C1 and C4 vary with

2
the selection of the crystal.
C2
GND The value of R4 varies with the actual
100pF 40MHz(±10ppm) PCB board.
VDD33 CHIP_PU GND
GND GPIO46
GPIO45
U0RXD
C5 R3 499 U0TXD
GPIO42

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
0.1uF GPIO41
GPIO40

EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD33 GND GPIO39 62 65
GND GND GND

R4
L1 2.0nH VDD33 1 45 CHIP_PU
C 2 GND EN 44 GPIO46 C
C6 C7 C8 C9 C10 VDD33 3 GND IO46 43

57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
Submit Documentation Feedback

GPIO0 4 3V3 GND 42

10uF 1uF 0.1uF 0.1uF 0.1uF GPIO1 5 IO0 GND 41 GPIO45
IO1 IO45

CHIP_PU

VDDA

VDDA
GND

U0RXD
U0TXD
MTMS

MTDO
MTCK
GPIO46

XTAL_P
XTAL_N

GPIO45

MTDI
VDD3P3_CPU
GPIO2 6 40 U0RXD
GPIO3 7 IO2 RXD0 39 U0TXD
GND GND GND GND GND GPIO4 8 IO3 TXD0 38 GPIO42
IO4 ESP32-S2-MINI-1U IO42
GPIO5 9 37 GPIO41
50 ohm Impedance Control 1 42 GPIO38 GPIO6 10 IO5 IO41 36 GPIO40
1 RF_ANT L2 TBD LNA_IN 2 VDDA GPIO38 41 GPIO37 GPIO7 11 IO6 IO40 35 GPIO39
3 LNA_IN GPIO37 40 GPIO36 GPIO8 12 IO7 IO39 34 GPIO38
ANT1 C11 C12 VDD3P3 GPIO36 IO8 IO38
4 39 GPIO35 GPIO9 13 33 GPIO37
VDD3P3 GPIO35 IO9 IO37
4
3
2

CONN TBD TBD GPIO0 5 38 GPIO34 GPIO10 14 32 GPIO36

22

GPIO1 6 GPIO0 GPIO34 37 GPIO33 GPIO11 15 IO10 IO36 31 GPIO35

GPIO2 7 GPIO1 GPIO33 36 IO11 IO35
GND GPIO3 8 GPIO2 SPID 35 63 64
GND GND
GPIO3 SPIQ GND GND

GND
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26

IO33
IO34
GPIO4 9 34 VDD33

NC
GPIO4 SPICLK
The values of C11, L2 and C12 GPIO5 10
GPIO5 SPICS0
33
GPIO6 11 32 U2
vary with the actual PCB board. GPIO6 SPIWP

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GPIO7 12 31
GPIO8 13 GPIO7 SPIHD 30 D1

VDD3P3_RTC_IO
B B
NC: No component. GPIO9 14 GPIO8 VDD_SPI 29 GPIO26
Not Recommended For New Designs (NRND)

GPIO9 SPICS1 ESD

VDD3P3_RTC

XTAL_32K_N
XTAL_32K_P

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26

GPIO33
GPIO34
C13 C14 GND
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO19
GPIO20

GPIO21
DAC_1
DAC_2
VDD_SPI GND
0.1uF 1uF
ESP32-S2-MINI-1U(pin-out)
U1 ESP32-S2FH4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ESP32-S2FN4R2 GND GND
ESP32-S2-MINI-1 & MINI-1U Datasheet v1.4

VDD33 R11 10K(NC) VDD33

C15 C16

0.1uF 0.1uF
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

GPIO21

A GND GND A

Figure 6: ESP32-S2-MINI-1U Schematics

5 4 3 2 1
6 Peripheral Schematics

6 Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example,
power supply, antenna, reset button, JTAG interface, and UART interface).

GND

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
EPAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
62 65
GND GND
VDD33 1 45 EN C2 TBD GND
2 GND EN 44 IO46
3 GND IO46 43 VDD33
IO0 4 3V3 GND 42 JP1
C1 C3 IO1 5 IO0 GND 41 IO45 R1 TBD 1
IO2 6 IO1 IO45 40 RXD0 2 1
22uF 0.1uF IO3 7 IO2 RXD0 39 TXD0 3 2
IO4 8 IO3 TXD0 38 IO42 4 3
IO4 ESP32-S2-MINI-1/ESP32-S2-MINI-1U IO42 4
GND GND IO5 9 37 IO41
IO6 10 IO5 IO41 36 IO40 UART
JP4 IO7 11 IO6 IO40 35 IO39 GND
1 IO8 12 IO7 IO39 34 IO38 JP2
1 2 IO9 13 IO8 IO38 33 IO37 TMS 1
2 IO10 14 IO9 IO37 32 IO36 TDI 2 1
Boot Option IO11 15 IO10 IO36 31 IO35 TDO 3 2
IO11 IO35 TCK 4 3
GND 63 64 4
GND
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26

IO33
IO34

GND GND JTAG

NC

U1 SW1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

R7 0 EN

C8 0.1uF
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO26

IO33
IO34

GND C4 12pF(NC) GND GND

R2

JP3
1

X1 R3 0(NC) R6 0 USB_D+ 2
32.768kHz(NC) R5 0(NC) R4 0 USB_D- 1 2
1
2

NC

X1: ESR = Max. 70 KΩ C6 C5 USB OTG

GND
C7 12pF(NC) NC: No component. TBD TBD

GNDGND

Figure 7: Peripheral Schematics

• Soldering the EPAD to the ground of the base board is not a must, however, it can optimize thermal
performance. If you choose to solder it, please apply the correct amount of soldering paste. Too much
soldering paste may increase the gap between the module and the baseboard. As a result, the adhesion
between other pins and the baseboard may be poor.

• To ensure that the power supply to the ESP32-S2 chip is stable during power-up, it is advised to add an
4 at the EN pin. The recommended setting3for the RC delay circuit is usually R = 10 kΩ
RC delay circuit 2 and
C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the module
and the power-up and reset sequence timing of the chip. For ESP32-S2’s power-up and reset sequence
timing diagram, please refer to ESP32-S2 Series Datasheet > Section Power Scheme.

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7 Physical Dimensions and PCB Land Pattern

7 Physical Dimensions and PCB Land Pattern

7.1 Physical Dimensions

Unit: mm

15.4±0.2 0.8
4.5

60 x 0.4 x 0.8 4 x 0.8 x 0.8

0.6
14 1.2
20±0.2

13.55

11.9
1.7
14

0.6
5
0.
Ø

4.5

0.85
0.5

4.5

7.7
1.2
0.7 2.4±0.15 1.7
11.9
14
Top view Side view Bottom view

Figure 8: ESP32-S2-MINI-1 Physical Dimensions

Unit: mm

15.4±0.2 0.8
0.85 60 x 0.4 x 0.8 4 x 0.8 x 0.8

0.6
1.2
3.2
15.4±0.2
1.6

13.55

11.9
1.7
14

0.6

14 4.5
0.85
0.5

4.5

7.7
1.2

0.7 2.4±0.15 1.7

11.9
14
Top view Side view Bottom view

Figure 9: ESP32-S2-MINI-1U Physical Dimensions

Note:
For information about tape, reel, and product marking, please refer to Espressif Module Packaging Information.

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7 Physical Dimensions and PCB Land Pattern

7.2 Recommended PCB Land Pattern

This section provides the following resources for your reference:

• Figures for recommended PCB land patterns with all the dimensions needed for PCB design. See Figure
10 ESP32-S2-MINI-1 Recommended PCB Land Pattern and Figure 11 ESP32-S2-MINI-1U Recommended
PCB Land Pattern.

• Source files of recommended PCB land patterns to measure dimensions not covered in Figure 10 and
Figure 11. You can view the source files for ESP32-S2-MINI-1 and ESP32-S2-MINI-1U with Autodesk
Viewer.

• 3D models of ESP32-S2-MINI-1 and ESP32-S2-MINI-1U. Please make sure that you download the 3D
model file in .STEP format (beware that some browsers might add .txt).

Unit: mm
Via for thermal pad
Pad
15.4

Pin 1
60 x 0.4 x 0.8 Antenna Area 4 x 0.8 x 0.8
4.5

1.2
0.6
11.9
1.7

20
14

1.2

4.5
0.85
4.5

7.7
0.6

1.7
11.9
14

Figure 10: ESP32-S2-MINI-1 Recommended PCB Land Pattern

Not Recommended For New Designs (NRND)

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7 Physical Dimensions and PCB Land Pattern

Unit: mm
Via for thermal pad
Pad

Pin 1 15.4
60 x 0.4 x 0.8 4 x 0.8 x 0.8

1.2
0.6
11.9

15.4
1.7
14

1.2
4.5

0.85
4.5
0.6

7.7
1.7
11.9
14

Figure 11: ESP32-S2-MINI-1U Recommended PCB Land Pattern

Not Recommended For New Designs (NRND)

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7 Physical Dimensions and PCB Land Pattern

7.3 Dimensions of External Antenna Connector

ESP32-S2-MINI-1U uses the third generation external antenna connector as shown in Figure 12 Dimensions of
External Antenna Connector. This connector is compatible with the following connectors:

• W.FL Series connector from Hirose

• MHF III connector from I-PEX

• AMMC connector from Amphenol

Unit: mm
Tolerance: +/-0.1 mm

CONTACT
A

2.00±0.10
1.7

A
GROUND CONTACT
2.05±0.10
1.7
0.57

0.85

CONTACT
1.40

0.10

HOUSING
HOUSING MATERIAL: THERMOPLASTIC, WHITE, UL 94V-0;
SHELL

CONTACT MATERIAL: COPPER ALLOY, GOLD PLATED ALL OVER;

SECTION: A-A
SCALE: 1:1
SHELL MATERIAL: COPPER ALLOY, GOLD PLATED ALL OVER;

PERFORMANCE:

CONTACT RESISTANCE: 20mOHM Max.

DIELECTRIC WITHSTANDING VOLTAGE: 200V AC FOR 1MINUTE;

INSULATION RESISTANCE: 500MOHM Min.

Figure 12: Dimensions of External Antenna Connector

Not Recommended For New Designs (NRND)

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8 Product Handling

8 Product Handling

8.1 Storage Conditions

The products sealed in moisture barrier bags (MBB) should be stored in a non-condensing atmospheric
environment of < 40 °C and 90%RH. The module is rated at the moisture sensitivity level (MSL) of 3.

After unpacking, the module must be soldered within 168 hours with the factory conditions 25±5 °C and
60%RH. If the above conditions are not met, the module needs to be baked.

8.2 Electrostatic Discharge (ESD)

• Human body model (HBM): ±2000 V
• Charged-device model (CDM): ±500 V

8.3 Soldering Profile

8.3.1 Reflow Profile
Solder the module in a single reflow.
Temperature (℃)

Peak Temp.
235 ~ 250 ℃
250
Preheating zone Reflow zone Cooling zone
150 ~ 200 ℃ 60 ~ 120 s 217 ℃ 60 ~ 90 s –1 ~ –5 ℃/s
217
200
Soldering time
> 30 s

Ramp-up zone
1 ~ 3 ℃/s
100

50

25
Time (sec.)
0
0 50 100 150 200 250

Ramp-up zone — Temp.: 25 ~ 150 ℃ Time: 60 ~ 90 s Ramp-up rate: 1 ~ 3 ℃/s

Preheating zone — Temp.: 150 ~ 200 ℃ Time: 60 ~ 120 s
Reflow zone — Temp.: >217 ℃ 60 ~ 90 s; Peak Temp.: 235 ~ 250 ℃ Time: 30 ~ 70 s
Cooling zone — Peak Temp. ~ 180 ℃ Ramp-down rate: –1 ~ –5 ℃/s
Solder — Sn-Ag-Cu (SAC305) lead-free solder alloy

Figure 13: Reflow Profile

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8 Product Handling

8.4 Ultrasonic Vibration

Avoid exposing Espressif modules to vibration from ultrasonic equipment, such as ultrasonic welders or
ultrasonic cleaners. This vibration may induce resonance in the in-module crystal and lead to its malfunction or
even failure. As a consequence, the module may stop working or its performance may deteriorate.

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9 MAC Addresses and eFuse

9 MAC Addresses and eFuse

The eFuse in ESP32-S2 series of chips has been burnt into 48-bit mac_address. The actual addresses the
chip uses in station or AP modes correspond to mac_address in the following way:

• Station mode: mac_address

• AP mode: mac_address + 1

There are seven blocks in eFuse for users to use. Each block is 256 bits in size and has independent
write/read disable controller. Six of them can be used to store encrypted key or user data, and the remaining
one is only used to store user data.

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Related Documentation and Resources

Related Documentation and Resources

Related Documentation
• ESP32-S2 Series Datasheet – Specifications of the ESP32-S2 hardware.
• ESP32-S2 Technical Reference Manual – Detailed information on how to use the ESP32-S2 memory and periph-
erals.
• ESP32-S2 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-S2 into your hardware product.
• ESP32-S2 Series SoC Errata – Descriptions of known errors in ESP32-S2 series of SoCs.
• Certificates
https://espressif.com/en/support/documents/certificates
• ESP32-S2 Product/Process Change Notifications (PCN)
https://espressif.com/en/support/documents/pcns?keys=ESP32-S2
• ESP32-S2 Advisories – Information on security, bugs, compatibility, component reliability.
https://espressif.com/en/support/documents/advisories?keys=ESP32-S2
• Documentation Updates and Update Notification Subscription
https://espressif.com/en/support/download/documents

Developer Zone
• ESP-IDF Programming Guide for ESP32-S2 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
https://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
https://esp32.com/
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
https://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
https://espressif.com/en/support/download/sdks-demos

Products
• ESP32-S2 Series SoCs – Browse through all ESP32-S2 SoCs.
https://espressif.com/en/products/socs?id=ESP32-S2
• ESP32-S2 Series Modules – Browse through all ESP32-S2-based modules.
https://espressif.com/en/products/modules?id=ESP32-S2
• ESP32-S2 Series DevKits – Browse through all ESP32-S2-based devkits.
https://espressif.com/en/products/devkits?id=ESP32-S2
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
https://products.espressif.com/#/product-selector?language=en

Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
https://espressif.com/en/contact-us/sales-questions

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Revision History

Revision History

Date Version Release notes

• Marked ESP32-S2-MINI-1-H4 and ESP32-S2-MINI-1U-H4 as end of life,

and other variants as NRND
• According to PCN20230601, upgraded the chip embedded in ESP32-
2024-04-23 v1.4 S2-MINI-N4R2 and ESP32-S2-MINI-1U-N4R2 from chip revision v0.0 to
chip revision v1.0, and Section 4.5 Current Consumption in Active Mode,
Section 4.6 Wi-Fi RF Characteristics, and Section 5 Module Schematics
are updated with information about chip revision v1.0 accordingly

• Changed Table Ordering Information to Table ESP32-S2-MINI-1 (ANT) Se-

ries Comparison1 and Table ESP32-S2-MINI-1U (CONN) Series Compari-
son
2023-05-25 v1.3 • Added links to some reference documents in Section 1 Module Overview
• Updated EPAD descriptions in Section 6 Peripheral Schematics
• Added descriptions in Section 7.2 Recommended PCB Land Pattern
• Other formatting updates

• Added Section 8.4 Ultrasonic Vibration

2022-09-23 v1.2
• Removed NRND watermark

• Added information about ESP32-S2-MINI-1-H4 � ESP32-S2-MINI-1U-H4

• Added module pictures on the title page
• Added NRND watermark
• Added a note with a link and QR code to the latest version of the docu-
ment
2022-03-01 v1.1
• Updated Section ”Learning Resources” and renamed to ”Related Docu-
mentation and Resources”
• Updated the format for table notes
• Updated Table 13 Current Consumption in Modem-sleep Mode and Table
14 Current Consumption in Low-Power Modes

Cont’d on next page

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Espressif Systems 32 ESP32-S2-MINI-1 & MINI-1U Datasheet v1.4
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Revision History

Cont’d from previous page

Date Version Release notes

• Added module variants embedded with the ESP32-S2FN4R2 chip

• Added module description to the title page
• Updated Chapter 1 Module Overview
2021-06-25 v1.0
• Added description in Section 7.3 Dimensions of External Antenna Con-
nector
• Replaced ”chip family” with ”chip series” following Espressif’s taxonomy

• Added TWAI to Chapter 1 Module Overview

• Updated Table 4.5 Current Consumption in Active Mode
2020-12-17 v0.6 • Updated the capacitance value of RC delay circuit to 1 µF in Chapter 6
Peripheral Schematics
• Updated note in Section 8.3.1 Reflow Profile

2020-09-23 v0.5 Preliminary release.

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 Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO
WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information
in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property
www.espressif.com of their respective owners, and are hereby acknowledged.
Copyright © 2024 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.

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