3300 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO.

6, JUNE 2015

3-D Thermal Component Model for Electrothermal

Analysis of Multichip Power Modules
With Experimental Validation
John Reichl, José M. Ortiz-Rodrı́guez, Allen Hefner, and Jih-Sheng Lai

Abstract—This paper presents for the first time a full three- coupling between chips must be considered within the elec-
dimensional (3-D), multilayer, and multichip thermal component trothermal models.
model, based on finite differences, with asymmetrical power distri- Modeling the heat diffusion equation for thermal model
butions for dynamic electrothermal simulation. Finite difference
methods (FDMs) are used to solve the heat conduction equation in development is extensive in research and publications. The
three dimensions. The thermal component model is parameterized most widely published electrothermal models in past litera-
in terms of structural and material properties so it can be readily ture assume single-chip configurations where assumed one-
used to develop a library of component models for any available dimensional (1-D) heat conduction is all that is required to
power module. The FDM model is validated with a full analytical predict junction temperatures. The authors in [2]–[4] use Cauer
Fourier series-based model in two dimensions. Finally, the FDM
thermal model is compared against measured data acquired from a networks, which contain R and C values with true physical
newly developed high-speed transient coupling measurement tech- meaning contrary to the widely used Foster cells. The R and
nique. By using the device threshold voltage as a time-dependent C values are determined from thermal transient measurements
temperature-sensitive parameter (TSP), the thermal transient of a generated from a heat source caused by a down-step variation
single device, along with the thermal coupling effect among nearby of heating power.
devices sharing common direct bond copper (DBC) substrates, can
be studied under a variety of pulsed power conditions. Each of the methods described in [2]–[4] results in com-
pact models parameterized in terms of structural and material
Index Terms—Compact thermal model, component thermal properties. But these models are only valid for a 1-D thermal
model, electrothermal, multichip modules, soft switching inverter.
profile where only a single chip is considered and an additional
model synthesis step is required from measurement or three-
I. INTRODUCTION dimensional (3-D) FEM analysis. In order to model lateral heat
spread due to thermal coupling within multichip modules, a
N order to further increase power densities within multichip
I power modules containing single-phase and three-phase in-
verter bridges, soft switching techniques are required along with
method that includes multidimensional (>1-D) heat conduction
has to be considered.
Fourier series-based thermal models proposed in [5]–[9] are
dense packaging. Soft switching techniques such as the tech-
parameterized in terms of structural and material properties and
nique described in [1] allow for the reduction or elimination
use feedback loops to force the appropriate boundary conditions
in switching loss by turning a device on under zero voltage
between multiple layer interfaces involving different materials.
switching (ZVS). Modules like the one in [1] contain multiple
Material interfaces with different cross-sectional area are ac-
insulated gate bipolar transistor (IGBT), MOSFET, and diode
counted for by increasing or decreasing the number of Fourier
chips mounted on a common direct bond copper (DBC) and
terms appropriately [9]. Each of these proposed methods are not
baseplate layers. As a result of the close proximity of the IGBT,
full analytical solutions to the heat conduction equation and still
MOSFET, and diode chips, lateral heat spread due to thermal
rely on some numerical solution to determine the Fourier coeffi-
cients. Therefore, an ordinary differential equation (ODE) solver
Manuscript received March 18, 2014; revised June 18, 2014; accepted June is still required from a simulator such as MATLAB Simulink.
26, 2014. Date of publication July 11, 2014; date of current version January 16, The increased simulation speed that typically results from a
2015. This work was supported by the DOE Contract DE-FE26-07NT43214. Fourier-based solution is further decreased by requiring an ad-
Recommended for publication by Associate Editor T. M. Lebey.
J. Reichl is with the Bradley Department of Electrical and Computer En- ditional feedback loop to ensure the proper boundary condi-
gineering, Future Energy Electronics Center, Virginia Tech, Blacksburg, VA tions between material interfaces. The accuracy of the solution
24060 USA, and also with the Semiconductor Electronics Division, National is therefore determined by the size of the feedback gain, which
Institute of Standards and Technology, Gaithersburg, MD 20899 USA (e-mail:
[email protected]). results in longer simulation time as the gain is increased. While
J. M. Ortiz-Rodrı́guez and A. Hefner are with the Semiconductor Electronics Fourier-based methods are advertised to be much quicker than
Division, National Institute of Standards and Technology, Gaithersburg, MD finite difference methods (FDMs), the computation savings may
20899 USA (e-mail: [email protected]; [email protected]).
J.-S. Lai is with the Bradley Department of Electrical and Computer En- not be as obvious once a full 3-D multichip chip configuration
gineering, Future Energy Electronics Center, Virginia Tech, Blacksburg, VA is considered requiring large feedback gains and a large number
24060 USA (e-mail: [email protected]). of Fourier terms solved numerically for accurate solutions. In
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. addition, the Fourier-based solutions do not consider the imper-
Digital Object Identifier 10.1109/TPEL.2014.2338278 fect contact that may exist between materials that can result in

0885-8993 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
REICHL et al.: 3-D THERMAL COMPONENT MODEL FOR ELECTROTHERMAL ANALYSIS OF MULTICHIP POWER MODULES 3301

significant temperature differences. Also, it is not easy to in-

clude temperature-dependent properties such as the nonlinear
thermal conductivity of silicon.
The most widely used method for thermal modeling of mul-
tichip power modules involve curve fitting Foster RC cell net-
works from data sheet provided thermal transient curves or 3-D
FEM solvers like Kojima et al. [10]–[16]. Kojima et al. [10],
[11] present an RC compact thermal model of a high-voltage
inverter module containing multiple chips based on Foster net-
work cells. The Foster network cells are determined from a Fig. 1. Circuit diagram of a full-bridge-coupled magnetic type ZVS inverter
thermal impedance matrix extracted from a 3-D FEM solver. module.
The impedance matrix describes the self-heating of each chip
within the module and the heating of a single chip due to the
heating of neighboring chips. Therefore, a full 3-D model that where increased computation time of an FDM-based model was
faithfully represents the lateral thermal interaction among neigh- desired was proposed in [29]. A set of N first-order finite differ-
boring chips is achieved. This method faithfully describes a 3-D ence equations describing the heat equation was converted to a
module and the strong thermal coupling between chips but re- set of M equations, where M  N . This is done by applying a
quires a full 3-D FEM and model extraction for any new module generalized minimized residual (GMRES) algorithm where the
configuration resulting in an extra model synthesis step. reduced number of equations can be represented by equivalent
Walkey et al. [17], [18] present a multichip compact ther- M Foster cells. The application of the GMRES algorithm is an-
mal model using voltage controlled voltage sources to represent other synthesis step, however, and may not be easily included
chip to chip thermal coupling. The generation of the model still in a compact thermal model.
involves extraction of parameters from either an analytical or This paper presents a 3-D FDM similar to the techniques used
numerical solution to the heat equation to generate a per device in [23] and [24] as a solution to the heat conduction equation
thermal model. for a multichip module. However, a full 3-D multilayered pack-
In [19] the addition of current sources representing chip to age describing the DBC layers is considered beneath the silicon
chip coupling are inserted at various locations into a foster net- chips. In addition, the imperfect thermal contact between mate-
work. The locations of these current sources are determined rials is also included and thermal-dependent parameters such as
from 3D FEM. the nonlinear thermal conductivity of silicon are considered.
The method presented in [20] results in a compact thermal Finally, the FDM model is also validated against measured
model where 3-D heat flow is accounted for by using appropriate data resulting from a newly developed high-speed double chip
symmetry in the discretization of the heat equation. The ther- temperature-sensitive parameter (TSP) transient measurement
mal package model, for example, describes the two-dimensional developed in [22]. By using the device threshold voltage as a
(2-D) later heat spreading by considering an effective heat flow time-dependent TSP, the thermal transient of a single device,
area approach. This method was extended to thermal component along with the thermal coupling effect among nearby devices
models for multichip considerations in [21] where neighboring sharing common (DBC) substrates, can be studied under a vari-
chips sharing a common DBC were assumed to have the same ety of pulsed power conditions. This technique allows hardware
power dissipation. However, in conditions where there are mul- model validation under short-term high-power dissipation levels
tiple chips with varying power dissipation sharing a common to be captured along with the thermal time constants resulting
DBC, the effective heat flow area is not well known ahead of from the chip to chip coupling over longer term power dissipa-
time. And in these cases, 1-D heat flow cannot necessarily be tions without the use of thermal couples.
assumed.
In [27] an analytical based solution to the heat equation based II. THERMAL MODEL DEVELOPMENT
on a greens function representation of the temperature field of a
three dimensional system was presented. However the solution A. Application
requires matrices to be determined through a least squares fit to The device considered in this paper is a half-bridge power
a thermal transient heating curve. module made up of MOSFETs and IGBTs operated in parallel
FDMs offer the most flexibility in representing thermal com- along with auxiliary devices made up of IGBTs for enabling the
ponent models parameterized in terms of structural and mate- ZVS condition. The application, shown in Fig. 1, is a single-
rial properties that faithfully can represent chip to chip thermal phase, full-bridge coupled magnetic ZVS inverter [1]. The mag-
coupling. The results are compact thermal models that can be netic elements Lr 1 and Lr 2 in Fig. 1 store energy enabled by the
used as building blocks for any multichip module configuration auxiliary devices, allowing discharge of the main device para-
without requiring additional modeling synthesis steps involving sitic capacitance aligning the device with zero volts prior to turn
thermal transients or 3-D FEM models. It is often referenced on. The turn-on switch loss is eliminated with this technique,
in literature that FDM methods require too much computing thereby drastically decreasing the overall switch loss resulting
time and cannot coexist with an electrical simulation making in increased module efficiency and minimizing EMI within the
dynamic electrothermal models impossible. A recent method system.
3302 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 6, JUNE 2015

Fig. 2. Module components of soft switching module.

TABLE I
CONSTANTS OF THERMAL PROPERTIES

Fig. 3. DBC stack up of soft switching module.

Material Thermal conductivity (W/(cm· K)) Density (g/cm3 ) Specific heat (J/(g· K))

Silicon 1.56 2.328 0.712

ALN 2.17 3.24 1.05
C. Heat Equation
Copper 4.01 8.98 0.385
Solder 0.57 8.17 0.159 Referring to Fig. 3, the heat is assumed to be generated on top
of the silicon chip and conducted through the different layers.
This is a multilayer, multidimensional heat conduction problem.
The resulting 3-D transient heat diffusion equation, assuming
The circuit in Fig. 1 is made up of two independent half-
no internal heat generation, at a particular layer i in Cartesian
bridge modules. Referring to Fig. 1, each module contains the
coordinates is shown as follows:
main switching elements of the inverter circuit made up of IG-    
BTs Q1 and Q2 operated in parallel with MOSFETs M1 and ∂ ∂Ti (x, y, z, t) ∂ ∂Ti (x, y, z, t)
ki + ki
M2 respectively. Free-wheeling diodes for the main switching ∂x ∂x ∂y ∂y
elements are also included and designated D1 and D2 in Fig. 1.  
∂ ∂Ti (x, y, z, t) ∂Ti (x, y, z, t)
In addition, to the main switching elements, auxiliary IGBTs + ki = ρi ci ,
∂z ∂z ∂t
Sx1 and Sx2 are also included in each module.
i = 1, . . . , m. (1)
B. Packaging In (1), ρi is the thermal density, ci the specific heat of the
material, respectively, and m represents the number of layers.
Each module utilizes DBC technology where copper is di-
It is often possible to simplify (1) if the thermal conductivity
rectly bonded to a ceramic substrate such as ALN. The thermal
ki of the material is constant. However, in silicon, the thermal
analysis in this paper focuses on two chips exhibiting strong
conductivity is nonlinear and is modeled by [20]
thermal coupling due to their proximity to each other and dif-
ferent power distributions. The different power distributions are  4/3
300
a result of the different circuit function each chip performs in ki (Ti (x, y, z, t)) = 1.5486 . (2)
Ti (x, y, z, t)
the inverter circuit. The power distribution of M1 and Q1 ex-
hibit the traditional inverter switch loss minus the turn-on loss To solve (1) for the module considered in this paper, cer-
due to ZVS condition. The power distribution of Sx1 is much tain boundary conditions are required. A constant surface tem-
different and has a very large peak power for a short dura- perature is maintained at bottom of the module resulting in a
tion to charge the resonant element used for enabling ZVS of Dirichlet boundary condition as shown
the main switch. The chips that are the focus of this paper are Tm (x, y, z, t)|y =y m + 1 = TA . (3)
the auxiliary IGBT Sx1 and main switching MOSFET M1 in
Fig. 1. Both chips share a common DBC and are relatively The top layer of the module corresponds to the heat flux (Watt
close together shown in Fig. 2 outlined in the dotted dashed per square centimeter) generated from the power distribution of
line. each chip where all the heat is assumed to flow into the top
It is desired to have a compact thermal model parameterized boundary of the silicon chip resulting in a Neuman condition
in terms of structural and material properties. Table I shows the shown as follows:

material information for each layer of the DBC. ∂T1 (x, y, z, t) 
The DBC materials and associated material thicknesses and −k1  = q  (t). (4)
∂y y =y 1 =0
dimensions for the two chips Sx1 and M1 are shown in Fig. 3.
The individual power distribution for each chip is assumed The sides of the module and in the areas with no heat flux
evenly distributed at the top of each chip, but the two chips generated on the top of the module, adiabatic boundary condi-
do not have the same power distribution. tions exist and result in a special case of the Neuman condition
REICHL et al.: 3-D THERMAL COMPONENT MODEL FOR ELECTROTHERMAL ANALYSIS OF MULTICHIP POWER MODULES 3303

volume and associated dimensions are shown in Fig. 4

   
p+1 p+1 p+1 p+1
Ti,j +1,k − T i,j,k T i−1,j,k − T i,j,k
kavg Ay z + ki−1 Axz
dxR dy B
 
p+1 p+1
Ti,j −1,k − T i,j,k
+ kavg Ay z
dxL
 
p+1 p+1
Ti+1,j,k − Ti,j,k
+ ki+1 Axz hci bc
hci dy T + ki+1
 
p+1 p+1
Ti,j,k +1 − Ti,j,k
Fig. 4. Interior control volume at a material interface. + kavg Axy
dz F
 
p+1 p+1
Ti,j,k −1 − T i,j,k
shown as follows: + kavg Axy
dz B

∂T1 (x, y, z, t)  p+1
Ti,j,k p
− Ti,j,k
 = 0. (5) = Exyz + q  Axz (bc − 1). (8)
∂y y =y 1 =0 Δt
Finally, if perfect thermal contacts exists between layers of In (8), bc = 1 for interior nodes and bc = 0 for the top of the
different materials silicon chips where a heat flux q is present. For this model, the
heat flux is determined simultaneously by the electrical simu-
Ti (x, yi+1 , z, t) = Ti+1 (x, yi+1 , z, t) (6) lator representing the instantaneous dissipated power of a par-
ticular device and is an input port to the model. The areas Ay z ,
and
Axz , and Axy represent the cross-sectional areas of the control
 
∂Ti (x, y, z, t)  ∂Ti+1 (x, y, z, t)  volume
ki  = ki+1  .   
∂y y =y i + 1 ∂y y =y i + 1
dy T + dy B dz B + dz F
Ay z = ,
(7) 2 2
  
dxL + dxR dz B + dz F
Axz = ,
D. 3-D FDM Thermal Model 2 2
  
The finite difference form of the heat equation in (1) is used to dxL + dxR dy T + dy B
solve the corresponding 3-D temperature distributions within the Axy = . (9)
2 2
multichip module shown in Fig. 2. The finite difference equa-
tions are derived using the energy balance method described The stored energy Exy z within the control volume is given
in [26]. This approach enables one to analyze many different as
phenomena such as problems involving multiple layers and ex- 1
Exy z = (dz F + dz B )(dxL + dxR )(ρi−1 ci−1 dy B
posed surfaces that do not align with an axis of the coordinate 8
system [26]. The finite difference equation for a node is obtained + ρi+1 ci+1 dy T ). (10)
by applying conservation of energy using simplified forms of
Fourier’s law to a control volume about the nodal region. There- The average thermal conductivity taking into account the
fore, the entire volume of the package is discretized into a finite average thermal conductivity at material interfaces is given by
number of nodes. The number of nodes in the y-direction is dy B ki−1 + dy T ki+1
sizey, the number of nodes in the x-direction is sizex and the kavg = . (11)
dy T + dy B
number of nodes in the z-direction is sizez. A variable grid size
is used for determining the number of nodes and results in an As mentioned earlier, contact resistance represents the imper-
optimized computation time. fect thermal contact between materials. The existence of a finite
A finite difference equation using the conservation of energy contact resistance is due to surface roughness effects between
is written to a control volume about an interior node T(i,j,k) in materials resulting in a temperature drop across the interface. In
(8) where i = 1:sizey, j = 1:sizex and k = 1:sizez. The implicit high-power applications, this drop is not negligible and can re-
form of a finite difference equation is used to approximate the sult in significant temperature rise and should be accounted for
time derivative, while evaluating all other temperatures at the in the thermal model. The contact resistance is included in (8)
new (p + 1) time, instead of the previous (p) time. Relative to by including the thermal contact conductance coefficient hci .
the explicit method, the implicit formulation has the advantage This coefficient is a function of the two interface materials and
of being unconditionally stable [26]. The corresponding control the medium between the materials (i.e., air or thermal grease,
3304 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 6, JUNE 2015

Fig. 5 2-D, 6 six-layer validation model.

Fig. 6. Transient interface temperatures.

etc.). The model in this paper included thermal contact resis-
tance between the DBC and the module baseplate. In addition,
thermal resistance was included between the module and the A 2-D, DFS form of the steady state solution for a certain
temperature-controlled heat sink. layer (i) can be written as
To determine the unknown nodal temperatures at t + Δt, the
i = 1 : TS S,1 (xm , yn )
corresponding nodes must be solved simultaneously at each
time step. The nodal equations in this paper were implemented = 1/2 · (a10 · yn + b10 )
in MATLAB, and the matrix inversion technique was used to ⎛  ⎞
N −1 yn − y 1
solve the corresponding nodal equations at each time step. In this  2
⎜ a1j · sinh j · 2π · N ⎟
manner, materials with nonlinear thermal conductivities such as + ⎜  ⎟
⎝ yn − y 1 ⎠
silicon given by (2) can be updated at each time step. j =1 +b1j · cosh j · 2π ·
N
 
2π
III. MODEL VALIDATION · cos j · · xm (14)
N
A. 2-D Discrete Fourier Series Model
A discretized, 2-D temperature field was used to model (1), i > 1 : TS S,i (xm , yn )
since it lends itself to a straightforward, approximate speci-
fication of an arbitrary, dynamic heat flux at the upper surface = 1/2 · (ai0 · yn + bio )
boundary. The temperature grid was N × N , N odd, with a suffi- ⎛  ⎞
yn − yi+1
ciently high grid resolution to reduce approximation error. In this N −1
 a · sinh j · 2π ·
2
⎜ ij N ⎟
particular application, a square wave function was used to model + ⎜  ⎟
⎝ yn − yi+1 ⎠
the applied surface heat flux distribution. It was modeled using j =1 +bij · cosh j · 2π ·
a discrete Fourier series (DFS). Due to the extremely fine grid N
resolution used in the validation modeling, all discrete deriva-  
j · 2π
tives were approximated using continuous derivatives. Fig. 5 · cos · xm . (15)
N
illustrates the geometry that was used in the development of the
2-D, six-layer validation model. The DFS coefficients in (14) and (15) are solved by sat-
The total solution to (1) was sought that contained both a isfying the interfacial boundary conditions, i.e., matching
transient Tr r and a steady-state Tss solution, i.e. heat flux and temperature at each of the layer interfaces;
and the surface and bottom boundary conditions, includ-
T (xm , yn , t) = TT R (xm , yn , t) + TS S (xm , yn ). (12) ing Fourier’s Law of heat conduction and a constant base
temperature, respectively. The insulated boundary conditions
A 2-D, DFS form of the transient solution can be written as at xm = (+(N − 1)/2, −(N − 1)/2) are satisfied using the
 cos((2πj/N ) · xm ) function.
TT R (xm , yn , t) = Cj k · sin (λj · yn ) · cos (λk · xm )
jk B. Model Validation
−κ·λ2j k ·t
·e (13) The DFS model is used for validation of the FDM model
under controlled dimensions and boundary conditions for a two-
where λ2j k = λ2j + λ2k and the individual eigenvalues satisfy the chip asymmetrical heating condition. The 3-D FDM model was
applied homogenous boundary conditions, i.e., zero heat flux at reduced to 2-D for this validation. This was done by applying
the upper and lateral sides of the chip, and zero temperature at the appropriate heat flux boundary condition on the top surface
the base of the chip. The DFS coefficient Cj k satisfies the initial of the module that results in a two dimensional heat conduction
boundary condition for the transient solution at time t = 0. problem. Figs. 6 and 7 show a surface temperature versus time
REICHL et al.: 3-D THERMAL COMPONENT MODEL FOR ELECTROTHERMAL ANALYSIS OF MULTICHIP POWER MODULES 3305

Fig. 9. Calibration data double TSP experiment.

Fig. 7. Steady-state interface temperatures versus x dimension.

surements are set up as differential measurements from the data

acquisition system because a substantial common mode voltage
spike appears on the gate and cathode during switching. This
is due to gate charging current interacting with the gate resister
used to prevent oscillation. The small bias currents also pro-
vides for the capability of using the TSP measurement during
the cooling phase. A heavily bypassed voltage power supply
is used to maintain a constant voltage across both the Sx1 and
MOS1B. Sx1 is pulsed from the small bias current to a large cur-
rent from a custom-made precision current source that features
high-speed gating and current control in 0.1 A increments up to
25.5 A [25].
The power dissipation in Sx1 due to the large pulsed current
and constant device voltage causes the device to heat up causing
the TSP of Sx1 to change. At the same time, the TSP of MOS1B
changes due to the heat source provided by the dissipation in
Sx1 . The measured temperature rise in MOS1B due to the power
dissipation in Sx1 allows model validation of lateral thermal heat
coupling between chips in close proximity.
Fig. 8. Thermal coupling TSP measurement circuit.

B. Test Procedure
plot, and a temperature versus x dimension plot, respectively, The measurement of the IGBT and MOSFET transient heat-
at each layer interface. Both Figs. 6 and 7 illustrate excellent ing requires two parts. First, the TSP of each device must be cal-
agreement between both the FDM model and the DFS validation ibrated at known operating conditions and at a series of known
model. temperatures. Second, with the heat sink at a fixed and known
temperature, the IGBT is subjected to a longer transient heat-
IV. MEASURED AND SIMULATED RESULTS ing pulse where the IGBT temperature increase will result in the
MOSFET temperature increase through thermal coupling within
A. Test Circuit
a common DBC. The TSP for the IGBT Sx1 is the measured
For the thermal cross-coupling experiment, an auxiliary IGBT gate to emitter voltage Vg e in Fig. 8. The TSP for the MOSFET
Sx1 and a main bridge MOSFET M1 are chosen due to their close MOS1B is the measured gate to source voltage Vg s in Fig. 8.
proximity and common DBC layers. M1 is made up of two Fixed temperatures are achieved by having the DUT mounted on
chips—MOS1A and MOS1B—and is shown in Fig. 8. Also, a temperature-controlled heat sink. The same test circuit shown
shown in Fig. 8 is the test circuit used to measure the transient in Fig. 8 can be used for the calibration and transient heating
heating and lateral coupling where the IGBT and MOS under measurement; the difference between these is determined by the
test are the chosen devices Sx1 and MOS1B, respectively. pulsewidth.
Sx1 and MOS1B are biased with small auxiliary currents com- For the calibration curve, the operating conditions that need to
prised of the 60 and 20 V power supplies along with the 3 kΩ be specified include the collector to emitter voltage and collector
resisters to establish an initial threshold voltage measurement current. Using a temperature-controlled baseplate temperature,
shown as Vg e and Vg s in Fig. 8 and provide the corresponding a very short pulsewidth is applied to the IGBT to avoid signif-
TSPs for Sx1 and MOS1B. The 470 Ω gate resistor serves as icant chip heating and the TSP of the IGBT and MOSFET are
a damping resistor to prevent oscillation. The threshold mea- recorded over temperature. The result is shown in Fig. 9 for Sx1
3306 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 6, JUNE 2015

and MOS1B. The TSP is measured for each device during a

heating and cooling phase. The heating phase refers to the TSP
that is measured during the pulse duration and the cooling phase
refers to the TSP that is measured after the pulse is removed.
The result of this calibration curve is an established relationship
between chip temperature and the corresponding TSP values of
the IGBT and MOSFET.
For the transient heating measurement, the current and voltage
conditions are the same as was for the TSP calibration. The
temperature of the heat sink is held constant at one temperature
for all heating measurements. The current pulsewidth of Sx1 is
increased long enough to show significant chip heating of both
Sx1 and MOS1B. The TSP values for both Sx1 and MOS1B
are recorded as a function of time, and the voltage waveforms
are mapped into temperature as a function of time by using the
calibration data. Each IGBT and MOSFET operating condition
requires a new calibration. Due to the time consuming process Fig. 10. Sx 1 transient heating measured versus simulated.
of calibration, a fully automated system has been developed at
NIST.
ture of a thermal couple located in the bottom baseplate. For our
C. Operating Conditions experiment, we chose not to run the heater and applied the high-
est water pressure possible to bring the baseplate temperature
Sx1 is pulsed with a peak power of 100 W under a variety of
below room temperature. This, however, does not guarantee the
pulsewidth conditions to provide multiple points of validation
entire baseplate is at the same temperature. Therefore, the ther-
for both Sx1 and MOS1B. The TSP of Sx1 and MOS1B are
mal mass and resistance of the two copper plates were included
monitored while Sx1 is pulsed. The average power applied to
as an additional layer in the model with a constant temperature
the IGBT is varied by using different power pulsewidths of
assumed at the very bottom.
constant power amplitude and multiple successive pulses are
In addition, contact resistance was added to represent the
also used to capture dynamic transient heating of the IGBT and
poor thermal contact at the interface between the two copper
neighboring MOSFET. The pulse repetition frequency is made
baseplates. The thermal contact conductance coefficients were
low enough to capture and study the thermal time constant of
not determined experimentally. Therefore, an assumption on
the heat propagation from the IGBT to the MOSFET. Much
the conductance coefficient is assumed based on a copper to
higher speed shorter pulses can be used to capture the resolution
copper interface and then adjusted within reason to achieve the
required to validate the silicon chip thermal model under a high-
correct offset temperature resulting from the measured data.
power short condition. This has been done in previous works by
A copper to copper interface thermal conductance coefficient
the authors of this study [25].
of 5.5 W/(cm2 ·K) [28] was applied at the interface of the two
In [25], the cooling effects had not been measured and only
copper baseplates and adjusted to 1.2 W/(cm2 ·K). This implies
transient heating was studied under very short power duration.
very poor contact between the two copper to copper interfaces.
The new system with cooling functionality allows successive
Future measurements should remove this interface. The module
pulse trains to be generated where the temperature of the de-
to baseplate coefficient was adjusted from 5.5 to 10 W/(cm2 ·K),
vice does not return to the heat sink temperature before the
which implies better thermal contact between the module and
next pulse. Therefore, a thermal steady state can be gener-
baseplate.
ated and used for further model validation and study of thermal
Fig. 10 shows the measured versus simulated data under a
coupling.
variety of pulsewidths of Sx1 , and Fig. 13 shows the resulting
MOS1B temperature resulting from the heating of Sx1 . There
D. Measured Data Versus FDM Model Prediction is excellent agreement between the measurement and measured
The FDM compact model was simulated with the dimensions data with the biggest error within a few degrees. Both the heating
from Fig. 3 and the material properties from Table I. A pulsed and cooling portions of the curves show very good agreement
heat flux was applied to Sx1 and the junction temperature of thus validating the entire DBC under a variety of conditions. In
Sx1 and MOS1B were monitored in the model under the same addition, the thermal coupling temperature and time constant
peak power and duty cycle conditions from the experiment. The from Sx1 to MOS1B are captured very nicely with the new
module was mounted onto a baseplate constructed of two cop- model. It should be noted that the measurement points within
per plates with piping and heaters installed in the bottom plate. the model were taken at the center of the chip. This may not
The two copper plates are joined together by thermal grease and be as accurate for capturing the MOSFET temperature due to
screws. Cold water is run through the piping and the heater is coupling since there is a temperature gradient across the top of
controlled by applying a voltage to the heater. This voltage is the chip. Therefore, computing the average temperature of the
the output from a feedback controller measuring the tempera- top of chip may result in a closer match in Fig. 11.
REICHL et al.: 3-D THERMAL COMPONENT MODEL FOR ELECTROTHERMAL ANALYSIS OF MULTICHIP POWER MODULES 3307

Fig. 12. Loss profile applied to FDM model. Power (top) and energy (bottom).

Fig. 11. MOS1B transient heating measured versus simulated.

V. INVERTER LOSS CONSIDERATION

The major losses in an inverter are due to conduction loss
and switching loss. The major switching loss is due to diode
reverse recovery induced turn-on loss and IGBT turn-off cur-
rent induced turn-off loss. Turn-on switching loss due to voltage
and current crossover during commutation can be reduced with
soft switching control as suggested in [1]. The IGBT turn-off
loss can result in large instantaneous power dissipation while
the tail current is decaying and the IGBT is supporting a large
voltage. This large instantaneous turn off loss can result in de-
vice failure in some cases due to a large instantaneous junc- Fig. 13. Inverter IGBT and periphery temperature.
tion temperature. This effect is one of the major motivations
behind dynamic electrothermal modeling. The thermal model
proposed in this study can coexist with the physics-based de- resistance, M is the modulation index, and ϕ is the power factor
vice models in an electrical switching simulation and predict angle. The average switching loss for an IGBT is given by
instantaneous junction temperature within a switching cycle.
In addition, short-circuit or failure modes can be studied. The 1 Vdc Γ ((β + 1)/2)
electrothermal model, therefore, becomes a valuable tool to the
β
Psw −IGBT = αIm kg fsw √ (17)
2 π Vtest Γ ((β/2) + 1)
engineer during the design process and can help aid the engineer
in predicting system efficiency and system reliability. where kg is the gate drive stiffness factor, fsw the switching
As an example of the capability of the thermal model pro- frequency, α and β are the turn-on and turn-off energy
posed in this study, a dynamic power dissipation profile is used as coefficients, and Vdc and Vtest represent the dc-bus voltage and
an input to the thermal model. The power dissipation profile rep- test voltage for switching energy coefficients, respectively. The
resents the instantaneous power dissipation of a typical IGBT in energy coefficients are readily available from the energy curves
a switching inverter. Both turn-on and turn-off losses, in addition given by the IGBT data sheets. For this example the IGBT
to conduction loss, are included in the instantaneous power dis- part number CM400DY-12NF is used. The calculated average
sipation. Therefore, the model can be tested with inputs contain- conduction loss was approximately 120 W. The average turn-on
ing the high-frequency content associated with switching loss and turn-off loss are 23 and 40 W, respectively. The total
within a switching cycle and the low-frequency content associ- average device loss is therefore 183 W. All loss calculations
ated with the inverter line frequency. The profile models a dual were made at 25 °C. The average loss calculations resulting
modulation method for a 280 V, 55 kW full-bridge inverter with from (16) and (17) were mapped into an instantaneous power
a switching frequency of 10 kHz and an inverter line frequency dissipation profile and used as an input to the thermal model.
of 60 Hz. Assuming a 0.83 power factor, the peak phase current Fig. 12 shows the IGBT instantaneous power dissipation and
is 315 A. The average conduction loss for an IGBT is given by energy during a single switching cycle of the inverter. Esw
  represents the energy at turn on and turn off.
1 1 Fig. 13 shows the IGBT junction temperature in addition to
Pc−IGBT = Im Vt + M cos φ
2π 8 the lateral peripheral temperature of the package. This shows
  that the thermal model predicts a lateral peripheral temperature
2 1 M
+ Im Rce + cos φ (16) rise due to thermal coupling as a result of power dissipated in
8 3π
the IGBT. As can be seen, there is not only the low-frequency
where Im is the peak output current, Vt is the IGBT fixed volt- content associated with the inverter frequency but also the higher
age drop under zero current condition, Rce is the IGBT on-drop frequency associated with switching loss.
3308 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 6, JUNE 2015

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