Minimum Mode 8086 System

➢ In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its
MN/MX pin to logic 1.
➢ In this mode, all the control signals are given out by the microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
➢ The remaining components in the system are latches, transreceivers, clock generator, memory and I/O
devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending
upon the address map of the system.
➢ Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the
valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by
8086.
➢ Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They are
required to separate the valid data from the time multiplexed address/data signals.
➢ They are controlled by two signals namely, DEN and DT/R.
➢ The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for
the monitor and users program storage.
Minimum mode 8086 system and timings

➢ The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts,
the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.
➢ The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO
signal. During the negative going edge of this signal, the valid address is latched on the local bus.
➢ The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO signal indicates a
memory or I/O operation.
➢ At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The
read (RD) control signal is also activated in T2.
➢ The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the
valid data is available on the data bus.
➢ The addressed device will drive the READY line high. When the processor returns the read signal to

high level, the addressed device will again tristate its bus drivers.

➢ A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is

again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the

processor sends the data to be written to the addressed location.

➢ The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2

(unlike RD is somewhat delayed in T2 to provide time for floating).

➢ The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or

write.
TIMING DIAGRAMS FOR 8086 IN MINIMUM
MODE
BUS CYCLE AND TIME STATES
➢ A bus cycle or machine cycle defines the sequence of events when the MPU communicates with an
external device, which starts with an address being output on the system bus followed by a read or
write data transfer.
Types of bus cycles:
✓ Memory Read Bus Cycle
✓ Memory Write Bus Cycle
✓ Input/output Read Bus Cycle
✓ Input/output Write Bus Cycle

➢ One cycle of clock is called a state or t-state. The bus cycle of the 8086 microprocessor consists of at
least four clock periods. These four time states are called T1, T2, T3 and T4. This group of states is
called a MACHINE CYCLE.
➢ The total time required to fetch and execute an instruction is called an instruction cycle. An instruction
cycle consists of one or more machine cycle.
Memory Read Cycle
➢ During period T1,
✓ The 8086 outputs the 20-bit address of the memory
location to be accessed on its multiplexed
address/data bus. BHE is also output along with the
address during T1.
✓ At the same time a pulse is also produced at ALE. The
trailing edge or the high level of this pulse is used to
latch the address in external circuitry. o Signal M/IO is
set to logic 1 and signal DT/R is set to the 0 logic level
and both are maintained throughout all four periods
of the bus cycle.

➢ Beginning with period T2,

✓ Status bits S3 through S6 are output on the upper four
address bus lines. This status information is
maintained through periods T3 and T4.
✓ On the other hand, address/data bus lines AD0
through AD7 are put in the high-Z state during T2.
✓ Late in period T2, RD is switched to logic 0. This
indicates to the memory subsystem that a read cycle
is in progress. DEN is switched to logic 0 to enable
external circuitry to allow the data to move from
memory onto the microprocessor's data bus.
Memory Read Cycle
➢ During period T3,
✓ The memory must provide valid data during T3 and
maintain it until after the processor terminates the
read operation. The data read by the 8086
microprocessor can be carried over all 16 data bus
lines.

➢ During T4,
✓ The 8086 switches RD to the inactive 1 logic level to
terminate the read operation. DEN returns to its
inactive logic level late during T4 to disable the
external circuitry.
Memory Read Cycle
➢ During period T1,
✓ The address along with BHE is output and latched
with the ALE pulse. o M/IO is set to logic 1 to indicate
a memory cycle.
✓ However, this time DT/R is switched to logic 1. This
signals external circuits that the 8086 is going to
transmit data over the bus.

➢ Beginning with period T2,

✓ WR is switched to logic 0 telling the memory
subsystem that a write operation is to follow.
✓ The 8086 puts the data on the bus late in T2 and
maintains the data valid through T4. Data will be
carried over all 16 data bus lines.
✓ DEN enables the external circuitry to provide a path
for data from the processor to the memory.
Maximum Mode 8086 System
➢ In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this mode, the
processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control
signal using this status information.
➢ In the maximum mode, there may be more than one microprocessor in the system configuration.
➢ The components in the system are same as in the minimum mode system.
➢ The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (for
memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status
lines.
➢ The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.
➢ It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB
and CEN pins are specially useful for multiprocessor systems.
Maximum Mode 8086 System
Maximum Mode 8086 System
➢ AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN
output depends upon the status of the IOB pin.
➢ If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral
data enable used in the multiple bus configurations.
➢ INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.
➢ IORC, IOWC are I/O read command and I/O write command signals respectively. These signals enable
an IO interface to read or write the data from or to the address port.
➢ The MRDC, MWTC are memory read command and memory write command signals respectively and
may be used as memory read or write signals.
➢ All these command signals instructs the memory to accept or send data from or to the bus.
Maximum Mode 8086 System
➢ For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.

➢ Here the only difference between in timing diagram between minimum mode and maximum mode is the
status signals used and the available control and advanced command signals.

➢ R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply
a required signal to its DT / R pin during T1.

➢ In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These
signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or
IOWC is activated from T3 to T4.

➢ The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

➢ If reader input is not activated before T3, wait state will be inserted between T3 and T4.