JSPM’s

Rajarshi Shahu College of

Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

Department of Electrical Engineering

Laboratory Manual
for Analog and digital Circuits
 JSPM’s
Rajarshi Shahu College of Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

Department of Electrical Engineering

Class: S.Y. B. TECH

Subject: Analog and Digital Circuits

Laboratory Manual
(Version 2)
 JSPM’s
Rajarshi Shahu College of Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

Vision of the Institute

To satisfy the aspirations of the youth force who want to lead the
nation towards prosperity through techno-economic development.

Mission of the Institute

To provide, nurture and maintain an environment of high academic

excellence, research, and entrepreneurship for all aspiring students
which will prepare them to face global challenges maintaining high
ethical and moral standards.

Vision of the Department

To develop globally competent Electrical Engineers by providing

industry oriented academic environment that inculcates professional
skills and ethics for techno-social benefits.

Mission of the Department

1. To transform students into successful professionals by inculcating

comprehensive knowledge of Electrical Engineering.
2. To develop a conducive environment through creativity, innovation
and industry institute interaction.
3. To encourage and enable students for higher education, research
and entrepreneurship.

2 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 JSPM’s
Rajarshi Shahu College of Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

Program Outcomes (PO’s)

Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change

3 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 JSPM’s
Rajarshi Shahu College of Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

Course Outcomes (CO’s)

CO1 Demonstrate the various applications of Op-Amp.

CO2 Illustrate the performance of FET.

CO3 Analyse the amplifier circuits.

CO4 Design of combinational circuits.

CO5 Design of sequential circuits.

CO6 Analyse uncontrolled rectifiers, filters & regulators.

4 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 JSPM’s
Rajarshi Shahu College of Engineering
(An Autonomous Institute affiliated to SPPU, Pune)

List of Experiments
Sr. No. Experiment Title Course Outcome (CO)
1. a) Study of 8-bit ring counter CO5

b) Study of twisted ring counter

2. a) Study of op-amp as a comparator CO1

b) Study of op-Amp as a zero-crossing detector

3. Study of op-amp as Schmitt trigger. CO1

4. Study of various flip-flops and verification of truth table. CO5

5. Study of characteristics of MOSFET CO2

6. Simulate frequency response of single stage CS amplifier CO3

(Simulator-multi sim based) and find the bandwidth.
7. a) Study of Encoder and decoder CO4

b) Study of Mux and Demux

8. Study of single-phase half wave and full wave rectifier CO6

Extra Experiments

1. Study of Op-amp as sine, and triangular wave generator CO1

2. Study of Instrumentation amplifier using three Op-amp, CMRR CO1

measurement
3. Design, build and test Comparator and Schmitt trigger. CO1
(Simulator based)
4. Design of Summing, scaling, and averaging amplifier. CO1
(Simulator-multisim based)
5. Build and test single stage CS amplifier using FET. Calculate Ri, CO2
Ro and Av. (Simulator-multisim based)
6. Study and verify shift register operation CO5

7. Study of up-down counters CO5

8. Study of IC-555 applications- astable and monostable CO6
multivibrator
5 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade
 EXPERIMENT NO: 1

Aim: a) Study of 8 bit Ring counter

b) Study of 8 bit twisted ring counter

Objectives: Study of counting process of 8-Bit Ring Counter and twisted ring counter

Outcomes:

Students will able to understand

• Operation of Ring counter
• Operation of twisted ring Counter.

Apparatus:

Sr. No. Apparatus

1. 8- bit ring counter Trainer kit

2. 8- bit twisted ring counter Trainer kit

3. Power supply

4. Connecting Links/Wires

Theory:
A counter driven by a clock can be used to count the number of clock cycles. Since the clock
pulses occur at known intervals, the counter can be used as an

instrument for measuring time and period or frequency.

Types Of Counter:
1. Asynchronous or ripple counters
2. Synchronous counters.

1. Asynchronous Or Ripple Counters: For these types counters the external clock signal is
applied to one flip-flop and then the output of preceding flip-flop is connected to the clock of next
flip-flop. E.g. ripple counter.

2. Synchronous Counters: In synchronous counters all the flip-flops receive the external clock
pulse simultaneously. Ring counter and Johnson counter are the examples of synchronous
counters.
Ring counter & twisted ring counter are applications of the shift register.

6 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Ring Counter:

The Ring Counter is one of the types of synchronous counter. A Ring Counter circulates a single
bit among the flip-flops to provide different distinguishable states. It is a shift register with
feedback. A register is capable of shifting its binary information either to the right or to the left is
called a shift register. The logical configuration of a shift register consists of a chain of flip-flops
connected in cascade, with the output of one flop-flop connected to the input of the next flip-
flop. All flip-flops receive a common clock pulse which causes the shift from one stage to the
next. The output of the last flip-flop in a shift register is connected back to the control input of
the first flip-flop in the register. Thus the shift register with this direct feedback technique is
known as Ring Counter.

4-Bit Ring Counter: We will make provisions for loading data into the parallel-in/ serial-out shift
register configured as a ring counter below. Any random pattern may be loaded. The most
generally useful pattern is a single 1

Loading binary (Q3Q2Q1Q0= 0001) into the ring counter, above, prior to shifting yields a viewable
pattern. The data pattern for a single stage repeats every four clock pulses in our 4-stage example.
The waveforms are shown in figure below.

Application:- It is used in stepper motor(which rotate in steps) which requires sequential pulses
to rotate it from one position to the next.

A Twisted Ring Counter:-

7 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

It is also called Johnson counter or switch-tail ring counter. It overcomes some of the limitations
of the ring counter. Like a ring counter a Johnson counter is a shift register fed back on its’ self..
If the complement output of a ring counter is fed back to the input instead of the true output, a
Johnson counter results. The difference between a ring counter and a Johnson counter is which
output of the last stage is fed back (Q or Q’).

4-Bit Twisted Ring Counter:-

This “reversed” feedback connection has a profound effect upon the behavior of the otherwise
similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor
equal to the number of stages. Start a Johnson counter by clearing all stages to 0s before the first
clock. This is often done at power-up time. Referring to the figure below, the first clock shifts three
0s from ( Q0 Q1 Q2) to the right into ( Q1 Q2 Q3).

The 1 at Q3’ (the complement of Q) is shifted back into Q0. Thus, we start shifting 1s to the right,
replacing the 0s. Where a ring counter recirculated a single 1, the 4-stage Johnson counter
recirculates four 0s then four 1s for an 8-bit pattern, then repeats.

8 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Circuit Diagram:-

For 8-bit Ring Counter

A. For 8-bit Twisted Ring Counter

Procedure:

A. For 8-bit Ring Counter

1. Connect +5V and ground to their indicated position on experiment board from DC
power supply.
2. Connect clock pulse from socket ‘CLK’.
3. Switch ‘On’ the power supply.
4. Press switch S1 (clear data) once to reset the outputs Q1-Q8.
5. Keep the position of switch S1 and S2 to logic high in normal operation.
6. Load the 8 bit data by SISO manner.
7. After loading data connect Q output of last flip-flop to the input of first flip-flop to
operate as ring counter.
8. Apply 8 clock pulses and Observe the desired count sequence.

9 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

B. For 8-bit Twisted Ring Counter
1. Repeat the above Steps 1 to 7
2. After loading data connect Q complement ( Q’) output of last flip-
Flop to the input of first flip-flop to operate as twisted ring counter.

3. Apply 16 clock pulses and Observe the desired count sequence.

Observation Table:-

A. For 8-bit Ring Counter

Clock
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Pulse

Initial

B. For 8-bit Twisted Ring Counter

Clock
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Pulse

Initial

10 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 4

10

11

12

13

14

15

16

Conclusion:

Questions:

1. What is difference between asynchronous and synchronous counter?

2.What is difference between ring and twisted ring counter

11 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 2

Aim: a) Study of op-amp as a comparator

b) Study of op-Amp as a zero-crossing detector.

Objectives:
• Study the applications of Op-Amp as a Comparator and as a Zero crossing detector.

Outcomes:

Students will able to understand

• Applications of Op-Amp as a Comparator and Zero crossing detector (ZCD)

Apparatus:

Sr. No. Apparatus

1. Analog trainer Kit

2. Function Generator

3. Oscilloscope

4. Dual Power supply

5. Multimeter

6. Connecting Links/Wires

Theory:
The operational amplifier is a versatile device that can be used to amplify DC as well as AC input
signals and was originally designed for performing mathematical operations such as addition,
subtraction, multiplication, and integration. Thus the name operational amplifier seems from its
original use for these mathematical operations and is abbreviated to op-amp. With the addition of
suitable external feedback components, the modern day op-amp can be used for a variety of
applications, such as AC and DC signal amplification, active filters, oscillators, comparators,
Schmitt trigger, regulator, integrator, differentiator.

Comparator (Voltage Level Detector):

An op-amp comparator is a circuit which compares an arbitrary input signal against a fixed
reference voltage. The output of the comparator circuit switches between the two saturation
voltages depending on the value of arbitrary input signal w.r.t the reference voltage (if the input
amplitude is less than the reference voltage, output is at one saturation level and vice-versa).

As shown in figure 1 a non-inverting comparator circuit. A fixed reference voltage Vref (say 1V
or 2V…) is applied to the (-) input (shown in figure 2a for Vref = 1V and figure 2b Vref = -1V),
and the other time varying signal voltage Vin is applied to the (+) input of op-amp. When Vin is
less than Vref, the output voltage Vout is at –Vsat (approximately equal to -VEE) as the voltage

12 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

at (-) input terminal is higher than that of the (+) input terminal. On the other hand, when the (+)
input terminal voltage Vin is greater than Vref, the (+) input terminal becomes positive w.r.t. the
(-) input and the Vout bring switches to +Vsat (approximately equal to +Vcc).

Figure:1

Figure:2
Thus, Vout changes from one saturation level to another whenever Vin = Vref as shown in figure
2 (a). In short comparator is a type of analog-to-digital converter. At any given time the Vout
shows whether Vin is greater or less than Vref. This is the reason why it is also called a voltage
level detector. In the similar way if the reference voltage is negative w.r.t. ground, with the
sinusoidal input applied to the noninverting terminal of op-amp the output will be as shown in
figure 2 (b).

Zero-crossing Detector (Sine wave-to-Square Wave Converter):

The above shown circuit can also be used as a zero crossing detector provided that Vref is set to
zero (Vref = 0). As shown in figure 3 (a), which is an inverting comparator used as a zero
crossing detector.

13 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Circuit Diagram:

A) Inverting Comparator: -

B) Zero-crossing Detector ( Non Inverting):

Procedure:

A) Op-Amp as a Non Inverting Comparator:

1. Connect +12V and -12V DC power supplies at their indicated positions on
Analog board from external source.
2. Connect variable +5V DC signal between points a and g1 i.e. to the inverting input of
the Op-amp through 300 Ohms resistance. This DC signal will act as a reference
Voltage against which the level of input signal will be compared.
3. Connect a 10Vp-p, 1 KHz signal between points f and g2 i.e. to the noninverting
input of the Op-amp. (Select the inverting and noninverting input terminal resistance
values to be equal).
4. Adjust the variable DC signal to 1V and observe the output waveform between
points i and g3 on Ch I of oscilloscope and input signal on Ch II of oscilloscope.
14 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade
 5. Vary the DC signal gradually from 1V to 5V and observe the output voltage
waveform with respect to input signal.
6. Plot the output waveforms on graph paper for both the above cases. (Refer figure 1
and figure 2).
B)
C) Op-Amp as a Zero-crossing Detector:

1. Connect +12V and -12V DC power supplies at their indicated positions on

Analog board from external source.
2. Connect a 10Vp-p, 1 KHz signal between points f and g2 i.e. to the noninverting
input of the Op-amp.
3. Connect the point a to the point g1 to analyze Op-amp as Zero Crossing Detector.
This connection will make reference voltage to be equal to 0V (Vref = 0V).
4. Observe the output waveform between points i and g3 on Ch I of oscilloscopeand
input signal on Ch II.
5. To make sure that the output waveform is crossing zero level at the same instant
to that of the input signal, adjust the offset pot.

6. Plot the output waveforms on graph paper for the Vref = 0V. (Refer figure 3)

Observation Table:

A) Op-Amp as a Non Inverting Comparator:

Reference Input Output Voltage On Off Total
Sr. Voltage Voltage V0 Time Time Time
No. Vref V0 +Vsat -Vsat (mSec) (mSec) (mSec)
(volt) (volt) (volt) (volt)

10 Vpp

10 Vpp

B) Op-Amp as a Zero-crossing Detector:

Reference Input Output Voltage On Off Total

Sr. Voltage Voltage V0 Time Time Time
No. Vref V0 +Vsat -Vsat (mSec) (mSec) (mSec)
(volt) (volt) (volt) (volt)

0V 10Vpp

Graph: Draw the Input-Output waveform of Op-Amp as a Comparator and ZCD.

15 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Conclusion:

Questions:

1. How to convert Op-Amp as comparator to Op-amp as ZCD?

2. State the other applications of Comparator.

16 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 3

Aim: Study of op-amp as Schmitt trigger.

Objectives: Understand the operation of Op-amp as Schmitt trigger

Outcomes:

Students will able to understand

Operation of Op-amp as Schmitt trigger

Apparatus:
Sr. Apparatus
No.

1. Analog board AB45

2. OPAMP-IC 741

3. Resistors

4. Dual Power supply

5. CRO

6. Function Generator

7. Multimeter

8. Patch cords/connectors

Theory:

Schmitt Trigger:

A Schmitt Trigger is a circuit which converts an irregular shaped waveform to a square wave or
pulse. This circuit is also called as a squaring circuit. A Schmitt trigger circuit is as shown in figure
below.

17 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Schmitt Trigger (a) Circuit diagram (b) Input-output waveform

The input voltage Vin triggers (changes the state of) output Vout every time exceeds certain
voltage levels called upper threshold Vut and lower threshold voltage Vlt as shown in figure.

These threshold voltages can be obtained by using the voltage divider R1-R2, where the voltage
across R1 is fed back to the (+) input. The voltage across R1 is a variable reference threshold
voltage that depends on the value and the polarity of the output voltage. When Vout = +Vsat, the
voltage across R1 is called the upper threshold voltage, Vut. The input voltage Vin must be
slightly more +ve than Vut in order to cause the output voltage Vout to switch from +Vsat to -
Vsat. As long as Vin < Vut, Vout is at +Vsat. Using the voltage divider rule,

𝑹𝟏
𝑽𝒖𝒕 = ∗ (+𝑽𝑺𝒂𝒕 )
𝑹𝟏 + 𝑹 𝟐

On the other hand, when Vo = -Vsat, the voltage

across R1 is referred to as lower threshold voltage,
Vlt. Vin must be slightly more negative than Vlt in
order to cause Vout to switch from -Vsat to +Vsat.
In other words, for Vin values greater than Vlt, Vout
is at -Vsat. Vlt is given by the following equation.

𝑹𝟏
𝑽𝒍𝒕 = ∗ (−𝑽𝑺𝒂𝒕 )
𝑹𝟏 + 𝑹𝟐

Thus if the threshold voltages Vut and Vlt are made larger than the input noise voltages, the
positive feedback will eliminate the false output transitions. Also, the positive feedback, because
of its regenerative action, will make Vout to switch faster between +Vsat and -Vsat.

The comparator with positive feedback is said to exhibit hysteresis, a dead zone. That is when
the input of the comparator exceeds Vut, its output switches from +Vsat to –Vsat and revert back

18 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 to its original state +Vsat, when the input goes below Vlt. The hysteresis voltage is, equal to the
difference between Vut and Vlt. Therefore, Vhy = Vut − Vlt

Circuit Diagram:

Procedure:
1. Connect the circuit as per circuit diagram.
2. Apply +Vcc = +12V and -VEE = -12V to OP-AMP.
3. Connect a 10Vp-p, 1 KHz sine wave signal to the inverting input of the Op-amp.
4. Choose the values of R = 300 ohm, R1 = 100 Ohm and R2 = 56 Ohm.
5. Observe the output waveform and input signal on CRO and Calculate the amplitude of the
square wave ±Vsat.
6. Calculate Vut ,Vlt and Vhy for Schmitt Trigger.
7. Repeat the steps for R = 200 ohm, R1 = 200 and R = 100 ohm, R1 = 300.
8. Compare the input and output waveforms.
9. Plot the charctersitics for Schmitt trigger.
Observation Table:

Input R R1 R2 Output Voltage On Off Time Total Time

Sr. Voltage V0 Time TOFF T = TON + TOFF
No. Vin Ω Ω Ω +Vsat -Vsat TON (mSec) (mSec)
(volt) (volt) (volt) (mSec)
1.

2.
3.

Calculation:

1. Upper Threshold Voltage

𝑹𝟏
𝑽𝒖𝒕 = ∗ (+𝑽𝑺𝒂𝒕 )
𝑹𝟏 + 𝑹𝟐

2. Lower Threshold Voltage

𝑹𝟏
𝑽𝒍𝒕 = ∗ (−𝑽𝑺𝒂𝒕 )
𝑹𝟏 + 𝑹 𝟐

19 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

3. Hysteresis Voltage Vhy = Vut - Vlt
Result Table:

Input R R1 R2 Output Voltage Upper Lower Hysteresis

Sr. Voltage V0 Threshold Threshold Voltage
No. Vin Ω Ω Ω +Vsat -Vsat Voltage Voltage Vhy (volt)
(volt) (volt) (volt) 𝑽𝒖𝒕 (volt) 𝑽𝒍𝒕 (volt)
1.

2.
3.

Graph: Draw the Input-Output waveform of Op-Amp as Schmitt Trigger.

Conclusion:

Questions:

1. Explain the Pin diagram of IC 741

2. What are features of IC 741?
What is difference between IC 741 and IC 324?

20 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Experiment no. 4

Aim: Study of various flip-flops and verification of truth table.

Apparatus:

Sr. No. Apparatus

1. Trainer Kit

2. Patch cords

3. Power Supply

Theory:

Flip-flops are binary cells capable of storing one bit of information. A Flip-flop has two outputs,
one for the normal value and one for complement value of the bit stored in it. A flip-flop circuit
can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed
by an input signal to switch states.

1. Clocked RS Flip-flop:

Clocked RS Flip-flop shown in figure 1 consists of two NOR Gates and two AND Gates. The input
S and R are set and reset input and output Q and Q' are normal and complement output. The input
CP is input for giving clock pulse. Flip-flop will change state only when CP goes from 0 to 1. The
output of two AND Gates remain at 0 as long as the clock pulse CP is 0, regardless of the S and R
input values. When the clock pulse goes to logic high level i.e. 1, information from the S and R is
allowed to reach the basic flip-flop. The set state is reached with S = 1, R = 0, and CP = 1. (for set
state, Q = 1 and for reset state, Q = O ) To change to the clear state, the inputs must be S = 0, R =
1, CP = 1. With both S = 1 and R = 1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of flip-flop is indeterminate, i.e., either
state may result, depending on whether the set or the reset input of the basic flip-flop remains a 1
longer before the transition to 0 at the end of the pulse.

Circuit/Logic Diagram:

RS Flip-flop:

21 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Truth Table:

Clock S Input R Input Qn+1

Pulse

0 0 No Change

0 1 0

1 0 1

1 1 Indeterminate (?)

2. D Flip-flop:

The logic symbol and characteristics table for D flip-flop is shown in figure 2. It has only one data
input (D) and clock input (CP). The outputs are labeled Q and Q'. The data (0 or 1) at the input 0
is delayed one clock pulse from getting to output Q. SD and CD are active low input (Negative
edge trigger) to set and reset the flip-flop i.e these inputs will be effective when logic 0 is applied.
A D Flipflop is a bistable circuit whose 0 input is transferred to the output after a clock pulse is
received. As long as the clock input is at 0, Gates 3, 4 have a 1 in their outputs, regardless of the
value of the other inputs. The D input is sampled during the occurrence of a clock pulse (CP=1).
If it is 1, the output of Gate 3 goes to 0, switching the flip-flop to the set state (unless it was already
set). If it is a 0 the output of Gate 4 goes to 0, switching the flip-flop to the clear state.

Truth Table:

Clock D Qn+1
Pulse Input

0 0

1 1

22 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

3. JK flip-flop :

A J-K flip-flop is refinement of R-S flip-flop in that the indeterminate state of the RS type is
defined in the JK type. Inputs J, K is used to set and clear the flip-flop. When both J, K are high
simultaneously, the flip-flop switches to its complement state, that is, if Q = 1, it switches to Q=
0, and vice versa. A CP signal which remains a 1 (While J=K = 1) after the outputs have been
complemented once will cause repeated and continuous transitions of the output. To avoid this
undesirable operation, the clock pulse must have a time duration which is shorter than the
propagation through the flip-flop.

The JK flip-flop shown above behaves like an R-S flip-flop, except when both J and K are 1, the
clock pulse is transmitted through one AND Gates only- the one whose input is connected to the
flip-flop output which is presently 1. Thus, if Q = 1, the output of the upper AND Gate become 1
upon application of a clock pulse, and the flip-flop is cleared. If Q = 0, the output of lower AND
Gate becomes a 1 and the flipflop is set. In either case, the output state of the flip-flop is
complemented.

Truth Table:

Clock J K Qn+1
Pulse Input Input

0 0 Qn

0 1 0

1 0 1

1 1 ̅𝒏
𝑸

4. T flip-flop:

The flip-flop is a single input version of the JK flip-flop. As shown below; the T flip-flop is
obtained from a JK type if both inputs are tied together. The designation T shows ability of flip-
flop to toggle. Regardless of the present state of the flip-flop, it assumes the complement state
when the clock pulse occurs while input T is logic1

23 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Truth Table:
Clock T Qn+1
Pulse Input

0 0

1 1

Procedure:

1. Connect +5V and ground to their indicated position on experiment board from external DC
power supply or from DC power block of Digital trainer kit.

2. Do the connection as per logic diagram of individual flip-flop.

3. Switch on the power supply.

4. Observe the output of Each flip flop as per their truth table.

Conclusion:

Questions:

1. What is 1 bit memory cell ?

2. What is difference between combinational and sequential circuit?

24 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 5

Aim: Study and plot of V-I characteristics of MOSFET.

Apparatus:

• MOSFET trainer Kit

• 2mm Patch Cords
• Mains Cord

Theory:

A MOSFET transistor is a semiconductor device which is widely used to switch the amplification
signals in the electronic devices. In MOSFETs, a voltage on the oxide-insulated gate electrode can
induce a conducting channel between the two other contacts called source and drain. The channel
can be of n-type or p-type and is accordingly called an nMOSFET or a pMOSFET (also commonly
nMOS, pMOS).

Types of MOSFET:

There are two basic types of MOSFETs

• Depletion MOSFETs, or D-MOSFETs, can be operated in either the depletion mode or the
enhancement mode.

• Enhancement MOSFETs, or E-MOSFETs, can be operated only in the enhancement mode.

Depletion MOSFET: Depletion-mode MOSFET is a piece of N-type material with a small P-type
region on the right, and on the left side of the channel a thin layer of silicon dioxide (insulator) is
deposited to create an insulated gate. The electrons flowing from source to drain must travel
through the channel between the gate and the substrate. The VDD supplies free electrons to flow
from the source to drain. These electrons flow through the narrow channel on the left of the P-type
substrate. (The gate voltage controls the width of the channel, and as a result it controls the flow
of the source, drain current of the device.)

Enhancement MOSFET (E-MOSFET) : An E-MOSFET does not have an N-channel between

the source and the drain. When the gate is positive it will attract free electrons into the P-type
region. The free electrons will combine with the holes located next to the silicon dioxide. At the
time that the gate becomes positive enough, all the holes touching the silicon dioxide are filled

25 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

with free electrons, and they begin to flow from the source to the drain of the device. This effect
is the same as creating a thin layer of N-type material next to the silicon dioxide that the gate is
connected to it. The thin conducting layer that is created is called the N-type inversion layer. While
the N-type inversion layer exists, free electrons can flow easily from source to drain. The amount
of the minimum gate voltage that is required to create the N-type inversion layer is called the
threshold voltage, (Vth).

Characteristics of an EMOSFET:

Drain Characteristics : Drain characteristics of an N-channel E-MOSFET are shown in figure.

The lowest curve is the VGST curve. When VGS is lesser than VGST, ID is approximately zero. When
VGS is greater than VGST, the device turns- on and the drain current ID is controlled by the gate
voltage. The characteristic curves have almost vertical and almost horizontal parts. The almost
vertical components of the curves correspond to the ohmic region, and the horizontal components
correspond to the constant current region. Thus E-MOSFET can be operated in either of these
regions i.e. it can be used as a variable-voltage resistor or as a constant current source.

26 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Transfer Characteristics:

Figure shows a typical transfer curve. The current IDSS at VGS <=0 is very small, being of the order
of a few nano-amperes. When the VGS is made positive, the drain current ID increases slowly at
first, and then much more rapidly with an increase in VGS. The equation for the transfer
characteristic does not obey equation. However it does follow a similar “square law type” of
relationship. The equation for the transfer characteristic of E-MOSFETs is given as

ID=K(VGS-VGST) 2

Circuit Diagram:

27 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Procedure: Drain Characteristics

1. Make the connections as shown in the above figure.

2. Connect the +35V DC supply to terminal 1 of Potentiometer P2 and terminal 3 to ground.
3. Now connect terminal 2 of Potentiometer P2 to of Resistance 100 Ω.
4. Now connect +ve terminal of Ammeter Resistance 100 Ω and –ve terminal to Drain (D) of
MOSFET to measure Drain Current.
5. Connect the +15V DC supply to terminal 1 of Potentiometer P1 and terminal 3 to ground.
6. Now connect terminal 2 of P1 to resistance 1KΩ.
7. Connect terminal of 1KΩ to gate (G) of MOSFET to give a supply of 15V for gate.
8. Connect Source (S) of MOSFET to Ground.
9. Connect +ve terminal of voltmeter to Gate (G) of MOSFET and -ve terminal to ground to
measure drain voltage VGS. Note: As Source (S) of MOSFET is already connected to ground
so we can connect –ve terminal of Voltmeter to ground or Source of MOSFET.
10.Rotate both potentiometers P1 and P2 in fully anti clockwise direction.
11.Connect the Power Supply.
12.Now switch on the power (press the rocker switch) from Power Supply box.
13.Now vary potentiometer P1 and set a value of gate voltage VGS at some constant value (5, 6,
7 & 8 V).
14.Now Remove Voltmeter between Gate (G) and ground, and connect between Drain (D) and
ground to measure Drain Voltage VDS.
15.Now vary the potentiometer P2 so as to increase the value of drain voltage VDS from zero to
30 V in step and measure the corresponding values of drain current ID for different constant
value of gate voltage VGS.
16.Note down the readings in given observation table.
17.Repeat the above procedure for different value of gate voltage VGS.
18.Plot a curve between drain voltage VDS and drain current ID, using suitable scale with the help
of observation table. This curve is the required drain characteristic.

Procedure: Transfer Characteristics

1. Connect the +15V DC supply to terminal 1 of Potentiometer P1 and terminal 3 to ground.

2. Now connect terminal 2 of Potentiometer P1 to resistance 1KΩ and terminal of Resistance
1KΩ to Gate (G) of MOSFET.
3. Connect Source (S) of MOSFET to Ground.
4. Select +35V variable DC power supply (by selecting the toggle switch at downward position)
and connect to terminal of Resistance 100Ω.
5. Now connect +ve terminal of Ammeter to terminal of Resistance 100Ω and –ve terminal to
Drain (D) of MOSFET to measure Drain Current ID (mA).
6. Rotate both of the potentiometer fully in anti-clockwise direction.
7. Connect +ve terminal of voltmeter to Drain (D) of MOSFET and -ve terminal to ground to
measure drain voltage VDS.
8. Now connect mains cord to the supply and Switch “On‟ the power supply.

28 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

9. Vary potentiometer and set a value of drain voltage VDS at some constant value (10, 20 &
28V).
10.Disconnect voltmeter between drain (D) and ground and connect between Gate (G) and
ground
11. Vary the potentiometer P2 so as to increase the value of gate voltage VGS from zero to -5 V
in step and measure the corresponding values of drain current ID for different constant value
of drain voltage VDS.
12.Note down the readings in given observation table.
13.Plot a curve between gate voltage VGS and drain current ID, using suitable scale with the help
of observation table. This curve is the required transfer characteristic.
14.Repeat the above procedure for different values of drain voltage VDS.
Observation Table:

1. Drain characteristics:

VGS = __________

Sr. No. Output Voltage VDS (volt) Output Drain current ID

(mA)

2. Transfer Characteristics:

VDS = __________

Sr. No. Output Voltage VGS (volt) Output Drain current ID

(mA)

29 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Graph:

1) Plot Drain characteristics

2) Plot Transfer characteristics

Conclusion:

Questions:

1. What are the types of FET?

2. What is difference between pitch off voltage and cut off voltage?

30 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Experiment No. 6

Title: Simulate frequency response of single stage CS amplifier and find the bandwidth.

Simulator: Multisim

Theory:

Write theory regrading JFET (CS) amplifier circuit and concept of frequency response.

Circuit Diagram: Draw circuit

31 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Design part on simulator workspace:

Frequency response curve:

32 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Observations Table:

Avmid = …………….

1. 50
Voltage Gain reduces by 50 % =10 log10 (100) = ………..

Lower cut off frequency = 𝑓𝐿 = − − − −

Higher cut off frequency = 𝑓𝐻 = − − − −

Band Width = B.W. = 𝑓𝐻 − 𝑓𝐿 = ---------

2. 60
Voltage Gain reduces by 60 % =10 log10 (100) = ………..

Lower cut off frequency = 𝑓𝐿 = − − − −

Higher cut off frequency = 𝑓𝐻 = − − − −

Band Width = B.W. = 𝑓𝐻 − 𝑓𝐿 = ---------

3. 70
Voltage Gain reduces by 70 % =10 log10 ( ) = ………..
100

Lower cut off frequency = 𝑓𝐿 = − − − −

Higher cut off frequency = 𝑓𝐻 = − − − −

Band Width = B.W. = 𝑓𝐻 − 𝑓𝐿 = ---------

Conclusion:

33 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 7 (a)

Aim: a) Study of 8 to 3 encoder circuit and 3 to 8 decoder circuit.

Objective:

Study of the following circuit and verifying their truth table

• 8 to 3 line Encoder Circuit

• 3 to 8 line Decoder Circuit.
Apparatus:

• Digital Trainer kit

• DC power supply
• 2mm Patch Cords
• Mains Cord

Theory:

An encoder has 2n input lines and n output lines. The output lines generate the binary code for the
2n input variables. Figure 1 shows 8 to 3 line encoder. It consists of eight inputs D0-D7, and three
outputs X, Y, Z that generates the corresponding binary number. X is MSB. It is constructed with
OR gates whose inputs can be determined from the truth table 1. The encoder in figure 1 assumes
that only one input line can be equal to 1 at any time. The circuit has eight inputs and could have
28= 256 possible input combinations. Only eight of these combinations have been considered. The
other input combinations are don't-care conditions.
A decoder is a digital function that produces a reverse operation from that of an encoder. A decoder
is a combinational circuit that converts binary information from n input lines to a maximum of 2n
unique output lines. Figure 2 shows 3 to 8 line decoder. The three inputs X, Y, Z are decoded in
to eight outputs D0-D7, each output representing one of the minterms of the three input variables.
The three inverters provide the complement of the inputs and each one of the eight AND gate
generates one of the minterms. Truth table 2 shows different input combinations for 3 to 8 line
decoder.

Procedure:
1. Connect + 5 V and ground to their indicated position on trainer kit from external DC power
supply.
2. Connect inputs D0-D7 as per Truth Table-1 to 8 to 3 line Encoder circuit as shown in figure
1.
3. Switch ‘On’ the power supply.
4. Observe output X, Y, Z on multimeter or on LED display and verify truth Table.
5. Connect inputs X, Y, Z as per truth table 2 to 3 to 8 line Decoder circuit of figure 2.
6. Observe output D0-D7 on multimeter or on LED display verify truth Table.
7. Repeat above steps for remaining input.

34 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Logic diagram:

For 8 to 3 Encoder Circuit:

Figure 1: 8 to 3 Encoder circuit

For 3 to 8 Decoder circuit:

Figure 2: 3 to 8 decoder circuit

35 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade
Truth Table:
(Logic 1 = +5 V & Logic 0=GND)

Table 1 for 8 to 3 Encoder circuit:

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Table 2 for 3 to 8 Decoder circuit:

Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Conclusion:

Questions:

1. Encoder and decoder are the types of which circuit?

2. Justify your above answer.

36 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 7 (b)

Aim: a) Study of 4 : 1 Multiplexer circuit and 1 : 4 Demultiplexer circuit.

Objective:

Study of the following circuit and verifying their truth table

• 4 : 1 Multiplexer circuit
• 1 : 4 Demultiplexer circuit.
Apparatus:

• Digital Trainer kit

• DC power supply
• 2mm Patch Cords
• Mains Cord
Theory:

Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. There are 2n input lines and n selection lines
whose bit combinations determine which input is selected.

A 4 to 1 Line Multiplexer is shown in figure 1. Each of the four input lines, D0 to D3 is applied to
one input of an AND gate. Selection lines S1, S0 are decoded to select a particular AND gate.
When S1, S0 = 10. The AND gate associated with input D2 has two of its inputs equal to 1 and
third input connected to D2. The other three AND gates have at least one input equal to 0, which
makes their output equal to 0. The OR- gate output is now equal to the value of D2, thus providing
a path from the selected input to the output. A multiplexer is also called a data selector, since it
selects one of many inputs and steers the binary information to the output line. Whenever any input
is selected which is in form of clock pulse all other inputs should be at zero level i.e. logic 0.

A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of a specific output line is controlled
by the bit values of n selection lines. 1 to 4 Line Demultiplexer is shown in figure 2 the single
input variable D has a path to all four outputs, but the input information is directed to only one of
the output lines, as specified by the binary value of the two selection lines S1 and S0. If the
selection lines S1, S0 = 1, 0 output D2 will be same as the input value D, provided D =0 while all
other outputs are maintained at 1. For D=1. All outputs are at high level. Clock pulse given to D
input can be obtained at output lines through selection lines S1 S0.

Table 1 and 2 shows Truth Table for 4 to 1 Line Multiplexer and 1 to 4 line demultiplexer.

37 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Procedure:
1. Connect +5 V and ground to their indicated position from external DC power supply.
2. Switch ON the power supply.
3. Connect inputs D0-D3 as per Truth Table1 to 4 to 1 line multiplexer. Circuit as shown in
figure 1.
4. Observe output, Z on multimeter or on LED display and verify truth Table.
5. Connect input D as per Truth Table 2 to 1 to 4 Line Demultiplexer circuit as shown in
figure 2.
6. Observe output D0-D3 on multimeter or on LED and verify truth Table.
Logic diagram:

4:1 Multiplexer circuit:

Figure 1 4: 1 Multiplexer circuit

Figure 2 1: 4 Demultiplexer circuit

38 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Truth Table:
(Logic 1 = +5 V & Logic 0=GND)

Table 1: Truth Table for 4 to 1 Line Multiplexer

Select Inputs Inputs Output

S0 S1 D0 D1 D2 D3 Z
0 0 1 0 1 0 1
0 1 1 0 1 0 0
1 0 1 0 1 0 1
1 1 1 0 1 0 0

Table 2: Truth Table for 1 to 4 Line Demultiplexer

Select Inputs Input Outputs

S0 S1 D D0 D1 D2 D3
0 0 0 0 1 1 1
0 1 0 1 0 1 1
1 0 0 1 1 0 1
1 1 0 1 1 1 0

Conclusion:

Questions:

1. What are the applications of multiplexer and demultiplexer ?

39 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 EXPERIMENT NO: 8

Aim: Study of Single-Phase Half wave and Full-wave bridge rectifier with RL load.

Objective: Find the parameters of rectifier

Outcome: Students will be able to find the parameters of HWR and FWR for RL load

Apparatus:

Sr. No. Apparatus

1. Rectifier Trainer Kit

2. Multimeter

3. Dual Race CRO

4. Patch cords

Theory:

The rectifier is a circuit or a component, which is used in the initial stages of a DC power supply.
The DC power supply is essential for the operation of many electronic devices and circuits. It
converts AC into DC, but the DC output is varying. One or more diodes are used for rectification.
There are several ways of connecting diodes to make a rectifier to convert AC to DC. The bridge
rectifier is the most important and it produces full-wave varying DC. There are three ways of
connecting the diodes which categorized the rectifier as shown below:

Half-wave Rectifier:

Figure (b) shows the half-wave rectifier circuit. It consists of a single diode in a series with a load
resistor. The input to the half-wave rectifier is an AC waveform as shown in Figure (a). The
working of a half-wave rectifier circuit may be studied by considering separately the positive and
negative half cycles of the AC input voltage.

During the positive half-cycle of the AC input voltage, the diode is forward biased so that the
circuit current flows and produces a voltage across the load resistor (RL). The voltage produced
across the load resistor has the same shape as that of the positive input half cycle of AC input
voltage as shown in Figure (c). During negative half-cycle, the diode is reverse biased and hence
it does not conduct. Thus, there is no current flow or voltage drop across load resistor (RL). It
means that only the positive half cycle of the AC input voltage is utilized for delivering AC power.

40 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Procedure:-

a. Half Wave Rectifier:-

1. Make the connections on the Rectifier Trainer.

2. Connect output of transformer (0-9 Vrms) to the input of half-wave rectifier.

3. Directly connect the output of rectifier to load.

4. Connect the mains cord to the Rectifier Trainer and switch on the mains supply.

5. Switch ‘On’ the power switch of the trainer.

6. Observe waveform on CRO.

7. Measure output frequency on CRO and you will observe that in half-wave

rectifier, the output frequency is same as that of input. fout = fin (50 Hz)

b. Full Wave Rectifier:-

1. Make the connections on the Rectifier Trainer.

2. Connect output of transformer (0-9 Vrms) to the input of full wave bridge rectifier.

3. Directly connect the output of rectifier to load.

4. Connect the mains cord to the rectifier Trainer and switch on the mains supply.

41 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

5. Switch ‘On’ the power switch of the trainer.

6. Observe waveform on CRO.

7. Measure output frequency on CRO and you will observe that in full-wave rectifier, the output
frequency is double that of input. fout =2 fin (100 Hz approximately)

Circuit Diagram:

Half Wave Rectifier:-

Full Wave Bridge Rectifier:-

Full-wave Bridge Rectifier

42 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Observation Table:-

Load Resistance = RL = _________

Sr. Type of Rectifier Input Voltage Output Output

no Vm (volts) Voltage Current

Vdc (volts) Idc (volts)

1 Half Wave Rectifier

2 Full Wave Rectifier

Calculation: -

Half Wave Rectifier

1. Calculation of Vdc:

With the help of CRO, Vm =______

Vm for half-wave rectifier, Vm =Vrms x 2

vm
Vdc = = 0.318V
π

To measure DC output voltage (Vdc), you can also connect Digital multimeter (DMM)
across load RL.

2. Calculation of I dc:
Vdc 𝑉𝑚 𝐼𝑚
Idc = 𝑅 ;Idc = = = 0.318Im
L 𝜋 𝜋

Full Wave Rectifier

1. Calculation of Vdc:

With the help of CRO, Vm. = ________

Vm for full-wave rectifier,Vm = Vrms x 2

2𝑉𝑚
Vdc = = 0.636Vm
𝜋

43 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 To measure DC output voltage (Vdc), you can also connect Digital Multimeter (DMM)
across load RL.

2. Calculation of I dc:
Vdc
Idc = RL where RL is the value of load resistor.

2𝑉𝑚 2𝐼𝑚
Idc = = = 0.636Im
𝜋𝑅𝐿 𝜋

Conclusion:-

Questions:

1. What are the different types of rectifiers?

2. Compare different parameters for HWR and FWR

44 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra Experiments

Extra experiment No.: 1

Aim: Study of Op-amp as sine, and triangular wave generator

Objectives:
Study of Op-amp as sine and triangular wave generator

Outcomes:

Students will able to understand: Study of Op-amp as sine and triangular wave generator

Apparatus:
Sr. No. Apparatus

1. Analog Board

2. Oscilloscope

3. Dual Power supply

4. Multimeter

5. Connecting Links/Wires

Theory:
Sine Wave Generator:

The sine wave is one of the most fundamental waveforms because we can express any
waveform in terms of Fourier combination of basic sine wave.

There are two types of oscillators as follows:

1. RC phase shift oscillator.

2. Wien bridge oscillator.

Oscillator:-

Oscillator is an amplifier which does not have any ac input & which operates on principal of
positive feedback to generate an ac signal. Oscillator consists of an amplifier & phase shift
network. For sustained oscillator Barkhausen criterion must be satisfied.

45 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Barkhausen Criterion:-

It states that the loop gain Aβ should be greater than or equal to 1 & phase shift around the loop
should be equal to zero at frequency of oscillations.

RC Network For Phase Shift Oscillator:-

For the RC phase shift oscillator we use three identical basic RC phase shifting network in
cascade. Sometimes this is also called as ladder network. “It produces a phase shift of 180ᵒ
precisely only at one particular frequency which is the frequency of operation of an oscillator”.

Fig: 1.1 RC phase shift network.

Operation:

OP -AMP is used as an Inverting amplifier. Therefore it introduces a phase shift of 180ᵒ

between input & output. The output of Inverting amplifier is applied at the input of RC phase shift
network. This feedback network attenuates the signal at its input & feed it to the amplifier input.
The level of attenuation is decided by the feedback factor β.

The gain of Inverting amplifier is decided by the value R1 & Rf. This gain adjusted such
a way that the product Aβ is slightly greater than 1 i.e. |𝑨𝜷| ≥ 𝟏.

46 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 It can be proved that the value of feedback factor β at the frequency of oscillations is β =
1 /29 & for sustained oscillations Loop gain |𝑨𝜷| ≥ 𝟏.Therefore the gain of inverting
amplifier ( A) should be greater or equal to 29.

Gain of inverting amplifier is given by, A = Rf / R1

Rf / R1 ≥ 29 OR R f ≥ 29 R 1.This value of Rf & R1 will insure sustained oscillations.

The expression for frequency of oscillations of an RC phase shift oscillator is given by

𝟏
𝒇𝒐 =
𝟐𝝅√𝟐𝑵 𝑹𝑪

Where N = No. of RC n/w stages, therefore N = 3

𝟏
𝒇𝒐 =
𝟐𝝅√𝟔 𝑹𝑪

𝒇𝒐 depends only on the components of feedback network (RC phase shift oscillator).

The RC phase shift oscillator generally used over the frequency range of 100 Hz to 100 KHz.

Triangular Wave Generator:

Fig. (a)

Figure (a) shows practical triangular waveform generator using comparator and integrator
connected one after another. It consists of a comparator (A) and an integrator (B). The output of
comparator A is a square wave of amplitude ± Vsat and is applied to the inverting (—) input
terminal of the integrator B. The output of integrator is a triangular wave and it is feedback as
input to the comparator A through a voltage divider R2 R3.

47 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

To understand circuit operation, assume that the output of comparator A is at + Vsat. This forces
a constant current (+Vsat /R1) through C to give a negative going ramp at the output of the
integrator, as shown in the Fig. (b). Therefore, one end of voltage divider is at a voltage +Vsat
and the other at the negative going ramp. When the negative going ramp reaches a certain value
— Vramp, the effective voltage at point P becomes slightly below 0 V.

As a result, the output of comparator A switches from positive saturation to negative saturation
(— Vsat). This forces a reverse constant current (right to left) through C to give a positive going
ramp at the output of the integrator, as shown in the Fig. (b). When positive going ramp reaches
+ Vramp, the effective voltage at point p becomes slightly above 0V. As a result, the output of
comparator A switches from negative saturation to positive saturation (+Vsat). The sequence
then repeats to give triangular wave at the output of integrator B.

Fig. (b)

The frequency of oscillation can be given as,

𝑹𝟑
𝒇𝒐 =
𝟒𝑹𝟏 𝑪𝟏 𝑹𝟐

Circuit Diagram:

Sine Wave Generator:

48 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Triangular Wave Generator:

Procedure:

A. Sine Wave Generator

1. Connect the circuit as shown in circuit diagram.
2. Apply ± Vcc = ± 12V to OP-AMP.
3. Observe the waveform on CRO at the output terminal of OP- AMP.

B. Triangular Wave Generator

1. Connect the circuit as per circuit diagram

2. Select properly the values of R, R1 ,R2, & C1
3. Apply the supply voltage of ± 12V
4. Observe the waveform on the CRO as a triangular wave.

Conclusion:

Questions:

1. State the Barkhausen criteria.

2. What is formula for frequency of Sine wave generator and triangular wave
generator?

49 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.: 2

Aim: Study of Instrumentation amplifier using three Op-amp, CMRR measurement

Objectives:
• Study the operation of Instrumentation amplifier using Op-amp
• Measure the CMR of Instrumentation amplifier

Outcomes:

Students will able to understand

• Operation of Instrumentation amplifier using Op-amp
• Measure the CMR of Instrumentation amplifier

Apparatus:
Sr. No. Apparatus

1. Analog kit - Instrumentation amplifier

2. DC Power Supplies +12V, -12V, +5V

3. Multimeter

4. Patch cords/connectors

Theory:

The Op-Amp became familiar to the individuals working in process control and instrumentation
technology. There are many instances in which the difference between two voltages needs to be
conditioned. An ideal differential amplifier provides an output voltage with respect to ground that
is some gain times the difference between two input voltages.

Vout = A (Va – Vb)

Where A is the differential gain and both Va and Vb are voltages with respect to ground. Such an
amplifier plays an important role in instrumentation and measurement.

Common Mode Rejection Ratio:

To define the degree to which a differential amplifier approaches the ideal, we use the term
common mode rejection. When the same input voltage is applied to both input terminals of an op-
amp, the Op-Amp is said to be operating in a common mode configuration. The common mode
rejection ratio (CMRR) of a differential amplifier is defined as the ratio of the differential gain to
the common mode gain. The common mode rejection (CMR) is the CMRR expressed in dB,

50 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 𝐴𝐷
𝐶𝑀𝑅𝑅 = CMR = 20 log10 (CMRR)
𝐴𝐶𝑀

The input voltage applied is common to both the inputs; it is referred to as a common mode
voltage VCM. Because ideally an op-amp amplifies only differential input voltages, no common
mode output voltage VOCMshould appear at the output. However, due to imperfections within
an actual op- amp, some common mode voltage VOCM appears to the output. Therefore, in
practice the ratio of the output common mode voltage VOCM to the input common mode voltage
VCM is called the common mode voltage gain ACM.

𝑉𝑂𝐶𝑀
𝐴𝐶𝑀 =
𝑉𝐶𝑀

The higher the value of CMRR, the better is the matching between two input terminals and the
smaller is the output common mode voltage. Clearly, the larger these number, the better the
differential amplifier. Typical values of CMR range from 60 to 100 dB.

Instrumentation Amplifier:

An Instrumentation Amplifier is a differential op- amp circuit providing high input impedances
with ease of gain adjustment through the variation of a single resistor. They find a host of
applications in process measurement systems, principally as the initial stage of application for
bridge circuits. Figure shows the circuit of Instrumentation Amplifier.

This circuit allows for selection of gain, within certain limits, by adjustment of a single resistor,
RG. It can be shown that the CMR of this circuit, although still dependent on careful matching of
the differential amplifier resistors, does not depend on matching of the two R1’s. The transfer
function of this amplifier is given by

2𝑅1 𝑅
𝑉𝑜𝑢𝑡 = (1 + )(𝑅3)(𝑉2 − 𝑉1)
𝑅𝐺 2

51 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

This intimidating circuit is constructed from a buffered differential amplifier stage with three
new resistors linking the two buffered circuits together. Consider all resistors to be of equal value
except for RG. The negative feedback of upper left Op-amp causes voltage at point 1 to be equal
to V1. Likewise, the voltage at point 2 is held to a value equal to V2. This establishes a voltage
drop across RG equal to the voltage difference between V1 and V2. That voltage drop causes a
current through RG and since the feedback loops of the two input op-amps draw no current, that
same amount of current through RG must be going through the two R1 resistors above and

below it. This produces a voltage drop between points 3 and 4 equal to:

2𝑅1
𝑉3−4 = (1 + )(𝑉2 − 𝑉1 )
𝑅𝐺

The regular differential amplifier on the right hand side of the circuit then takes this voltage drop
between points 3 and 4, and amplifies it by a gain of 1 (assuming again that all resistors are of
equal value). Through this looks like a cumbersome way to build a differential amplifier, it has
the distinct advantages of possessing extremely high input impedance on the V1 and V2 inputs,
and adjustable gain that can be set by a single resistor. Manipulating the above formula a bit, we
have a general expression for overall voltage gain in the instrumentation amplifier.

2𝑅1
𝐴𝑉 = (1 + )
𝑅𝐺

The input impedance is very high, and the output impedance is very low. They can thus ensure a
high CMR.

Circuit Diagram:

52 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Procedure:

A] For Instrumentation Amplifier

1. Connect +12V and -12V DC Power Supplies at their indicated position

2. Apply + 2V DC signal at socket ‘V1’
3. Apply + 5V DC signal at socket ‘V2’.
4. Connect patch cord between‘d’& ‘h’ socket and also ‘a’ & ‘e’ socket as shown in circuit
diagram.
5. Connect patch cord between ‘g’ & ‘i’ socket and also ‘c’ & ‘f’ socket.
6. Rotate the gain adjustment potentiometer and set value of RG equal to 100K between ‘TP1’
and ‘TP2’ by digital multimeter.
7. Switch on the Power Supply.
8. Connect voltmeter between VO and ground to measure output voltage.
9. Measure theoretical value of output voltage by using formula
𝑅3
𝑉𝑜𝑢𝑡 = (𝑉 − 𝑉1 )
𝑅2 2

10. Check theoretical and practical value of output voltage is same.

11. Disconnect +2V DC signal from socket ‘V1’ and connect +3V DC signal at
socket ‘V1’ and follow the procedure from step 5.

B] For Calculation of CMRR

1. Connect +12V and -12V DC Power Supplies at their indicated position from external source
2. Common Mode Gain:

a) Apply + 2V DC signal at socket ‘V1’ and apply + 2V DC signal at socket ‘V2’

b) Connect patch cord between ‘a’ and ‘b’ socket.
c) Connect patch cord between‘d’ & ‘h’ socket and also ‘g’ & ‘i' socket.
d) Rotate the gain adjustment potentiometer and set value of RG equal to 100K
between ‘TP1’ and ‘TP2’ by digital multimeter.
e) Switch on the Power Supply.
f) Connect voltmeter between VO and ground to measure output voltage. This is the
output in the Common mode configuration. (VOCM)
3. Differential Mode Gain:
a) Apply + 3V DC signal at socket ‘V1’ and apply + 5V DC signal at socket ‘V2’
b) Connect voltmeter between Vo and ground to measure output voltage. This is the
output of the differential mode configuration. (VOD)
4. Calculate CMRR by using equation
𝑉𝑂𝐷
𝐶𝑀𝑅𝑅 = 20 𝑙𝑜𝑔10 ( )dB
𝑉𝑂𝐶𝑀

5. Repeat the steps for different value of RG = 50K.

53 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Observation Table :

A] For Instrumentation Amplifier

Obs. No. Input Voltage V1 Input Voltage Output Voltage VO (volts)

(volts) V2 (volts)
Observed Calculated
1
2

B] For Calculation of CMRR

Value of Gain Differential Mode Common Mode 𝑪𝑴𝑹𝑹 =

Resistance RG 𝑽
Input Output Input Output 𝟐𝟎 𝒍𝒐𝒈𝟏𝟎 (𝑽 𝑶𝑫 )
(kohm) 𝑶𝑪𝑴
Voltage Voltage Voltage Voltage (dB)
V2 – V1 VOD V2 = V1 VOD
(volts) (volts) (volts) (volts)

Conclusion:

Questions:
1. Explain the concept of CMRR
2. Explain Op-Amp as instrumentation Amplifier.

54 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.:3

Title: Design, build and test Comparator and Schmitt trigger. (Simulator based)

Simulator: Multisim

Circuit Diagram: Draw circuit diagram

Theory : Explain op-amp as a comparator and Schmitt trigger

Procedure:

Part1 :op-amp as a comparator.

1.Design comparator in simulator editor Window

Vin = 10 Vpp, 1kHZ
Vref = 1 V ,2 V , -1 V ,-2 V
VCC = +12 V, VEE = -VEE
R1 = R = 10 kOhm

2.Observe input and output waveforms on Oscilloscope

3. Take the readings of Output Waveform from Oscilloscope.

Part2 : op-amp as a Schmitt Trigger

1.Design comparator with feedback (Rf =10 kOhm) in simulator editor Window
Vin = 10 Vpp, 1kHZ
VCC = +12 V, VEE = -VEE

55 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 2.Observe input and output waveforms on Oscilloscope
3. Take the readings of Output Waveform from Oscilloscope.
4. Take the values of VLT and VUT values.
5.Observe hysteresis on Oscilloscope and calculate Hysteresis voltage.

Observations:

1 )Op-amp as a Comparator

(screenshot of comparator circuit and its Output)

56 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Sr. No. Vin Vref +Vsat -Vsat

1 10 V p-p +1 V

2 10 V p-p -1V

3 10 V p-p +2 V

4 10 V p-p -2V

2) Op-amp as a Schmitt Trigger

Sr. No. Vin Vlt Vut Vhys +Vsat -Vsat

1 10 V p-p

Conclusion:

57 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.:4

Title: Design of Summing, scaling, and averaging amplifier.

Simulator: Multisim

Theory :

Part 1 : Op-amp as a Summing amplifier.

In this simple summing amplifier circuit, the output voltage, ( Vout ) now becomes proportional
to the sum of the input voltages, V1, V2, V3, etc. Then we can modify the original equation for
the inverting amplifier to take account of these new inputs thus:

However, if all the input impedances, ( RIN ) are equal in value, we can simplify the above
equation to give an output voltage of:

58 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

summing amplifier formula:

𝑅𝑓
𝑉𝑜𝑢𝑡 = − (𝑉 + 𝑉2 + 𝑉3 )
𝑅𝑖𝑛 1
Note that when the summing point is connected to the inverting input of the op-amp the circuit
will produce the negative sum of any number of input voltages. Likewise, when the summing
point is connected to the non-inverting input of the op-amp, it will produce the positive sum of
the input voltages.

Part 2 : Op-amp as a Scaling amplifier

A scaling amplifier is a special type of summing amplifier with the output signaldetermined by
multiplying each input signal by a different factor (determined by the ratio of the input-signal
resistor and feedback resistor) and then adding the products.

𝑅𝑓 𝑅𝑓 𝑅𝑓
≠ ≠
𝑅1 𝑅2 𝑅3
𝑅𝑓 𝑅𝑓 𝑅𝑓
𝑉𝑜𝑢𝑡 = −( × 𝑉1 + × 𝑉2 + × 𝑉3)
𝑅1 𝑅2 𝑅3

Part 3 : Op-amp as a Averaging amplifier:

𝑅𝑓 1
All input resistances are equal and 𝑅𝑖𝑛 = = where n = number of inputs.
𝑛

R1 =R2 =R3 = Rin

𝑅𝑓
𝑉𝑜𝑢𝑡 = − (𝑉 + 𝑉2 + 𝑉3 )
𝑅𝑖𝑛 1
1
𝑉𝑜𝑢𝑡 = − (𝑉1 + 𝑉2 + 𝑉3 )
𝑛
Circuit Diagram: Draw circuit diagram

59 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Observations :

1) Inverting Summing Amplifier

V1 = ____, V2 = ________, V3 = ______,

R1 =R2 =R3 = _________ ; Rf = ______

𝑅𝑓
𝑉𝑜𝑢𝑡 = − (𝑉1 + 𝑉2 + 𝑉2 ) = __________.
𝑅𝑖𝑛

2) Inverting scaling Amplifier

V1 = ____, V2 = ________, V3 = ______,

R1 =------,R2 =-------, R3 = _________ ; Rf = ______

𝑅𝑓 𝑅𝑓 𝑅𝑓
𝑉𝑜𝑢𝑡 = − (𝑅1 × 𝑉1 + 𝑅2 × 𝑉2 + 𝑅3 × 𝑉3)= __________.

60 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 3) Inverting averaging Amplifier

V1 = ____, V2 = ________, V3 = ______,

R1 =R2 =R3 = _________ ; Rf = ______
𝑅𝑓 1
=
𝑅𝑖𝑛 𝑛
𝑅𝑓
𝑉𝑜𝑢𝑡 = − 𝑅𝑖𝑛 (𝑉1 + 𝑉2 + 𝑉2 ) = __________.

Conclusion:

61 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.:5

Title : Build and test single stage CS amplifier using FET. Calculate Ri, Ro and Av.

Simulator: Multisim

Design Part:

Observations Table :

62 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Calculations:

Conclusion:

Extra experiment No. : 6

63 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade
Aim: Study and verify shift register operation

Objectives:
• Study the operation of Serial In Serial Out Shift register
• Study the operation of Serial In Parallel Out Shift register
• Study the operation of Parallel In Serial Out Shift register
• Study the operation of Parallel In Parallel Out Shift register

Outcomes:

Students will able to understand

• Operation of 4 modes of shift register.

Apparatus:
Sr. No. Apparatus

1. Shift Register Trainer kit

2. Power supply

3. Connecting Links/Wires

Theory:
A register is a group of binary storage cells suitable for holding binary information. A
group of flip-flops constitute a register. Since each flip-flop is a binary cell capable of storing one
bit of information, a n-bit register has a group of n flip-flops and is capable of storing any binary
information containing n bits.

A register capable of shifting its binary information either to the right or to the left is called
a shift register. The logical configuration of a shift register consists of a chain of flip-flops
connected in cascade, with the output of one flip-flop connected to the input of next flip-flop. Here,
all the flip-flops receive a common clock pulse, which causes the data bits to shift from one stage
to the next.

Classification of Shift Registers: -

Shift registers are classified based on modes of operation as :

1. Serial in-serial out shift register

2. Serial in-parallel out shift register

3. Parallel in-serial out shift register

4. Parallel in-parallel out

64 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade
1. Serial in-serial out shift register :

A basic 4-bit shift register can be constructed using four D flip-flops, as shown in above figure.
The register is first cleared, forcing all four outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop from the left (FF0). During each clock pulse, one
bit is transmitted from left to right. The least significant bit (LSB) of the data is the first to be
shifted through the registers i.e. from FF0 to FF3.

2. Serial in-parallel out shift register :

In this kind of register, data bits are entered serially in the same manner as discussed above. The
difference is the way in which the data bits are taken out of the register. Once the data are stored,
each bit appears on its respective output line, and all bits are available simultaneously. A
construction of a 4-bit serial in parallel out register is shown below.

The Q output of a given flip-flop is connected to the D input of the next flip-flop to its right. The
serial input determines what goes into the leftmost flip-flop during the shift. Each positive edge of
the clock pulse transition shifts the contents of the register one bit position to the right. The serial
output is taken from the output of rightmost flip-flop prior to the application of clock pulse. There
are four parallel outputs Q0-Q3 with Q3 as LSB. The CLEAR input is an active low input to the
flip-flops. It resets or clears the outputs Q0-Q3 when low.

3. Parallel in-serial out shift register :

A 4-bit parallel in serial out shift register is shown below. D0, D1, D2 and D3 are the parallel
inputs, where D0 is the most significant bit and D3 is the least significant bit. To load or
write data, the mode control line is taken LOW and the data is clocked in. The data can be

65 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 shifted when the mode control line is HIGH as SHIFT is active high. The register performs
right shift operation on the application of a clock pulse.

4. Parallel in-parallel out :

The following circuit is a four-bit parallel in parallel out shift register constructed by D flip-
flops. In case of parallel in parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits.

In the above figure, the D's are the parallel inputs and the Q's are the parallel outputs. Once the
register is clocked, all the data at the D inputs appear at the corresponding Q outputs
simultaneously. And with help various control lines can be shifted to either right or left direction
i.e. either from FF0 to FF3 or vice versa.

66 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Circuit Diagram:

A. Serial In Serial Out (SISO) shift register

B. Serial In Parallel Out (SIPO) shift register

C. Parallel In Serial Out (PISO) shift register:

D. Parallel In Parallel Out (PIPO) shift register:

67 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Procedure:

1. Do all the connections as shown in the circuit diagram.

2. Reset all the three D flip flops by connecting CLEAR pin of each D flip flop to LOW input.
3. Connect CLEAR pin to HIGH input to make it inactive.

A. Serial In Serial Out:

For Serial In :-Connect D input of the first D flip flop to the LSB (least significant bit)of the data
to be shifted. Apply clock pulses for the second ,third and fourth bit (i.e. MSB) of the data. Data
is loaded serially at this step.

For Serial Out:- Apply clock pulses for taking out data serially.

B. Serial In Parallel Out :

For Serial In :- Connect D input of the first D flip flop to the LSB (least significant bit)of the data
to be shifted. Apply clock pulses for the second ,third and fourth bit (i.e. MSB) of the data. Data
is loaded serially at this step.
For Parallel Out:- Apply only one clock pulse for taking out data in parallel way

C. Parallel In Serial Out :

For Parallel In :-Connect D input of individual D flip flop to load all flip flop with desired input
simultaneously at only one clock pulse. Apply CLOCK PULSE. Data is loaded in parallel way at
this step.

For Serial Out:- Apply clock pulses for taking out data serially
D. Parallel In Parallel Out :
For Parallel In :- Connect D input of individual D flip flop to load all flip flop with desired input
simultaneously at only one clock pulse. Apply CLOCK PULSE. Data is loaded in parallel way at

68 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

this step.
For Parallel Out:- Apply only one clock pulse for taking out data in parallel way
Observation Table:
A. Serial In Serial Out: Preset = Clear = 1

CLOCK
PULSE D0 Q3
NO.

B. Serial In Parallel Out: Clear = 1

CLOCK
PULSE D0 Q0 Q1 Q2 Q3
NO.

69 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

C. Parallel In Serial Out: CLK INH = 0 ;SHIFT/LOAD = 0 (for Load); SHIFT/LOAD = 1(for
Shift)

CLOCK
PULSE SHIFT/LOAD D0 D1 D2 D3 Q3
NO.

1 0

2 1

3 1

4 1

D. Parallel In Parallel Out: Clear = 1

MODE S0 S1

Parallel Load 1 1

Shift left 0 1

Shift Right 1 0

Inhibit 0 0

CLOCK
PULSE S0 S1 D0 D1 D2 D3 Q0 Q1 Q2 Q3
NO.

Conclusion:
Questions:
1. What do you mean by register?
2. What do you mean by universal register?
3. What do you mean by bidirectional and unidirectional shift register?

70 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.: 7

Aim: Study of up-down counters

Apparatus:

Sr. Apparatus
No.

1. 4 bit Synchronous up/down counter kit

2. Power supply

3. Connecting Links/Wires

Theory:

4 Bit Synchronous Counter: - It consists of 4 flip flops (they may be positive or negative edge
triggered JK or T flip flop). Let us assume its construction using 4 positive edge triggered JK flip
flops. 4 bit Synchronous counter consists of 16 states in its count sequence i.e. it counts from
binary equivalent of 0 to binary equivalent of 15. Being Synchronous counter all 4 JK flip flops in
it will be triggered simultaneously by clock pulse.

4 Bit Synchronous Up Counter: -It counts in the up direction i. e. it counts from binary equivalent
of 0 to binary equivalent of 15 after application of clock pulses.

Circuit Diagram:

71 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Up Count sequence Down Count Sequence

Data Input -a,b,c,d = Logic 1 Data Input -a,b,c,d = Logic 1

̅̅̅̅̅̅̅̅̅̅ = 𝑳𝒐𝒈𝒊𝒄 𝟎
𝑪𝑻𝑬𝑵 ̅̅̅̅̅̅̅̅̅̅ = 𝑳𝒐𝒈𝒊𝒄 𝟎
𝑪𝑻𝑬𝑵

̅̅̅̅̅̅̅
𝑳𝒐𝒂𝒅 = 𝑳𝒐𝒈𝒊𝒄 𝟏 ̅̅̅̅̅̅̅
𝑳𝒐𝒂𝒅 = 𝑳𝒐𝒈𝒊𝒄 𝟏

̅ = 𝑳𝒐𝒈𝒊𝒄 ____
𝑼/𝑫 ̅ = 𝑳𝒐𝒈𝒊𝒄 _____
𝑼/𝑫

Procedure:

1. Make power on to unit.

2. Connect clock at the clock input.
3. Set the required data (i.e. OOOO) at data inputs A, B, C, D and make LOAD input low.
Data will get loaded independent of the leve1 of the clock (as it is asynchronous active
low input pin). After that make LO.{D pin inactive by connecting it to high input.
̅̅̅̅̅̅̅̅̅ pin to low input for 4 bit synchronous up counter operation &
4. Connect UP/𝐷𝑂𝑊𝑁
̅̅̅̅̅̅̅̅̅ pin to high input for 4 bit synchronous down counter operation.
Connect UP/𝐷𝑂𝑊𝑁
5. To obtain count sequence make enable input 1ow (as it is a active low asynchronous
input)
6. Apply clock pulses and observe the output at QA, QB, QC, QD.

Observation Table:

For Up count Sequence For Down count Sequence

Clock Qd Qc Qb Qa Clock Qd Qc Qb Qa
Pulse (MSB) (LSB) Pulse (MSB) (LSB)

1. 1.

2. 2.

3. 3.

4. 4.

72 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 5. 5.

6. 6.

7. 7.

8. 8.

9. 9.

10. 10.

11. 11.

12. 12.

13. 13.

14. 14.

15. 15.

Conclusion:

73 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Extra experiment No.8

Title: Study of IC-555 applications- astable and monostable multivibrator

Objectives:
• Study of IC-555 applications
1) Monostable multivibrator
2) Astable multivibrator
Outcomes:

Students will able to understand: IC 555 applications as

1) Monostable multivibrator
2) Astable multivibrator

Apparatus:
Sr. No. Apparatus

1. Analog trainer kit

2. Oscilloscope

3. Dual Power supply

4. Multimeter

5. Function Generator

6. Connecting Links/Wires

Theory:

1. Monostable Multivibrator:

A monostable multivibrator, often called as one shot multivibrator. It is a pulse generating

circuit in which the duration of pulse is determined by RC network connected externally
to the 555 timer IC.
In a stable or standby state the output is zero or at a low logic level. When an external
trigger pulse is applied, the output is forced to go high. The time output remains high is
determined by the external RC network connected to the timer. At the end of timing Interval
the output automatically reverse back to its logic low level state. The output remains low
until the trigger pulse is again applied. This cycle is repeated. The monostable circuit has
only one stable state (output low), hence the name monostable.

74 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 Figure1 (a) Circuit diagram Figure1 (b) Waveforms

2. Astable Multivibrator:

An astable multivibrator, often called as a free running multivibrator, is a rectangular wave

generating circuit. This circuit does not require an external trigger to change state of output,
hence name is a stable multivibrator. However, time during which the o/p is either high or low
is determined by the resistor & a capacitor which are externally connected to the 555 timer.

75 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

Circuit Diagram:

1. Monostable Multivibrator:

2. Astable Multivibrator:

Procedure:

1. Monostable Multivibrator:

1. Connect power supply + 5V.

76 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 2. Do the connections as per circuit diagram.
3. Keep the pot (R2 1M) to fully anticlockwise direction.

4. Apply a pulse signal of 5Vpp and 1 KHz (keep duty cycle of pulse 50%) at pin 2

of IC 555. Observe the same on oscilloscope CHI.

5. Connect pin 3 of IC55 i.e. output socket to the oscilloscope CHII.

6. Vary the pot and observe the variation of output pulse duty cycle with the

change in resistance R (where, R=R1+R2).

7. For any value of R measure the ON time of output pulse.

8. Calculate the same by following equation for theoretically calculating the output

pulse ‘On’ time. TP = 1.1 * RC1

Note: For calculating the value of R, disconnect the +5V supply and connection

between point a and b. Connect ohmmeter between point a and TP1. The ohmmeter will
read the value of R.

9. Verify theoretical and practical values of TP.

Note: The two values of TP (theoretical and practical values) will match only for

time for which input pulse is High i.e. only for ‘On’ 'time of input pulse. To

verify this vary the duty cycle of input signal and check the output pulse duty

cycle by varying R (R=R1+R2).

10. Repeat above procedure for different values of R.

2. Astable Multivibrator:

1. Connect power supply +5V.

2. Keep the pot (R2 1M) to fully anticlockwise direction.
3. Connect pin 3 of IC55 i.e. output socket to the oscilloscope.
4. Vary the pot and observe the variation of output signal’s frequency with the
change in resistance R (where, R=R1+R2).
5. To verify the above calculate the frequency of output signal using following
Equation
1.44
𝑓𝑂𝑢𝑡 =
(R1 + 2R3)C1
Note: For calculating the value of R, disconnect the +5V supply and connection
between point a and b. Connect ohmmeter between point a and TP1. The ohmmeter will
read the value of R.

77 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade

 6. Trace the waveforms of the voltage across capacitor C1
7. Repeat above procedure for different values of R.

Observation Table:

1. Monostable Multivibrator:

Sr. No. Value of Value TON

of
R= R1+R2 (mSec)
C1
(Ω ) Observed Calculated
(µF ) from CRO
TON = 1.1 RC1

2. Astable Multivibrator:

Sr. Value of Value Value TON TOFF

No. of of
R= (mSec) (mSec)
R1+R2 R3 C1
Observed Calculated Observed Calculated
(Ω ) (Ω ) (µF ) from from
CRO TON = 0.69(R + R3)C1
CRO TOFF = 0.69 R3C1

Calculations:

1. Monostable Multivibrator: TON = 1.1 RC1

2. Astable Multivibrator:
TON = 0.69(R + R3)C1
TOFF = 0.69 R3C1

Total time = T = TON + TOFF

Conclusion:

Questions: 1. What is the difference between monostable and astable multivibrator.

2. What is formula of frequency for astable multivibrator?

****************************************************************************

78 | P a g e Department of Electrical Engineering Prepared by Mrs. M. A. Kanawade