COUNTERS

* Counters are important digital electronic circuits.

* They are Sequential logic circuits because timing is
obviously important and they need a memory
characteristic.
* Digital counters have the following important
characteristics,
1. Maximum number of count
2. Up-Down Count
3. Asynchronous or Synchronous Operation
4. Free-Running or Self-Stopping

1
 Classification
• Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent
state flip-flops

• Synchronous counter – all state bits change under control of a single clock (All F/F
change state simultaneously)

• Decade counter – counts through ten states per stage

• Up/down counter – counts both up and down, under command of a control input

• Ring counter – formed by a shift register with feedback connection in a ring

• Johnson counter – a twisted ring counter

• Cascaded counter and

• Modulus counter.
Classifications of Counters

Asynchronous Counters

 Only the first flip-flop is clocked by an external clock. All subsequent

flip-flops are clocked by the output of the preceding flip-flop.

 Asynchronous counters are slower than synchronous counters

because of the delay in the transmission of the pulses from flip-flop

to flip-flop.

 Asynchronous counters are also called ripple-counters because of the

way the clock pulse ripples it way through the flip-flops.

Classifications of Counters

Synchronous Counters

 All flip-flops are clocked simultaneously by an external clock.

 Synchronous counters are faster than asynchronous counters

because of the simultaneous clocking.

 Synchronous counters are an example of state machine design

because they have a set of states and a set of transition rules for
moving between those states after each clocked event.
 Asynchronous/Ripple Counter

• Asynchronous counter are commonly referred to as ripple counter

because the effect of the input clock pulse is first “felt” by first flip-flop
(FF0).

• Cannot get to the second flip-flop (FF1) immediately because of the

propagation delay through FF0.

• So the effect of an input clock pulse “ripples” through the counter,

taking some time, due to propagation delays, to reach the last flip-flop.

Only the first FF receive clock pulse from the source ( clock genarator),
others FFs receive clock pulse from either Q or Q’ of prior FF
5
 Asynchronous/Ripple Counter
Propagation delays in a 3-bit asynchronous (ripple-clocked) binary
counter.

6
 Asynchronous/Ripple Counter
Three-bit asynchronous binary counter and its timing diagram for one
cycle.
Clk Q2 Q1 Q0
pulse

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 0 0 0
(REPEAT
)

RIPPLE COUNTER UP – PGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE
FROM Q’
 Asynchronous/Ripple Counter
Four-bit asynchronous binary counter and its timing diagram.

CLK Q3 Q2 Q1 Q0
PLUSE

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
REPEAT

RIPPLE COUNTER UP – NGT AND ALL NON FIRST CLK RECEIVE

CLK PLUSE FROM Q
Asynchronous Decade Counter

• The Modulus of a counter is the number of unique states that the counter will sequence
through.

• Counter can also be designed to have a number of states in their sequence that is less
than the maximum of 2n.

• Counters with the states in their sequence are called decade counters.

• To obtain a truncated sequence, it is necessary to force the counter to recycle before

going through all of its possible states.

• One way to make the counter recycle after the count of nine (1001) is to decode count
ten (1010) with a NAND gate and connect the output of the NAND gate to the clear
(CLR) inputs of the flip-flops. The inputs the NAND gate are from the Q output from
FF1 and FF3 ( from 1010 -- FF3FF2FF1FF0)
 Asynchronous Decade Counter
An asynchronously clocked decade counter with asynchronous recycling.

CLK Q3 Q2 Q1 Q0
PLUSE

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
GLITCH
11 0 0 0 1
12 0 0 1 0
13 0 0 1 1
14 0 1 0 0
15 0 1 0 1
16 0 1 1 0

MOD 10 RIPPLE UP COUNTER – NGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q
MOD 10 AS RESET / CLITCH AT 1010.
•The inputs the NAND gate are from the Q output from FF1 and FF3 ( from 1010 -- FF3FF2FF1FF0)
 Shift Register Counters

 Shift registers can form useful counters by recirculating a pattern of

0’s and 1’s. Two important shift register counters are the Johnson
counter and the ring counter.
 The Ring counter and Johnson counter can be made with a series of
either D flip-flops or J-K flip-flops.
 Ring Counter
 The ring counter can also be implemented with either D flip-flops or
J-K flip-flops.
 4-bit ring counters are constructed from a series of D flip-flops J-K
flip-flops. Notice the feedback.

Initial status
after clear and
Preset
Q0 Q1 Q2 Q3
0 0 0 1
 Ring Counter

 A common pattern for a ring counter is to load it with a single 1 or a

single 0.
 Draw the waveforms for the 4-bit ring counter
 Application of counters

• Frequency counters

• Digital clock

• Time measurement

• A to D converter

• Frequency divider circuits

• Digital triangular wave generator.