6/18/23, 2:03 PM Fabrication Steps: CMOS Processing (Part 1) |VLSI Concepts

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Thursday, September 4, 2014
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Fabrication Steps: CMOS Processing (Part 1)
Featured Post
Fabrication Steps: CMOS Processing
10 Employee
Chapter1 Chapter2 Chapter3 Chapter4 Workplace
Index Digital CMOS Employees func
Semiconductor Background
Background Processing making sure tha
incredibly import

3.1 3.2 3.3 3.4 3.5 3.6

Fabrication Create Create Implant Implant Create
Steps N-Well and Field Oxide Gate Oxide and Poly Layer N+ Impurities P+ Impurities Metal Contact
Vls

Property of material plays a very important role on the performance of MOSFET devices. If you are not agreeing with this
statement, then maybe you have to refer device physic. But now just believe me. J
While we are fabricating the MOSFET, we have to take care about the different material used based on the performance of end
product (MOSFET) and so we can say that properties of the material (which material, doping, sizes …) come from the Fabrication of
the MOSFET. In this post, I am going to brief you about the different Fabrication steps of CMOS device and some important info
which will help you to understand different terminology + fundamental of lower technology node process. Videos

Just few basics:

VLS
Materials can be classified in to 3 main groups as per their electrical conducting property.

1. Insulator

Used to isolate conducting or semiconducting material from each other.

MOS devices and Capacitance require insulator for their physical operation.
Which insulator is required – it depends on the functionality for which you want to use it.
Few of the known insulators are
Silicon Dioxide
Silicon Nitride
2. Conductor

Conductors are used in the IC world for electrical connectivity.

These are used as Local interconnects, Global Interconnects and in Contact/VIAs.
Few of the good conductors are:
Silver Total Pageviews
Gold
Copper
11,595,5
Aluminum
Platinum
3. Semiconductor

This is the base of whole semiconductor Subject. Silicon is the known semiconductor material. Popular Posts

This is very popular because of

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6/18/23, 2:03 PM Fabrication Steps: CMOS Processing (Part 1) |VLSI Concepts
Physical characteristic "Timing Paths
Timing Analys
Low cost because of easily available in the nature. basic (Part 1)
Selective doping of various regions of silicon allows the conductivity of the silicon to be changed with
Basic of Timin
the application of voltage. Analysis in Ph
Design
Other semiconductor material is GaAs but this use only for specific purpose/applications.
"Setup and H
There are lot of processing technology are available in the market but only few are very popular. Out of which majority of : Static Timing
(STA) basic (
production is done with Traditional CMOS. Others are limited to the area where CMOS is not very suitable (like High speed RF
applications). "Examples Of
and Hold time
Timing Analys
basic (Part 3c

"Setup and H
Violation" : St
Timing Analys
basic (Part 3b

10 Ways to fix
and HOLD vio
Static Timing
(STA) Basic (

Delay - "Wire
Model" : Stati
Analysis (STA
(Part 4c)

"Time Borrow
Static Timing
(STA) basic (

Delay - "Inter
Delay Models
Few important concepts about the fabrication Timing Analys
basic (Part 4b

ICs are created on Silicon Wafer. Maximum Clo

Frequency : S
Silicon Wafer is a very think disk of intrinsic Silicon on which rectangular or square shape of multiple ICs are created. Timing Analys
basic (Part 5b
Individual ICs are cut with the help of diamond saw and marked as pass or fail after proper testing.
The individual IC is called a “die”
EDN Feed

Macro models
engineers sim
circuits and s
Automate ES
protection ver
for complex IC
Formal-based
methodology
digital design
verification tim
Getting in syn
UVM sequenc
Get those clo
domains in sy

Followers

Followers (742

On the basis of good no of die in a wafer, we define a term YIELD.

Yield = (No of Good die)/(Total No of die on the wafer)
We always try to achieve 100% yield but that’s the ideal scenario. In a mature technology node or say process Yield
approximately equal to 90%.
Always remember – Yield decides the cost of the chip. Follow
All ICs on a same wafer are processed at the same time, so the time taken and process steps are same regardless the no
of ICs in silicon wafer.
This means the cost to process a wafer is the same whether it has 1 IC, or 1000 IC’s on it or not.
Lower technology node process (e.g. 45nm) has more number of die in silicon wafer in comparison to higher
technology node process (e.g. 180nm).

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Now we will understand few of the terminology which is linked with the Fabrication and now-a-days are more know to outside
world. I will not discuss too much about these because we need not to know the every details (like equations, equipment in each
process and all) of these steps. I will try to cover as much as possible which is required/ sufficient for CMOS fabrication point of
view.
Oxidation (Oxide Growth)
Photolithography
Etching
Deposition
Ion Implantation
Annealing

Oxidation:

Note: In case you are interested in more details about this process, you can refer chapter 3 of VLSI Technology by S.M SZE.

Oxidation of Silicon is necessary throughout the IC fabrication process. SiO2 plays an important role in IC technology because no
other semiconductor material has a native oxide which is able to achieve all the properties of SiO2. Silicon Dioxide has several uses:

To serve as a mask against implant or diffusion of dopant into the silicon

To provide the surface passivation (creating protective SiO2 layer on the wafer surface). It protects the junction from
moisture and other atmospheric contaminants.
To isolate one dielectric from other.
SiO2 acts as the active gate electrode in MOS device structure.
Used to isolate one device from other.
To provide the electrical isolation of multilevel metallization system.
Several techniques are there for forming oxide layer and each technique has their preferred uses.

1. Thermal Oxidation
1. When the interface between the oxide and the silicon requires a low charge density level, thermal oxidation has been
preferred technique.
2. Vapor-Phase technique
1. Also know as Chemical Vapor Deposition (CVD)
2. When oxide layer is required on the top of a metal as in case of multilevel metallization structure, vapor-phase
technique is preferred technique.

Just as a general principal and which you will see later – When Silicon exposed to oxygen – silicon dioxide form rapidly. Remember
– Silicon got consumed during this process.
There are 2 ways of doing oxidation. I can help you with the equations.

Si (Solid) + O2 -> SiO­2 (Solid)

This process is known as Dry Oxidation.

No byproduct.
Form a thin layer of Silicon Dioxide.
Si (Solid) + 2HO2 -> SiO­2 (Solid) + 2H2
Know as Wet Oxidation.
Hydrogen (H2) is the byproduct.
Forms a thick layer of Silicon Dioxide.
Note:
If heat is added to the process, the rate of SiO2 growth is sped up considerably
This is called “Thermal Oxidation” which applies to both Wet and Dry processes
Temperatures usually are in the range of 700 – 1300 C
Oxidation of Silicon surface:

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6/18/23, 2:03 PM Fabrication Steps: CMOS Processing (Part 1) |VLSI Concepts

Oxidation through a window in the oxides:

Selective Oxide Growth:

Note: above 3 diagrams are captured from CMOS Processing link.

Photolithography:

Note: In case you are interested in more details about this process, you can refer chapter 4 of VLSI Technology by S.M SZE.
A technique used in IC fabrication to transfer a desired pattern onto the surface of a silicon wafer. The word lithography comes
from the Greek lithos, meaning stones, and graphia, meaning to write. It means quite literally writing on stones. In the case of
semiconductor lithography (also called photolithography) our stones are silicon wafers and our patterns are written with a light
sensitive polymer called a photoresist.
Few important points to know about photolithography:
Process of lithography can be accomplished by selectively exposing parts of the wafer while other parts are protected.
The exposed sections are susceptible to doping, removal, or metallization.
Specific patterns can be created to form regions of conductors, insulators, or doping.
Due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts for about 30
percent of the cost of manufacturing.
Designer do the following things:
Drawing the “layer” patterns on a layout editor
Silicon Foundry:
Generate the Mask as per the layer pattern provided by Designer.
Transfer the mask pattern to the wafer surface.
Process the wafer to physical pattern each layer of the IC.

Lithography Process:
Photoresist coating:
A material that is acid-resistant under normal conditions.
When exposed to UV light, the material becomes soluble to acids
We put the photo resist on a wafer.
There are 2 type of photo resist. Positive and Negative. Positive Photoresist is the most popular due to its
ability to achieve higher resolution features

Original State After UV Exposure

“Positive Photoresist” Insoluble Soluble
“Negative Photoresist” Soluble Insoluble

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Exposure:
Mask pattern is developed as per the design.
A mask in an opaque plate (i.e., not transparent) with holes/shapes that allow UV light to pass
The mask contains the pattern that we wish to form on the target wafer
We pass the UV light and expose the photoresist region selectively as per the pattern present in the Mask.
UV rays create a soluble pattern in the photoresist. Depending on the type of photoresist (negative or
positive), the exposed or unexposed parts become resistant to certain types of solvents.
Apart of UV light there are other type of exposing radiation are also present.
Electron, X-rays or ions

Development:
Then we can soak the entire thing in acid/solvent and only the soluble photoresist (depends on positive or
negative photoresist) is removed.
The developed photoresist acts as a mask for patterning of underlying layers. We can also say that this
allows us to form a protective barrier on certain parts of the wafer while exposing others parts.

Etching:

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Just few points about etching. More in details you can refer my other post.

Once the desired shape is patterned with photoresist, the etching process allows unprotected materials to be removed.
Etches can remove Si, SiO2, polysilicon, and metal depending on what we want to accomplish.
I was just reading an article and like below definition of this step. I hope you will also like it.
The Process which immediately follows the photolithography step is the removal of material from areas of the wafer unprotected
by photoresist.

When I am going to discuss the different steps of CMOS fabrication in next few posts, you will get a very clear picture

Deposition:

Deposition is the process of laying down a thin film of material on the surface of a silicon wafer. During chip designing we use
several such films. It is opposed of growing where it consumes part of the target / wafer (like Oxide Growth)

Note: Copied the above diagram from Internet.

Few important things about the deposition:

These layers form wires and insulators that interconnect all the transistors of the device.
Material examples are:
SiO2, nitride, poly, metal
Materials are divided into 4 categories.
Metal
Aluminum alloys
Tungsten
Titanium Nitride
Silicides
Tungsten
Molybdenum
Titanium
Polysilicon
Dielectric
Silicon Dioxide
Silicon Nitride
Phospho-silicate Glass
Boro-phospho-silicate Glass
As per the process of Deposition it’s classified into 3 major areas

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1. Chemical Vapor Deposition (CVD)

This method are commonly used for depositing
Polysilicon
Dielectric
Metals
Silicides
The films created by this method are uniform films with excellent step coverage.
This method is very economical. Just chemical reaction is the limitation.
2. Physical Vapor Deposition (PVD)
It involves the physical removal of material from a target via ion bombardment. This is similar to sand blasting.
Film material flies away from the target and adheres to the wafer, making the desired film.
It can be used to deposit any material on any substrate. Because it’s a physical in nature and doesn’t rely on a
chemical reaction.
This method is not as economical as CVD
This method are commonly used for depositing
Aluminum
Gold and their alloys.
3. Epitaxy
It’s a unique form of CVD. The purpose of epitaxial deposition is to grow additional single crystal silicon above
the original wafer surface.
It’s a very expensive method and only used in the MOS processing.
Silicon
MBE
MOCVD

Ion Implantation:

The process of adding impurities (B, P, As) to a silicon wafer. Adding impurities are also known as doping. (ni -> NA, ND).
The Impurities means ions are accelerated toward the wafer with the help of Electric Field and it tunnel into the crystal
structure.
With the help of Lithography process, we can add these impurities selectively.

Annealing:

When we add the impurities into the wafer then it breaks the covalent bond of the structure. To improve/fix this
damage, Annealing is the process.
Below figure helps you to understand.

In the next part we will discuss about the various discuss different steps in the CMOS fabrication (Mostly only by Pictures).

Posted by VLSI Expert at 3:27 PM

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