Computer Organization and

Architecture

THE PROCESSOR: DATAPATH &

CONTROL
 Implementing MIPS
◼ We're ready to look at an implementation of the MIPS instruction set
◼ Simplified to contain only
◼ arithmetic-logic instructions: add, sub, and, or, slt
◼ memory-reference instructions: lw, sw
◼ control-flow instructions: beq, j

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format
An Overview of the
Implementation
◼ For every instruction, the two steps are identical:
◼ Send the program counter (PC) to the memory that contains

the code and fetch the instruction from that memory

◼ Read one or two registers, using fields of the instruction to

select the registers to read. For the load word instruction,

need to read only one register, but most other instructions
require two registers to read.
◼ After these two steps, the actions required to complete the
instruction depend on the instruction class, the actions are
largely the same, independent of the exact opcode.
An abstract view of the implementation of the MIPS subset
(Major Functional Units & Major Connections between them)
◼ All instructions start by using the program counter to supply the instruction
address to the instruction memory.
◼ After the instruction is fetched, the register operands used by an instruction are
specified by fields of that instruction.
◼ Once the register operands have been fetched, they can be operated on to
compute a memory address (for a load or store), to compute an arithmetic
result (for an integer arithmetic-logical instruction), or a compare (for a branch).
◼ If the instruction is an arithmetic-logical instruction, the result from the ALU
must be written to a register. If the operation is a load or store, the ALU result
is used as an address to either store a value from the registers or load a value
from memory into the registers. The result from the ALU or memory is written
back into the register file.
◼ Branches require the use of the ALU output to determine the next instruction
address, which comes from either the ALU (where the PC and branch offset are
summed) or from an adder that increments the current PC by 4.
◼ The thick lines interconnecting the functional units represent buses, which
consist of multiple signals.
An abstract view of the implementation of the MIPS subset
(Necessary Multiplexors and Control Lines)
◼ The top multiplexor controls what value replaces the PC (PC + 4 or the
branch destination address); the multiplexor is controlled by the gate that
“ands” together the Zero output of the ALU and a control signal that
indicates that the instruction is a branch.
◼ The multiplexor whose output returns to the register file is used to steer
the output of the ALU (in the case of an arithmetic logical instruction) or
the output of the data memory (in the case of a load) for writing into the
register file.
◼ Finally, the bottommost multiplexor is used to determine whether the
second ALU input is from the registers (for a non immediate arithmetic-
logical instruction) or from the offset field of the instruction (for an
immediate operation, a load or store, or a branch).
◼ The added control lines are straightforward and determine the operation
performed at the ALU, whether the data memory should read or write, and
whether the registers should perform a write operation.
◼ The control lines are shown in color.
Implementing MIPS: the
Fetch/Execute Cycle
◼ High-level abstract view of fetch/execute implementation
◼ use the program counter (PC) to read instruction address
◼ fetch the instruction from memory and increment PC
◼ use fields of the instruction to select registers to read
◼ execute depending on the instruction
◼ repeat…

Data

Register #
PC Address Instruction Registers ALU Address
Register #
Instruction
memory Data
Register # memory

Data
Overview: Processor
Implementation Styles
◼ Single Cycle
◼ perform each instruction in 1 clock cycle
◼ clock cycle must be long enough for slowest instruction; therefore,
◼ disadvantage: only as fast as slowest instruction
◼ Multi-Cycle
◼ break fetch/execute cycle into multiple steps
◼ perform 1 step in each clock cycle
◼ advantage: each instruction uses only as many cycles as it needs
◼ Pipelined
◼ execute each instruction in multiple steps
◼ perform 1 step / instruction in each clock cycle
◼ process multiple instructions in parallel – assembly line
 Datapath: Instruction
Store/Fetch & PC Increment

Instruction
address
Add
PC
Instruction Add Sum

Instruction
4
memory
Read
PC address
a. Instruction memory b. Program counter c. Adder
Instruction

Instruction
Three elements used to store memory

and fetch instructions and

increment the PC
Datapath
Animating the Datapath
Instruction <- MEM[PC]
PC <- PC + 4
ADD

PC
ADDR
Memory
RD Instruction
 Datapath: R-Type Instruction

ALU control ALU operation

5 Read 3 Read 3
register 1 register 1
Read Read
Register 5 data 1 data 1
Read Read
numbers register 2 Zero Zero
Registers Data ALU Instruction register 2
ALU
5 Write result Registers ALU ALU
register Write result
Read
data 2 register
Write Read
Data data data 2
Write
RegWrite
data

RegWrite
a. Registers b. ALU

Two elements used to implement Datapath

R-type instructions
 Animating the Datapath
add rd, rs, rt
Instruction
op rs rt rd shamt funct R[rd] <- R[rs] + R[rt];

5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite
 Datapath:
Load/Store Instruction

3 ALU operation
Read
MemWrite register 1 MemWrite
Read
data 1
Read
Instruction register 2 Zero
Registers ALU ALU
Address Read Write Read
result Address
data 16 32 register data
Sign Read
Write data 2
extend Data
Write Data data
data memory memory
RegWrite Write
data
16 32
Sign MemRead
MemRead
extend

a. Data memory unit b. Sign-extension unit

Two additional elements used Datapath

To implement load/stores
Animating the Datapath
lw rt, offset(rs)
R[rt] <- MEM[R[rs] + s_extend(offset)];
Animating the Datapath
sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)] <- R[rt]