IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO.

9, SEPTEMBER 2020 9267

Hardware Emulation of Energization of a Long

Transmission Line by High-Frequency
Power Electronic Converter
Sushmit Mazumdar and Kaushik Basu , Senior Member, IEEE

Abstract—Hardware emulators, simulating a test environment

in real time, are an essential tool in testing power system equipment.
This article presents a hardware emulator of a programmable
transmission line capable of simulating high-frequency transients.
Emulation of, energization of long transmission line, requires the
observer to solve transmission line or telegraphers equations in real
time. This article identifies a continuous time model that captures
the wave nature and suitable for real-time implementation.
This article derives the discrete-time model to be solved in the
observer of the hardware emulator. A step-by-step procedure Fig. 1. Schematic of a hardware emulator.
is given to determine two key emulator parameters: observer
sampling frequency, and switching frequency of the power
amplifier considering different hardware, event, and software received from the control hardware under test are processed
related constraints. For high bandwidth requirement, a high in real time by real-time digital simulator in accordance to a
switching frequency, 100-kHz, 12-kVA silicon carbide (SiC) based
voltage source converter is designed to operate under a current
mathematical model representing the emulated test environ-
controller with a gain crossover frequency of 5 kHz. A system on ment. This is called hardware-in-the-loop testing [1]–[4]. A
chip that combines an Anvanced RISC Machine (ARM) processor power apparatus can also be tested in real time by inserting
along with an field programmable gate array (FPGA) is used to a power amplifier (PA) between the real-time digital simulator
implement the observer. Experimental results verify accuracy and the power hardware under test. The PA is usually realized
of the designed emulator in the event of energization of a long
transmission line. Though proposed transmission line emulator
with a power electronic converter and such a test setup is known
can only be used to study the energization of a long line with one as power hardware in the loop (PHIL). PHIL to emulate test
end terminated with shunt reactor, the solution can be extended environments, such as photovoltaic system [5], variable speed
for emulation of a long line that links two sections of power grid. wind turbine with doubly fed induction generator, and perma-
Index Terms—Hardware emulator, power hardware in loop nent magnet synchronous machine emulation [6] has been done.
(PHIL), silicon carbide (SiC)-based power amplifier (PA), Various kind of faults in a grid have also been emulated [7].
transmission line energization. Testing of microgrids by PHIL technology is reported in [8]
I. INTRODUCTION and [9]. The most expensive component of PHIL is the real-
time digital simulator, such as OPAL-RT, Typhoon-HIL, RTDS,
T IS difficult to perform direct on-field-tests of power gen-
I eration and transmission equipment. So, it is necessary to
simulate the test environment in real time. This is usually done
dSPACE, or RT-Box, etc. Usually this type of real-time digital
simulator is capable of real-time simulation of a complex test
environments, such as large power system network. In general,
through real-time digital simulators. A control hardware under
the real-time digital simulator, in PHIL test setup, finds the
test can be interfaced with a real-time digital simulator through
current reference to be tracked by the PA from the sensed
analog-to-digital and digital-to-analog converters. The signals
voltage signal, by solving the electrical characteristics of the
emulated environment, or plays the role of the observer. To
Manuscript received July 18, 2019; revised October 23, 2019 and December
25, 2019; accepted January 29, 2020. Date of publication February 12, 2020; emulate a specific test environment, a real-time controller (DSP
date of current version May 1, 2020. This work was supported by the Department or field programmable gate array (FPGA)) can be programmed to
of Science and Technology, Government of India, through the Fund for Improve- perform as an observer. This type of emulated test environment,
ment of Science and Technology Infrastructure Program at the Indian Institute of
Science, Bangalore, India, and Project “Development of an Advanced System- as shown in Fig. 1, is known as hardware emulator. Hardware
on-Chip (SoC)-Based Embedded Controller for PowerElectronic Converters.” emulator of synchronous generator and electrical load has been
Recommended for publication by Associate Editor F. Wang. (Corresponding reported in [10], [11], and [12]–[14], respectively. Hardware in
author: Sushmit Mazumdar.)
The authors are with the Department of Electrical Engineering, Indian In- loop of an induction machine is attempted in [15].
stitute of Science, Bangalore 560012, India (e-mail: [email protected]; Being the fundamental element of the power system, hardware
[email protected]). emulator for transmission line is required to bridge the gap
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org. between the source (synchronous generator) and load emula-
Digital Object Identifier 10.1109/TPEL.2020.2973543 tors. Hence, a programmable transmission line emulator (TLE)
0885-8993 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 9268 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

could be one or a group of voltage source inverters interfacing

wind- or solar-based sources to the grid. The transient currents
during energization need to be supplied by the DUT, whereas the
voltage at the point of common coupling will also be distorted. It
is important that these group of converters (DUT) does smoothly
ride-through this transient. The proposed TLE will serve as a test
setup. This article makes the following contributions.
1) Unlike previously studied phenomenalike power flow or
fault, this article attempts at the emulation of the energiza-
tion of a long transmission line.
2) As a first step through simulation, this article identifies
a transmission line model that is suitable for real-time
implementation on an embedded platform. It also ensures
faithful reproduction of the transient phenomenon under
study.
3) The derivation of the discrete-time version of the identi-
fied model to be solved in the observer of the hardware
Fig. 2. General architecture of a TLE. emulator is then presented in this article.
4) A step-by-step method has been developed for the deter-
mination of two key parameters: sampling frequency of the
needs to be developed that will have the flexibility of emulating observer and switching frequency of the PA, considering
transmission line with varying line parameters. The general hardware and software related constraints.
architecture of a TLE is shown in Fig. 2 [16]–[18]. The two 5) Due to high bandwidth requirement, a silicon carbide
major components of this setup are the observer and the PA. (SiC)-based power converter along with a resonant-based
With the line end voltages vse(J) and vre(J) , as the input, the closed-loop controller are designed for the implementa-
observer solves the transmission line model in real time and tion of the PA. Both the observer and controller are imple-
estimates the line end currents. These currents (i∗se(J) and i∗re(J) ) mented on Zynq 7000 a System-on-Chip (SoC) platform
are then tracked by the PA by controlling its output currents in from Xilinx.
(1) and (2), shown at the bottom of this page. 6) A test setup and a suitable test procedure for the emulation
The PA is comprised of two back-to-back connected 3φ of energization has been developed.
voltage source converters (VSCs) operating under closed-loop This article is organized as follows. Section II provides the
current control. Based on similar architecture, emulation of modeling of a distributed parameter lossy transmission line
short lossless transmission line during steady state has been suitable for emulation of high-frequency transients. Section III
reported in [16] and [17]. The transmission line is modeled describes the details of implementation of the real-time observer
as a lumped inductor and is emulated by the VSCs using two on an embedded platform. Simulation of the developed observer
approaches, namely, phasor-domain model and time-domain in MATLAB/Simulink is shown in Section IV. Section V deals
model. In [18], a TLE for symmetrical 3φ fault emulation of with scaling of the actual transmission line to laboratory-level
short lines has been reported. In [19], a TLE is developed for emulator. Details of the controller design for the PA has been
emulation of three-phase symmetrical fault at an arbitrary point discussed in Section VI. The proposed test bench setup for the
of a long transmission line. To capture the distributed nature of TLE is given in Section VII. Finally, the relevant simulation and
a long line, a model based on method of characteristics is used experimental results are provided in Section VIII followed by
in [19], which is taken from [20]. As voltages and currents are the conclusion in Section IX. Though the proposed TLE is meant
computed at intermediate points of the transmission line and this for emulation of energization of a long transmission line only,
helps in determining the initial conditions required for postfault Appendix A gives a brief outline of how the presented design
emulation in [19]. can be extended to a general TLE of Fig. 2.
This article focuses on the design of TLE for emulation of
transients in a long line with a shunt reactor connected at the open
end. In this PHIL test setup, the sending grid, which is switched II. MODEL SELECTION
ON to the transmission line, is the device under test (DUT). As In PHIL emulator design, one of the most important tasks is
we are moving toward converter-based generation [21], DUT to identify a model of the emulated system (here, transmission

ise(J) (t) = C1 vse(J) (t) −C2 vse(J) (t − τ ) − C3 ise(J) (t − τ ) − C4 vre(J) (t − τ ) − C5 ire(J) (t − τ ) (1)
  
Is(J) (t−τ )

ire(J) (t) = C1 vre(J) (t) −C2 vre(J) (t − τ ) − C3 ire(J) (t − τ ) − C4 vse(J) (t − τ ) − C5 ise(J) (t − τ ) (2)
  
Ir(J) (t−τ )

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9269

Fig. 3. Waveforms for the switching of the circuit shown in Fig. 4 at the positive peak of the a phase voltage with the parameters given in Table I using (a) FDM
and R–L model, (b) FDM and nominal-π model, and (c) FDM and Bergeron’s model in PSCAD software.

TABLE I
PARAMETERS OF THE ACTUAL TRANSMISSION LINE UNDER STUDY

Fig. 4. Circuit schematic of voltage switching of an unenergized transmission

line with shunt reactor connected at the receiving end.

Among the numerical schemes that capture distributed na-

ture of the line, the model in [19] and Bergeron’s model are
considered. Both are derived using method of characteristics in
line). A more complex model ensures accurate results but at the solving telegrapher’s equations. Compared to the method used
cost higher computation burden. We need to identify a model in [19], in Bergeron’s model, series resistance is considered
that is computationally least challenging but results in faithful only in lumped form and shunt conductance is neglected. It is
reproduction of the event under consideration. shown in Appendix D, in emulation of energization of a long
A simple series connected resistance and inductance (R–L) transmission line with one end terminated with shunt reactor, that
model is fairly accurate for the short lines (length (l) < 80 km), Bergeron’s model is more computationally efficient compared
but not sufficient for the medium or long lines. For medium to the scheme used in [19]. In this work, Bergeron’s model is
lines (80 km < l < 250 km), the nominal-π lumped parameter selected as the numerical scheme to solve the transmission line
model can be used for steady state analysis but it fails to gen- in real time and emulate by a VSC. In Bergeron’s model, the
erate appropriate results during transients. For long lines (l > terminal currents (ise(J) (t) and ire(J) (t) where J {a, b, c}) at
250 km), both R–L and the nominal-π model are inadequate for time t can be computed using (1) and (2) from the knowledge
producing the correct result during the transients as well as in the of the terminal voltages (vse(J) (t) and vre(J) (t)) and the val-
steady-state conditions. The circuit diagram for energization of a ues of these quantities at retarded time instant (t − τ ), where
transmission line with a shunt reactor connected at the other end τ = cl is the wave travel time, l is the length of the line, and
1
is shown in Fig. 4. The breaker B is closed at the positive peak of c = √LC is the velocity of the wave. R, L, and C are the
the a phase of the grid voltage. The simulation is done in PSCAD line resistance, inductance, and capacitance per unit length,
software using the frequency-dependent model (FDM) [22] with respectively. The coefficients C1−5 can be computed using
a set of parameters given in Table I. The subscripts se and re the line parameters
 as shown in Table VI, in Appendix C,
L
denotes the sending and receiving end of the transmission line, where Zc = C is the characteristic impedance of the line,
respectively. and RT = lR is the total line resistance. vseg(J) (t) is the grid
The FDM of the PSCAD has been taken as the benchmark voltage.
model and compared with R–L and nominal-π models for the
same parameters provided in Table I. The mismatch in the
sending end voltage and current of the “a” phase are shown
A. Model to be Implemented in Embedded Platform
in Fig. 3(a) and (b). Therefore, for lines above 250 km, one must
consider the fact that the parameters are not lumped but rather Equations (3) and (4) can be written by considering the circuit
distributed. configuration of Fig. 4 at the sending and receiving end of the

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 9270 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

TABLE II
INSTRUCTION CYCLE REQUIREMENTS BY THE ZYNQ SOC

Fig. 5. Equivalent network of the transmission line.

line, respectively and

dise(J) (t) Lg  
vse(J) (t) = vseg(J) (t) − Lg (3) vse(J) [k] = vseg(J) [k] − ise(J) [k] − ise(J) [k − 1] . (8)
dt Tob
dire(J) (t) Substituting vre(J) [k] and vse(J) [k] using (7) and (8), respec-
vre(J) (t) = −Lsh . (4)
dt tively, into (5) and (6), we derive (9) and (10). The constants are
The equivalent circuit based on (1)–(4) is shown in Fig. 5, where defined in Table VII in Appendix C
vseg(t) is the grid voltage, Lg is the grid inductance, and Lsh is ise(J) [k] = C6 vseg(J) [k]+ C7 ise(J) [k−1]+ C8 vseg(J) [k−N ]
the inductance of the shunt reactor connected at the receiving
end. + C9 ise(J) [k − N ] + C10 ise(J) [k − N − 1]
+ C11 ire(J) [k − N ] + C12 ire(J) [k − N − 1] (9)
III. IMPLEMENTATION OF OBSERVER ON
EMBEDDED PLATFORM ire(J) [k] = C13 ire(J) [k − 1] + C14 ire(J) [k − N ]

The observer computes the current reference (ise(J) (t)) to + C15 ire(J) [k − N − 1] + C16 vseg(J) [k − N ]
be tracked by the PA by sensing vseg(J) (t). The observer is + C17 ise(J) [k − N ] + C18 ise(J) [k − N − 1] .
implemented on an embedded platform to digitally compute (10)
the current reference in discrete time. In this section, we first
determine the set of difference equations to implement the circuit Equations (8)–(10) are solved in real time to implement the
shown in Fig. 5. We also will outline a step-by-step procedure observer. vseg(J) [k] is the input, ise(J) [k] and ire(J) [k] are the
for determination of two key parameters namely sampling time state variables, and vse(J) [k] and ise(J) [k] are the outputs.
period of the observer (Tob ) and the switching period (Tsw ) of
the VSC. B. Determination of Observer Computation Time
Xilinx make Zynq SoC has been selected as the embed-
A. Discretized Equation of Bergeron’s Model
ded platform, which has an Anvanced RISC Machine (ARM)
For digital implementation, τ must be an integral multiple of Cortex-A9-based processing system (PS). The required number
Tob in order to avoid the complex interpolation schemes [23]. of instruction cycles for execution of different operations or
Hence, substituting τ = N Tob , t = kTob (where k is the discrete instructions has been listed in Table II [24]. We assume that
time index), and defining ise(J) [k] = ise(J) (t = kTob ), (1) and the 3φ transmission line is balanced and transposed throughout
(2) can be written as its length. So, we calculate the line end currents for two phases
and the third one is taken as the negative sum of the other two
ise(J) [k] = C1 vse(J) [k] − C2 vse(J) [k − N ] − C3 ise(J) [k−N ]
phases. This reduces the computational burden for real-time
− C4 vre(J) [k − N ] − C5 ire(J) [k − N ] (5) implementation. The number of instructions to be executed in
every observer computational cycle can be found considering
and the following steps:
ire(J) [k] = C1 vre(J) [k] − C2 vre(J) [k − N ] − C3 ire(J) [k − N ] 1) feed the latest sending end grid voltage of the a and b phase
of the transmission line [2 × nls ];
− C4 vse(J) [k − N ] − C5 ise(J) [k − N ] . (6) 2) referring (9), seven multiplication and six addition are
involved for calculating the sending end current for each
Equations (5) and (6) demand the use of three memory buffers
a and b phase [14 × nmul , 12 × nadd ];
for each phase of the transmission line to store the past values of
3) referring (10), six multiplication and five addition are
the sending end voltages, currents, and receiving end currents.
involved for calculating the receiving end current for each
Therefore, the size of the first-in first-out (FIFO) buffers should
a and b phase [12 × nmul , 10 × nadd ];
be atleast N . Using backward Euler on (4) and (3), we can write
4) referring (8), one multiplication and two subtraction are
Lsh   involved for calculating the sending end line voltage for
vre(J) [k] = − ire(J) [k] − ire(J) [k − 1] (7) each a and b phase [2 × nmul , 4 × nsub ];
Tob

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9271

2) Determination of Wave Travel Time: The length of the

transmission line is considered to vary from 300 to 500 km. The
wave velocity for the chosen line with the parameters shown in
Table I is 2.78 × 105 km/s. Considering a standard set of line
parameters [25], the range of wave velocity is found to vary from
2.5 × 105 to 3 × 105 km/s. So, the minimum wave travel time
300
τmin = = 1000 μs. (14)
3 × 105
Similarly, the maximum wave travel time
500
Fig. 6. Harmonic analysis of the a phase sending end current of Bergeron’s τmax = = 2000 μs. (15)
2.5 × 105
model of PSCAD.
3) Constraints on Observer Sampling Period: Observer dig-
itally simulates the transmission line in real time, by sampling
5) N + 1 number of shifting operations in the memory
the sending end voltage, vseg(J) [k], and computing the cur-
buffers of the sending end grid voltage and current of
rent reference, i∗se(J) [k]. According to sampling theorem, the
a and b phase, so that it can be recycled and used
sampling frequency must be at least twice that of the largest
[4 × (N + 1) × nmov ];
frequency component present in the input signal, here vseg(J) ,
6) N + 1 number of shifting operations in the memory
in order to avoid aliasing. This implies the input signal must be
buffers of the receiving end current of a and b phase, so
band-limited. If this is not the case, we need to pass it through a
that it can be recycled and used [2 × (N + 1) × nmov ];
low-pass filter, also known as antialiasing filter. In present case
7) sending end current calculation for the c phase [2 × nsub ].
during energization when the breaker (see B in Fig. 8) is closed,
The shifting operation in the memory buffers is done by a
there is a step change in the input signal, which theoretically
counter, which needs to be incremented and compared with the
contains all frequency components. In the current waveform,
reference value. Denoting the instruction clock period of the
which is the output here, we have seen that there is no component
PS as Tclk(PS) (which is 6 ns for the selected processor), the
beyond 500 Hz. Since the system (Bergeron’s model) is a linear
total computational time required by the observer (Tobc ) can
system, therefore, we can say that it acts as a low-pass filter with a
be written as
cutoff frequency of 500 Hz. So, we will come up with the same
114 τ current waveform even if we remove the components beyond
Tobc = Tclk(PS) [277 + 19N ] ≈ 1.66 + μs. (11)
1000 Tob 500 Hz from the input step voltage and apply it to the system
(Bergeron’s model). The cutoff frequency of the antialiasing
C. Determination of Frequency Content of the Sending End filter (Fc(aa) ) is kept at 5 kHz, so that there is negligible amount
Line Currents During the Switching Instant of phase loss to the components up to 500 Hz. Now, following
The FFT analysis of the sending end current waveforms gen- sampling theorem, sufficient guard bandwidth, the minimum
erated from Bergeron’s model of PSCAD for the case discussed sampling frequency of the observer is set at five times higher than
earlier has been done at the switching instant of the line, choosing the cutoff frequency of the antialiasing filter. So, the minimum
the time window till the transients die down completely. The sampling frequency is set at 25 kHz. Therefore, the maximum
result of the FFT analysis is shown in Fig. 6. The maximum possible value of the observer sampling period
frequency content (Fi(max) ) in the sending end line currents is 1 1
Tob ≤ Tob(max) = = = 40 μs. (16)
found to be nearly 500 Hz. 5 × Fc(aa) 5 × (5 × 103 )
In digital control of power converters, generally the controller
D. Determination of Tob and Tsw
output is updated at every switching period Tsw . Therefore, it is
1) Constraints on Switching Period of the VSC: The switch- not necessary to update the control loop reference signal coming
ing frequency of the converter (Fsw ) is kept atleast ten times from the observer faster than this rate. Hence, we can write
higher than the current control loop bandwidth to minimize the
phase loss of the current control loop gain, which is again kept Tob ≥ Tsw . (17)
at ten times the maximum frequency of the current signal to be There are approximately Tob /Tsw number of switching cycles
tracked. So, we can say that the minimum value of the switching in one observer sampling cycle. So, the amount of observer
frequency computation that needs to be done in each switching cycle is
Tobc
Fsw(min) = 100 × Fi(max) = 50 kHz Tob /Tsw . Hence, we should ensure that

⇒ Tsw(max) = 20 μs ≥ Tsw . Tobc

(12) Tsw ≥ Δt + (18)
Tob /Tsw
SiC-based converter is designed to operate at a maximum
where Δt is the time required to perform sensing and signal
switching frequency of 100 kHz. So
filtering, closed-loop control and duty cycle updation, and pro-
∴ Tsw(min) = 10 μs ≤ Tsw . (13) tection. Δt is nearly 5 μs for the selected Zynq PS. Substituting

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 9272 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

Fig. 8. Block diagram of observer simulation in MATLAB/Simulink software.

Fig. 7. Feasible region of Tob and Tsw for all possible values of τ .

(11) in (18), we get

2
5Tob
Tsw ≥ 2 − 1.66T − 0.114τ . (19)
Tob ob

4) Steps to Determine N , Tob , and Tsw : In summary for a

given τ , Tob , and Tsw needs to satisfy (12), (13), (16), (17), and
(19). Graphically, this results in the shaded feasible region in
the Tsw − Tob plane, as shown in Fig. 7. Note here that the
transmission line parameter τ affects determination of Tob and
Tsw through (19). Substituting the extreme values of τ from (14) Fig. 9. Sending end voltage and current waveforms for the simulation of the
and (15) in (19), we come up with circuit, shown in Fig. 4, with the parameters given in Table I using frequency
dependent and Bergeron’s model of PSCAD and the developed observer (see
2
5 Tob Fig. 8) in MATLAB/Simulink.
Tsw ≥ (20)
2
Tob − 1.66Tob − 114
and chosen as
2
5 Tob Tob
Tsw ≥ 2 . (21) Tsw =  . (24)
Tob − 1.66Tob − 228 Tob
Tsw(max) ceil
Fig. 7 also shows how (19) changes for two extreme values
of τ . Based on this, a step-by-step procedure for selecting N , IV. SIMULATION IN MATLAB/SIMULINK
Tob , and Tsw is developed.
Step 1—Determination of N : It is clear from Fig. 7 that for As shown in Fig. 8, a block has been developed in MAT-
any value of τ , it is possible to achieve Tob close to Tob(max) and LAB/Simulink that acts as an observer to solve the distributed
Tsw close to Tsw(max) . From (11), it can be seen that Tobc reduces parameter transmission line. The development of the block is
on maximizing the value of Tob for a given value of τ . Hence, based on (8)–(10). Using the line parameters given in Table I, τ
the buffer size N is chosen as is obtained as 1440 μs. Hence, applying (16), (22), and (23), the
buffer size as well as the sampling time period of the observer
τ
N= (22) has been chosen, as shown in the following:
Tob(max) ceil
1440
where the ceiling function [x]ceil rounds off x to the nearest N= = 36
40 ceil
higher integer.
Step 2—Determination of Tob : and
τ 1440
Tob = . (23) Tob = = 40 μs.
N 36
Hence, it is ensured that the chosen Tob is always less than Voltage switching action of the transmission line, as shown in
Tob(max) . Fig. 4, is then simulated with the parameters provided in Table I.
Step 3—Determination of Tsw : In order to reduce the switch- From Fig. 9, we can see that the result of the developed observer
ing loss in the VSC, Tsw is selected on the higher side of in the MATLAB/Simulink matches well with the Bergeron’s
its range, i.e., close to Tsw(max) . At the same time, for ease model of PSCAD. Hence, this justifies the modeling [see (8)–
of implementation in the digital platform, Tsw is chosen such (10)] and developed procedure to determine observer sampling
that Tob becomes an integral multiple of Tsw . Hence, Tsw is period and the buffer size for digital implementation.

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9273

TABLE III
PARAMETERS OF THE SCALED DOWN TRANSMISSION LINE SYSTEM

TABLE IV
PARAMETERS OF THE CONTROLLER USED FOR THE PA OF THE TLE

Fig. 10. Block diagram representation of the controller for PA.

V. SCALING DOWN OF THE ACTUAL SYSTEM TO and

LABORATORY-LEVEL HARDWARE
Lsh = Lsh × Sz .
For emulating the transmission line using laboratory-level
power electronic hardware, we need to scale down the system to The parameters of the scaled down system are given in Table III.
the power and voltage level, which can be safely handled in the
laboratory. But while scaling, we should ensure that the system VI. CONTROLLER DESIGN FOR PA
dynamics remains unaltered. Hence, the wave velocity in both In this section, a closed-loop current controller for the PA
the actual and the scaled down transmission line should be same. is designed for tracking the sending end current following the
From Fig. 3(c), it is seen that the maximum value of current (Im ) current reference generated by the observer.
in a phase is nearly 1800 A. Now, with reference to the ratings
of the device used in the PA, the maximum possible value of A. Plant Model

current in the scaled down system (Im ) is set at 28 A. Similarly,
mapping the 400 kV level of the original system to 220 V The voltage source inverter in the sending side of the PA is
level of the scaled down system, the scaling factor Sz can be needed to operate under current control with current reference
written as i∗se(J) coming from the observer (see Fig. 12). This inverter is

connected to the sending end grid vseg(J) through a filter inductor
VLL(RMS)

Im
220 Lf , which has a parasitic series resistance Rf . After sensing the
28
Sz = VLL(RMS)
= 400000 = 0.03536. (25) inductor current and grid-side voltage, the control is similar to
Im 1800 the control of a grid-tied inverter under current control. With
Since the per unit values are same both in the original and the grid and dc-bus voltage feed forward cancellation (see Fig. 10)
scaled down system for the conservation of the system dynamics, and as switching frequency is sufficiently higher than the control
hence denoting R , L , and C  as the line resistance, inductance, loop gain crossover frequency 5 kHz, it is possible to model the
and capacitance per unit length of the scaled down transmission plant for each phase, ise(J) (s)/d(s) = 1/(Rf + sLf ).
line system, we can write
B. Design Objectives
R  = R × Sz
1) The dominant component of the line current during en-
L = L × S z ergization is 50 Hz (see Fig. 6). Also, the current in the
post energization steady state is essentially a sinusoid at
and
frequency 50 Hz. So, the controller must provide large
C gain at 50 Hz as the controller is designed in natural abc
C = .
Sz frame.
Therefore, the travel time of the wave in the scaled down 2) During energization, the current has frequency compo-
transmission line nents up to 500 Hz. The controller must ensure sufficiently
√ √ large loop gain (at least greater than 10 or 20 dB) for all
τ  = l × L C  = l × LC = τ. frequencies below 500 Hz.
Similarly, the values of the grid inductance and the line end
C. Controller Design
reactor for the scaled down system can be obtained as
A PR controller, given in (26), is chosen. It has three parame-
Lg = Lg × Sz ters: resonant frequency ω◦ , proportional gain Kpr , and integral

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 9274 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

connected on the other side (see Fig. 4) is shown in Fig. 12.

The test procedure has been elaborately discussed as follows.
1) 3φ VSC is used to track the sending end currents of the
transmission line during the instant of switching.
2) An active front-end converter is used to provide a stable
dc bus vDC and also supply for the losses in the VSC
along with supporting the emulated resistive loss in the
transmission line.
3) To have the flexibility of implementing a programmable
grid impedance in the experimental setup, a strong grid
(sinusoidal voltage source) is used and the inductive grid
impedance is emulated inside the embedded platform.
Fig. 11. Bode diagram of the current control loop of Fig. 10. 4) Since the switching phenomenon of the transmission line
will be emulated by VSC, it should be synchronized to the
gain Kir grid before the emulation is being done. The steps are as
Kir follows.
sKir s2 + s K + ω◦2
GPR pr a) The VSC is run in standalone mode generating the
c (s) = Kpr + 2 = Kpr . (26)
s + ω◦2 s2 + ω◦2 output voltage of same magnitude, frequency, and
With this, the open-loop gain becomes phase as that of the grid.
Kir
b) Once the grid synchronization is being done, the con-
1
s2 + s K + ω◦2 Rf tactor C1 is closed and the VSC is operated in current
GTLE
oltf (s) = Kpr
pr
× . (27)
s2 + ω◦2 1
L
+ Rff s control mode with current reference i∗se(J) = 0.
5) Again to have the flexibility to emulate the switching of the
The first objective is met by choosing ω◦ = 100π rad/sec. The transmission line at different values of the phase voltage,
second objective is met through the following procedure: we need to extract the voltage information of the grid
1) by setting the gain crossover frequency at 5 kHz, which is before switching. Then, depending on the desired instant
ten times of 500 Hz. This is done by choosing Kpr using the of switching, the contactor C2 will be energized and a step
following procedure. With Rf = 0.2 Ω and Lf = 0.5 mH voltage will get applied at the input of the observer. This
for the selected filter and equating the gain crossover will start the emulation process and the VSC will start
frequency (ωgc ) for the aforementioned transfer function tracking the current generated by the observer.
to 5 kHz, we can write
Kpr VIII. EXPERIMENTAL VERIFICATION
oltf (jω)|ω=ωgc ≈
|GTLE =1
Lf × ωgc As shown in Fig. 13, an SiC-based 3φ VSC rated for 415 V/
−3
⇒ Kpr = Lf × ωgc = 0.5 × 10 × 2π × 5000 ≈ 15.71. 50 Hz ac, 10 kW, 800 V dc, and 100-kHz switching frequency
(28) has been designed and fabricated in the laboratory. Single leg
modules of half-bridge topology with plug- and play-type gate
2) the gain of open-loop transfer function at 500 Hz is set to driver card has been developed and then connected to achieve
20 dB by selecting the parameter Kir . Kir is evaluated by the required topology. The modularity in the design not only
equating the gain of GTLE
oltf (s) to 20 dB at a frequency of allows the flexibility to adopt different converter topology but
500 Hz, i.e. also facilitates easy repair and replacement. Discrete SiC devices
  Kir 2
2 +
from Rohm (SCH2080KE) of TO-247 package have been used
5 Kpr 2π×500 to build the VSC. The gate drive IC (ADuM4135BR) from
|Goltf (jω)|ω=2π×500 ≈ 
TLE
 2 = 10 analog devices has been used to build the gate driver card. A
−3
1 + 2π×500×0.5×10
0.2 prototype of the TLE, as shown in Fig. 12, has been fabricated
in the laboratory to verify the proposed emulation scheme. The
⇒ Kir = 2π × 500 × 1.945 ≈ 6110. (29)
corresponding hardware setup of the developed TLE test bench
The loop gain is plotted in Fig. 11. It shows that loop gain is is shown in Fig. 14. The observer is implemented on a Zynq SoC
more than 20 dB for all frequencies below 500 Hz and gain is XC7Z010-1CLG400 C from Xilinx.
quite high at 50 Hz. Closed-loop transfer function shows almost
unity gain and zero phase upto 500 Hz. The parameters of the A. Parameters and Test Conditions
designed controller for the power amplifier are given in Table IV.
For a set of line parameters, grid impedance, and shunt reactor,
the transients in the line currents are studied for three different
VII. PROPOSED SCHEME OF IMPLEMENTATION values of line length. The parameters of the original and scaled
OF THE TLE TEST SETUP
down system are provided in Tables I and III, respectively.
A proposed test bench setup for the hardware emulation of Considering the values of l to be 300, 400, and 500 km, we obtain
the energization of a transmission line with a shunt reactor three different values of wave travel time. As given in Table V,

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9275

Fig. 12. Proposed scheme for the hardware implementation of the TLE.

Fig. 14. Hardware setup of the TLE test setup.

Fig. 13. Developed SiC-based VSC.

B. Results

TABLE V
The sending end voltage and current of the transmission line
EXPERIMENTAL PARAMETERS FOR THE OBSERVER AND PA for the “a” and “b” phase are captured for each of the test
cases. The results of the conducted test corresponding to a
particular value of line length and switching instant are shown in
Figs. 15–17, where each of the figure again contains subfigures
as described.
Fig. 15(a) shows the simulation of the circuit schematic,
shown in Fig. 4, with the parameters of the original system
the values of the size of FIFO buffer (N ), observer sampling given in Table I using FDM in PSCAD for the mentioned value
period (Tob ), and the switching period of the VSC (Tsw ) are of the line length and switching instant. Fig. 15(b) shows the
chosen based on the calculations proposed in Section III. Also simulation of the circuit schematic, shown in Fig. 4, with the
to verify the functionality of the observer under different test parameters of the scaled system given in Table III using FDM in
conditions, the lines are switched at the zero crossing (Φ = 0◦ ) PSCAD for the mentioned value of the line length and switching
and the positive peak (Φ = 90◦ ) of “a” phase of the sending end instant. Fig. 15(c) shows the simulation of the block diagram
grid voltage. schematic shown in Fig. 4 with the parameters of the scaled

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 9276 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

Fig. 15. Waveforms for the switching of the circuit, shown in Fig. 4, at the positive peak of the a phase voltage and line length of 400 km. (a) Simulation of
circuit schematic, shown in Fig. 4, using parameters of original system given in Table I by FDM in PSCAD. (b) Simulation of circuit schematic, shown in Fig. 4,
using parameters of scaled system given in Table III by FDM in PSCAD. (c) Simulation of block diagram schematic, shown in Fig. 8, using parameters of scaled
system given in Table III by MATLAB/Simulink. (d) Hardware emulation using parameters of scaled system given in Table III by the proposed emulation scheme
shown in Fig. 12.

Fig. 16. Waveforms for the switching of the circuit, shown in Fig. 4, at the positive zero crossing of the a phase voltage and line length of 300 km. (a) Simulation
of circuit schematic, shown in Fig. 4, using parameters of original system given in Table I by FDM in PSCAD. (b) Hardware emulation using parameters of scaled
system given in Table III by the proposed emulation scheme shown in Fig. 12.

system given in Table III by the observer in MATLAB/Simulink and current of a phase of Fig. 15(b) and (d) are plotted together,
for the mentioned value of the line length and switching instant. as shown in Fig. 18. The corresponding FFT analysis of the
Fig. 15(d) shows the hardware emulation of the scaled system current waveforms generated from the simulation as well as the
with the parameters given in Table III, as per the proposed experiment is also shown in Fig. 19.
emulation scheme shown in Fig. 12, for the mentioned value Figs. 16(a) and 17(a) show the simulation of the circuit
of the line length and switching instant. To investigate the schematic, shown in Fig. 4, with the parameters of the original
performance of the developed TLE, the sending end voltage system given in Table I using FDM in PSCAD for the mentioned

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9277

Fig. 17. Waveforms for the switching of the circuit, shown in Fig. 4, at the positive zero crossing of the a phase voltage and line length of 500 km. (a) Simulation
of circuit schematic, shown in Fig. 4, using parameters of original system given in Table I by FDM in PSCAD. (b) Hardware emulation using parameters of scaled
system given in Table III by the proposed emulation scheme shown in Fig. 12.

Fig. 19. FFT analysis of the current waveforms generated from the simulation
as well as experiment shown in Fig. 18.

Fig. 18. Exaggerated view for the sending end voltage and current of a phase
from the waveforms. It is also noted that the peak value of the
of Fig. 15(b) and (d). current transient increases with increase in line length. This
is due to the addition of more shunt capacitance associated
with the transmission line. It can be seen that in all cases, the
value of the line length and switching instant. Figs. 16(b) and emulation performed by the developed TLE closely matches
17(b) show the hardware emulation of the scaled system with with the PSCAD results.
the parameters given in Table III, as per the proposed emulation
scheme shown in Fig. 12 for the mentioned value of the line IX. CONCLUSION
length and switching instant.
The problem of hardware emulation of energization of a long
unenergized transmission line has been successfully addressed
C. Observation in this article. After studying various line models, a traveling
It is observed that, on switching the transmission line of dif- wave based numerical solution (Bergeron’s model) was selected
ferent lengths at the zero crossing of a particular phase voltage, to solve the distributed parameter lossy transmission line in real
the transient in the line currents for that phase is minimum time by the observer. The wave travel time, computed from
compared to the other phases. Moreover, as the length of the transmission line parameters directly impacts, the determina-
line is increased, the transients get damped out faster due to the tion of the observer sampling frequency, the key discretization
increase in the effective line resistance, which is also observed parameter of the transmission line emulation. This article shows

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 9278 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

how to derive the switching frequency of the VSC. For the PA

of the TLE setup, an SiC-based VSC rated for 415 V/ 50 Hz ac,
10 kW, 800 V dc, and capable of operating at a switching
frequency greater than 50 kHz has been designed and fabricated
in the laboratory. Furthermore, the hardware topology for the
implementation of the TLE as well as scaling of the actual
transmission line to laboratory-level emulator is presented. The
design of the proportional resonant controller is also given in the
article, which is used by the PA to track the currents provided
by the observer. Finally from the results, it can be concluded
that the developed TLE exhibits a high level of similarity with
the actual transmission line system results obtained from the Fig. 20. Block diagram structure of PR controller in continuous time domain.
FDM of PSCAD. One limitation of the presented TLE is its
applicability only in the energization but it can be extended to a and
general TLE of Fig. 2, as shown in Appendix A.  
x2(J) [k] = x2(J) [k − 1] + x1(J) [k] × ω◦ × Tsw . (34)
APPENDIX A Considering (ω◦ × Tsw ) and (Kir × Tsw ) being the predeter-
A brief outline of implementation of the general scheme of mined quantities, from (33), (34), and Fig. 20, we can say that
Fig. 2 with Bergeron’s model is given in this appendix. Equations the computations involved per phase with the controller are: four
(5) and (6) are solved by the observer. The observer computation multiplication, three addition, two subtraction, and two move
time in this case following the procedure of Section III-B is given operation. Hence, referring Table II, the total computation time
by (Tobc = (1.1 + 1000138 τ taken by the PR controller is nearly 0.8 μs for the selected Zynq
Tob ) μs). As now instead of one VSI, we
need to control two VSIs, effectively controller computation processor.
time (Δt) in (18) will become double. Equations (19)–(21) will APPENDIX C
be modified as follows:
2
10 Tob TABLE VI
Tsw ≥ 2 − 1.66T − 0.114τ (30) CONSTANTS OF BERGERON’S MODEL
Tob ob
2
10 Tob
Tsw ≥ (31)
2
Tob − 1.66Tob − 114
and
2
10 Tob
Tsw ≥ . (32)
2
Tob − 1.66Tob − 228 TABLE VII
ADDITIONAL OBSERVER CONSTANTS
Rest of the procedure, as in Section III, remains same.

APPENDIX B
For the ease of digital implementation and to reduce the cost
of the emulator system, both the observer and the controller for
the PA have been implemented on a single embedded platform.
In (18), the parameter Δt is used to account for the time taken
for sensing and signal filtering, closed-loop control and duty
cycle updation, and protection in the selected Zynq PS. The
digitization of the PR controller is given below. To eliminate
the necessity of online calculation of trigonometric functions or APPENDIX D
maintaining a look up table, Two Integrator with Forward and We have compared the computational burden of the numer-
Backward (TIFB) Euler is used to implement the PR controller ical scheme used in [19] with Bergeron’s model when applied
in the digital platform. The block diagram structure of the PR to the emulation of energization of a long transmission with
controller in continuous time domain is shown in Fig. 20. After one end terminated with a shunt reactor in this appendix. The
discretization by TIFB, the difference equations of the resonant telegrapher’s equation of a long transmission line is given by
integrator (RI) can be expressed as ∂i(J) ∂v(J)
   Ri(J) + L + =0 (35)
x1(J) [k] = x1(J) [k − 1] + Kir × i∗se(J) [k] − ise(J) [k] ∂t ∂x
  ∂v(J) ∂i(J)
 Gv(J) + C + = 0. (36)
× Tsw − x2(J) [k − 1] × ω◦ × Tsw (33) ∂t ∂x

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 MAZUMDAR AND BASU: HARDWARE EMULATION OF ENERGIZATION OF A LONG TRANSMISSION LINE 9279

Following the procedure of Section III-B, the observer computa-

tion time in this case is given by (Tobc = Tclk(PS) [95 + 103N ]).
From (11), Tobc[19] > Tobc(Bergeron) for N > 2. Note, typically N
is relatively large (minimum value of which is 27 in the example
used in this article).
Fig. 21. Space discretization by the numerical scheme using method of char-
acteristics used in [19].

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 9280 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 9, SEPTEMBER 2020

[20] J. L. Naredo, A. C. Soudack, and J. R. Marti, “Simulation of transients Kaushik Basu (Senior Member, IEEE) received the
on transmission lines with corona via the method of characteristics,” IEE B.E. degree from the Bengal Engineering and Science
Proc.—Gener., Transmiss., Distrib., vol. 142, no. 1, pp. 81–87, Jan. 1995. University, Shibpur, India, in 2003, the M.S. degree
[21] J. M. Carrasco et al., “Power-electronic systems for the grid integration of in electrical engineering from the Indian Institute of
renewable energy sources: A survey,” IEEE Trans. Ind. Electron., vol. 53, Science, Bangalore, India, in 2005, and the Ph.D.
no. 4, pp. 1002–1016, Jun. 2006. degree in electrical engineering from the University
[22] H. W. Dommel, “Digital computer solution of electromagnetic transients of Minnesota, Minneapolis, MN, USA, in 2012.
in single-and multiphase networks,” IEEE Trans. Power Apparatus Syst., He was a Design Engineer with Cold Watt India
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(EMTP Theory Book). Portland, OR, USA: Bonneville Power Admin., 2015. He is currently an Assistant Professor with the
1986. Department of Electrical Engineering, Indian Institute of Science. He has been
[24] L. H. Crockett, R. A. Elliot, M. A. Enderwitz, and R. W. Stewart, The an author and co-author of several technical papers published in peer-reviewed
Zynq Book: Embedded Processing With the ARM Cortex-A9 on the Xilinx journals and conferences. His research interests include various aspects of the
Zynq-7000 All Programmable SoC. Glasgow, U.K., Strathclyde Academic general area of power electronics.
Media, 2014. Dr. Basu is the Founding Chair of IEEE Power Electronics Society and IES
[25] Manual on Transmission Planning Criteria, Central Elect. Authority, New Bangalore Chapter.
Delhi, India, Jan. 2013.

Sushmit Mazumdar received the B.E.(Hons.) de-

gree in electrical engineering from the Indian Institute
of Engineering Science and Technology, Shibpur,
India, in 2015, and the M.Tech.(Research in Power
Electronics) degree in electrical engineering from
the Indian Institute of Science, Bangalore, India, in
2019.
From 2015 to 2016, he was a Graduate Engineer
Trainee with M. N. Dastur and Company Pvt. Ltd.
He is currently an Analog Design Engineer with the
Power Management IC Group of Intel Corporation,
Bangalore, India. His research interests include design of high-frequency power
converters, hardware emulation, grid integration of distributed generation, and
electric drives.

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