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12-Verilog HDL Coding and Summary of Module-3-12-06-2024

12-Verilog HDL coding and Summary of Module-3-12-06-2024

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sedhupathirajendranofficial
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5 views

12-Verilog HDL Coding and Summary of Module-3-12-06-2024

12-Verilog HDL coding and Summary of Module-3-12-06-2024

Uploaded by

sedhupathirajendranofficial
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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HALF ADDER

a b sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Gate level Modelling

module halfadder_str(a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

Data flow Modelling

module halfadder_df(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

Behavioural Modelling (If else)

module halfadder_beh( A, B, S, Cout);

input wire A, B;
output reg S, Cout;

always @(A or B )
begin
if(A==0 && B==0)
begin
S=0;
Cout=0;
end
else if(A==0 && B==1)
begin
S=1;
Cout=0;
end

else if(A==1 && B==0)


begin
S=1;
Cout=0;
end

else if(A==1 && B==1)


begin
S=0;
Cout=1;
end

end

endmodule

Behavioural Modelling (Case statement)

module halfadder_beh(A, B, S, Cout);


input wire A, B;
output reg S, Cout;

always @(A or B)
begin

case ({A,B})

2'b00: begin S = 0; Cout = 0; end


2'b01: begin S = 1; Cout = 0; end
2'b10: begin S = 1; Cout = 0; end
2'b11: begin S = 0; Cout = 1; end
endcase

end

endmodule
HalfAdder Test bench

module halfadder_test;
reg a,b;
wire sum,carry;
halfadder_df ha1(a,b,sum,carry);
initial
begin
a=0;
b=0;
#10 b=1;
#10 a=1;
#10 b=0;
#50 $stop;
end
endmodule
FULL ADDER

A B cin Sum cout


0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Gate level Modelling

module fulladder_str(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire x1,x2,x3;
xor(x1,a,b);
xor(sum,x1,cin);
and(x2,x1,cin);
and(x3,a,b);
or(cout,x2,x3);
endmodule

Data flow Modelling

module fulladder_df(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|cin&(a^b);
endmodule
Behavioural Modelling (If else)

module fulladder_beh( A, B, Cin, S, Cout);

input wire A, B, Cin;


output reg S, Cout;

always @(A or B or Cin)


begin
if(A==0 && B==0 && Cin==0)
begin
S=0;
Cout=0;
end

else if(A==0 && B==0 && Cin==1)


begin
S=1;
Cout=0;
end

else if(A==0 && B==1 && Cin==0)


begin
S=1;
Cout=0;
end

else if(A==0 && B==1 && Cin==1)


begin
S=0;
Cout=1;
end

else if(A==1 && B==0 && Cin==0)


begin
S=1;
Cout=0;
end

else if(A==1 && B==0 && Cin==1)


begin
S=0;
Cout=1;
end

else if(A==1 && B==1 && Cin==0)


begin
S=0;
Cout=1;
end

else if(A==1 && B==1 && Cin==1)


begin
S=1;
Cout=1;
end

end

endmodule

Behavioural Modelling (Case statement)

module full_adder_beh(A, B, Cin, S, Cout);


input wire A, B, Cin;
output reg S, Cout;

always @(A or B or Cin)


begin

case ({A,B,Cin})

3'b000: begin S = 0; Cout = 0; end


3'b001: begin S = 1; Cout = 0; end
3'b010: begin S = 1; Cout = 0; end
3'b011: begin S = 0; Cout = 1; end
3'b100: begin S = 1; Cout = 0; end
3'b101: begin S = 0; Cout = 1; end
3'b110: begin S = 0; Cout = 1; end
3'b111: begin S = 1; Cout = 1; end
endcase

end

endmodule
FullAdder Test bench

module fulladder_test;
reg a,b,cin;
wire sum,cout;
fulladder_df fa1(a,b,cin,sum,cout);
initial
begin
a=0;
b=0;
cin=0;

#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=0;
#10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule
HALF SUBTRACTOR

a B diff borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Gate level Modelling

module halfsub_str(a,b,diff,borrow);
input a,b;
wire x;
output diff,borrow;
xor(diff,a,b);
not(x,a);
and(borrow,x,b);
endmodule

Data flow Modelling

module halfsub_df(a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff=a^b;
assign borrow= (~a)&b;
endmodule

Behavioural Modelling (If else)

module halfsub_beh( A, B, D,Borrow);

input wire A, B;
output reg D, Borrow;

always @(A or B )
begin
if(A==0 && B==0)
begin
D=0;
Borrow=0;
end

else if(A==0 && B==1)


begin
D=1;
Borrow=1;
end

else if(A==1 && B==0)


begin
D=1;
Borrow=0;
end

else if(A==1 && B==1)


begin
D=0;
Borrow=1;
end

end

endmodule

Behavioural Modelling (Case statement)

module halfsub_beh(A, B, D, Borrow);


input wire A, B;
output reg D, Borrow;

always @(A or B)
begin

case ({A,B})

2'b00: begin D = 0; Borrow = 0; end


2'b01: begin D = 1; Borrow = 0; end
2'b10: begin D = 1; Borrow = 0; end
2'b11: begin D = 0; Borrow = 1; end
endcase
end

endmodule
Halfsubtractor Test bench

module halfadder_test;
reg a,b;
wire d,borrow;
halfadder_df ha1(a,b,d,borrow);
initial
begin
a=0;
b=0;
#10 b=1;
#10 a=1;
#10 b=0;
#50 $stop;
end
endmodule
FULL SUBTRACTOR

A B bin diff bout


0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Gate level Modelling

module fullsub_str(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
wire x1,x2,x3,x4,x5;
xor(x1,a,b);
xor(diff,x1,bin);

not(x2,a);
and(x3,b,x2);

not(x4,x1);
and(x5,bin,x4);

or(bout,x3,x5);

endmodule
Data flow Modelling

module fullsub_df(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
assign diff=a^b^bin;
assign bout=((~a)&b)|bin&(~(a^b));
endmodule

Behavioural Modelling (If else)

module fullsub_beh( A, B, Bin, D, Bout);

input wire A, B, Bin;


output reg D, Bout;

always @(A or B or Bin)


begin
if(A==0 && B==0 && Bin==0)
begin
D=0;
Bout=0;
end

else if(A==0 && B==0 && Bin==1)


begin
D=1;
Bout=1;
end

else if(A==0 && B==1 && Bin==0)


begin
D=1;
Bout=1;
end

else if(A==0 && B==1 && Bin==1)


begin
D=0;
Bout=1;
end

else if(A==1 && B==0 && Bin==0)


begin
D=1;
Bout=0;
end

else if(A==1 && B==0 && Bin==1)


begin
D=0;
Bout=0;
end

else if(A==1 && B==1 && Bin==0)


begin
D=0;
Bout=0;
end

else if(A==1 && B==1 && Bin==1)


begin
D=1;
Bout=1;
end

end

endmodule

Behavioural Modelling (Case statement)

module full_adder_beh(A, B, Bin, D, Bout);


input wire A, B, Bin;
output reg D, Bout;

always @(A or B or Bin)


begin

case ({A,B,Bin})

3'b000: begin D = 0; Bout = 0; end


3'b001: begin D = 1; Bout = 1; end
3'b010: begin D = 1; Bout = 1; end
3'b011: begin D = 0; Bout = 1; end
3'b100: begin D = 1; Bout = 0; end
3'b101: begin D = 0; Bout = 0; end
3'b110: begin D = 0; Bout = 0; end
3'b111: begin D = 1; Bout = 1; end
endcase

end

endmodule

FullSubtractor Test bench

module fulladder_test;
reg a,b,bin;
wire d,bout;
fullsub_df fa1(a,b,bin,d,bout);
initial
begin
a=0;
b=0;
cin=0;

#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=0;
#10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule

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