12-Verilog HDL Coding and Summary of Module-3-12-06-2024
12-Verilog HDL Coding and Summary of Module-3-12-06-2024
a b sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
module halfadder_str(a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
module halfadder_df(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
input wire A, B;
output reg S, Cout;
always @(A or B )
begin
if(A==0 && B==0)
begin
S=0;
Cout=0;
end
else if(A==0 && B==1)
begin
S=1;
Cout=0;
end
end
endmodule
always @(A or B)
begin
case ({A,B})
end
endmodule
HalfAdder Test bench
module halfadder_test;
reg a,b;
wire sum,carry;
halfadder_df ha1(a,b,sum,carry);
initial
begin
a=0;
b=0;
#10 b=1;
#10 a=1;
#10 b=0;
#50 $stop;
end
endmodule
FULL ADDER
module fulladder_str(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire x1,x2,x3;
xor(x1,a,b);
xor(sum,x1,cin);
and(x2,x1,cin);
and(x3,a,b);
or(cout,x2,x3);
endmodule
module fulladder_df(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|cin&(a^b);
endmodule
Behavioural Modelling (If else)
end
endmodule
case ({A,B,Cin})
end
endmodule
FullAdder Test bench
module fulladder_test;
reg a,b,cin;
wire sum,cout;
fulladder_df fa1(a,b,cin,sum,cout);
initial
begin
a=0;
b=0;
cin=0;
#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=0;
#10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule
HALF SUBTRACTOR
a B diff borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
module halfsub_str(a,b,diff,borrow);
input a,b;
wire x;
output diff,borrow;
xor(diff,a,b);
not(x,a);
and(borrow,x,b);
endmodule
module halfsub_df(a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff=a^b;
assign borrow= (~a)&b;
endmodule
input wire A, B;
output reg D, Borrow;
always @(A or B )
begin
if(A==0 && B==0)
begin
D=0;
Borrow=0;
end
end
endmodule
always @(A or B)
begin
case ({A,B})
endmodule
Halfsubtractor Test bench
module halfadder_test;
reg a,b;
wire d,borrow;
halfadder_df ha1(a,b,d,borrow);
initial
begin
a=0;
b=0;
#10 b=1;
#10 a=1;
#10 b=0;
#50 $stop;
end
endmodule
FULL SUBTRACTOR
module fullsub_str(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
wire x1,x2,x3,x4,x5;
xor(x1,a,b);
xor(diff,x1,bin);
not(x2,a);
and(x3,b,x2);
not(x4,x1);
and(x5,bin,x4);
or(bout,x3,x5);
endmodule
Data flow Modelling
module fullsub_df(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
assign diff=a^b^bin;
assign bout=((~a)&b)|bin&(~(a^b));
endmodule
end
endmodule
case ({A,B,Bin})
end
endmodule
module fulladder_test;
reg a,b,bin;
wire d,bout;
fullsub_df fa1(a,b,bin,d,bout);
initial
begin
a=0;
b=0;
cin=0;
#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=0;
#10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule