JISCE / UG / CSE / R18 / EVEN / SEM-4 / CS401 / 2022-23

COMPUTER ARCHITECTURE
CS401
TIME ALLOTTED: 3 HOURS FULL MARKS: 70
The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as practicable

GROUP – A
(Multiple Choice Type Questions)
1. Answer any ten from the following, choosing the correct alternative of each question: 10×1=10
Marks CO No.
(i) Which of the following is a type of computer architecture? 1 1
(a) Microarchitecture
(b) Harvard Architecture
(c) Von-Neumann Architecture
(d) All of the mentioned
(ii) RISC stands for ____________. 1 2
(a) Reduce Instruction Set Computer
(b) Risk Instruction Sequential Compilation
(c) Risk Instruction Source Compiler
(d) None of the above
(iii) The VLIW architecture follows ___________ approach to 1 3
achieve parallelism.
(a) SISD
(b) MIMD
(c) MISD
(d) SIMD
(iv) What does EEPROM stands for? 1 2
(a) Electrically Erasable and Programmable Read-Only
Memory
(b) Electronically Erasable and Programmable Read-
Only Memory
(c) Electrically Enabled and Programmable Read-Only
Memory
(d) None of the above
(v) Both the CISC and RISC architectures have been 1 2
developed to reduce the __________.
(a) Time delay
(b) Semantic gap
(c) Cost
(d) All of the mentioned
(vi) What does MIMD stand for? 1 3
(a) Multiple Instruction Memory Data
(b) Multiple Instruction Multiple Data
(c) Memory Instruction Multiple Data
(d) Memory Information Memory Data

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 JISCE / UG / CSE / R18 / EVEN / SEM-4 / CS401 / 2022-23 JISCE / UG / CSE / R18 / EVEN / SEM-4 / CS401 / 2022-23

(vii) What does VLIW stands for? 1 3 5. (a) Define Cache memory. 3 2
(a) Very Long Instruction Width
(b) Very Large Instruction Word (b) Define MIPS. 2 2
(c) Very Long Instruction Width 6. Describe omega interconnection network. 5 3
(d) Very Long Instruction Word
(viii) Which of the following is the full-form of CISC? 1 3 GROUP – C
(a) Complex Instruction Sequential Compilation (Long Answer Type Questions)
(b) Complete Instruction Sequential Compilation Answer any three from the following 3×15=45
(c) Computer Integrated Sequential Compiler
Marks CO No.
(d) Complex Instruction Set Computer
(ix) Computer address bus is ____________. 1 2 7. (a) Describe the differences between RAM and ROM. 5 2
(a) Multidirectional (b) Describe EPROM. 5 2
(b) Bidirectional (c) Describe the differences between volatile and non-volatile 5 2
(c) Unidirectional memory.
(d) None of the above 8. (a) What is Cache miss? 2 2
(x) Which of the following computer bus connects the CPU to 1 2
a memory on the system board? (b) Describe memory hierarchy with suitable diagram. 8 2
(a) Expansion bus (c) Describe Optical memory. 5 2
(b) Width bus 9. (a) Describe RISC. 5 2
(c) System bus (b) Write a short note on MIMD. 5 3
(d) None of the above (c) What is Hit ratio? 5 2
(xi) The difference in the address and data connection between 1 2 10. (a) Apply Booth’s algorithm: (-7) * (-3). 8 2
DRAM’s and SDRAM’s is __________. (b) Describe ALU with suitable diagram. 5 2
(a) The requirement of more address lines in SDRAM’s (c) What is the purpose of Program Counter? 2 2
(b) The usage of a buffer in SDRAM’s 11. (a) What is paging? 5 2
(c) The usage of more number of pins in SDRAM’s (b) Describe FIFO. 5 2
(d) None of the mentioned (c) What is Page fault? 5 2
(xii) Which of the following is a group of bits that tells the 1 2
computer to perform a particular operation?
(a) Accumulator
(b) Register
(c) Instruction code
(d) None of the above
GROUP – B
(Short Answer Type Questions)
Answer any three from the following 3×5=15
Marks CO No.
2. (a) State Amdahl’s law. 3 1
(b) What kinds of problems do we solve with Amdahl’s law? 2 1
3. (a) What is Data Hazard? 2 1
(b) How can we solve Structural Hazards? 3 1
4. (a) What do you mean by Instruction Fetching? 3 1
(b) What is Flash Memory? 2 2

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