INTERRUPT SYSTEM

Interrupt input/output transfer is a method of data transfer where by an external device inform
the processor that it is ready for communication and it require attention. It can be intiated at
any time without refference to the system clock i.e It is asynchronous
The peripheral requiring service interrupt the microprocessor system using an Interrupt
signal.Interrupt signals are used to synchronise the microprocessor with the peripheral device
because the peripheral are slower.The response to the interrupt request is directed or
controlled by the microprocessor.
IMPORTANCE (NEED) FOR INTERRUPT SYSTEM
1. Synchronisation
Interrupt signals relieves the microprocessor off the burden of polling an input /output
device over and over to see if it require service
2. Real time response
Interrupt allows the microprocessor to respond rapindly to a situation requiring
immediate attention
INTERRUPT OPERATION /CYCLES
When a peripheral wishes to be serviced it sends an interrupt request signal ( INTR for the
8085) to the PIO( PROGRAMMABLE INPUT/OUTPUT PORT) or the system itself. In
response the PIO or the system generate a control signal called interruprt acknowlegment
signal ( INTA for the 8085)
If an interrupt signal is present the following events occurs;
1.Microprocessor complete executing the current instruction in the main program
2.Save the address in the progam counter and the content of the microprocessor registers
3.Branch to an ISR(Interrupt Service Routine) to service the peripheral device
4.Execute the ISR to give the peripheral the service required
5.Restore the content of the PC and processor register to the values that existed before the
interrupt
6.Continue executing the main program
 This process can be illustrated as follow

Continues to execute
Normal
Interrupt occurs main program
Program

Retrieve PC & registers

contents

CPU completes executing current Fetch return address of

instruction saves return address main program
& processor registers contents

Branch to ISR Execute ISR of particular

interrupt

TYPES OF INTERRUPT
1.VECTORED INTERRUPT
2.POLLED INTERRUPT

POLLED INTERRUPT
In polled interrupt system the processor examine every possible source of the interrupt signal
before a decision is made about the address of an ISR to which the cpu is to be directed.
In this system all the device interrupt the microprocessor on the same interrupt line (INTR for
8085) hence reffered to as multiple device single interrupt level system. Due to this the
microprocessor interrogate (poll) all the devices connected to it to be able to identifies the
device that caused the interrupt.The interrupting input/output devices are logically ORed and
the single output generated is connected to the microprocessor.

INTERRUPT
D1 LINE
INTR 8085
D2
D3 microprocessor
i.e
TRUE TABLE
D1 D2 D3 OUTPUT
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

When a device interrupt the processor has to execute the following steps inorder to process
1.Finish executing the current instruction
2.Save the content of PC and processor register content
3. Identifies the device that caused the interrupt by reading the status to find the flag that is set
4.Branch to the Interrupt Service Routine (ISR) associated tpo the device and perform data
transfer
5.Enable the interrupt system so that a further interrupt may be recognised
6.Restore the content of the PC and the processor register
7.Return to the main program

N/B In real life even when a microprocessor provide only one interrupt level, a chip called
8259 PIC (Peripheral Interrupt Controller) is used to provide additional interrupt level.
TYPE OF POLLED SYSTEM
The microprocessor can interrogate the peripheral devices using to methods. i .e
1.Software polling
2.Hardware polling
SOFTWARE POLLING
In this method, the interrogating is done by software means whereby the microprocessor
enter into a subroutine that immediately begins polling the external devices to determine the
device requesting for the interrupt.
The flow chart below shows a software polling of a peripheral device

INTERRUPT

Save contents of CPUregister and PC contents

Determine couse of interrupt

Is device
Service device A
A flag set Yes

No
Is device B
interrupt flag
Yes Service device B
set

Restore the saved contents of CPU

and PC

Enable interrrupt line

Return
HARDWARE POLLING
An alternative of software polling is to use a hardware arbitrate circuit where CPU respond to
an interrupt request by sending out on a separate line an interrupt acknowledgement signal to
each device. Only the device that generated the original interrupt signal will respond by
directing the microprocessor to it ISR.
In hardware polling the processor and its external set of devices are physically interconnected
in such a manner that the cpu may interrrogate the device automatically inorder to obtain the
address of the interrupting device.
One commonly used mechanism for hardware polling is the daisy chainning (hardwired).
The figure below shows daisy chainning

INTR

INTA INTA

MICRO Device 1 Device 2

PROCESSOR

DATA BUS

When the processor is ready to honour an interrupt request the cpu automatically sends an
acknowledgement signal INTA to the I/O devices on a wire that is daisy chained from device
to device.
As the signal move down the chain it interrogate each device to determine whether the device
is active or the interrupt flag is set. If the device is in inactive state the INTA signal is
permitted to move to the next device until the active device is recognised.
When the active device is recognised, it captures the INTA signal and prevent it from
propagating down the chain.This device then direct the cpu to its ISR and the device is
serviced.
ADVANTAGES OF HARDWARE POLLING OVER SOFTWARE POLLING
1.It provide a rapid mechanism for identifying the highest priotised device requiring service
2.No time consuming executing a subroutine for polling
3.It permits large number of devices to be connected to the cpu on the same line
DISADVANTAGES
1.Logic delay experienced by the acknowledgement signal INTA as it moves down the chain

DISADVANTAGES OF POLLING OVER VECTORED INTERRUPT

1. Does not respond quickly to catastrophic events
2. There is time wastage in polling
VECTORED INTERRUPT
Where many I/O device are involved and faster interrupt response is needed, polling may not
be a practical solution.In such a case a system in which each device identifies itself at the time
of interrupt is desired.
This implies that the processor should have a set of interrupt levels and to this a unique device
is connnected.Thus when a device interrupt the processor knows which device is active and
branches (vector) to a specific memory location (ISR) that has been assigned to that interrupt
level.Such a system is reffered to as Vectored Interrupt or multiple devices multi level
system.
The 8085 microprocessor has FOUR such levels i.e
RST 4.5 (TRAP)
RST 5.5
RST 6.5
RST 7.5

8085 INTERRUPT FACILITIES

The 8085 has a total of FIVE hardware interrupt i.e INTR, RST 4.5, RST5.5, RST6.5 and
RST7.5 INTR is a polled interrupt whereas the others are vectored interrupt.

It has 8 software interrupt i.e RST 0 ,RST1---------------------------------------RST 7.

SOFTWARE INTERRUPT

They are also known as restart instruction (mnemonic RST) since they cause the cpu to be
restarted at a specific vectored address. All RST interrupt whether hadrware or software are
vectored.Only INTR is a polled interrupt/
The RST instructions are like vector because they points to specific location (vector location )
in memory i.e
Interrupt location opcode(Hex) Effect Vectore location (Hex)
RST 0 C7 CALL 0000H 0000H
RST 1 CF CALL 0008H 0008H
RST 2 D7 CALL 0010H 0010H
RST 3 DF CALL 0018H 0018H
RST 4 E7 CALL 0020H 0020H
RST 5 EF CALL 0028H 0028H
RST 6 F7 CALL 0030H 0030H
RST 7 FF CALL 0038H 0038H

Each of the interrupt RST 0 ---------------------RST 7 can be accessed by use of a software

instruction having the opcode listed when a logic 1 is applied by an interrupting device on the
INTR pin of the CPU. When logic 1 is received by a cpu it sends out a logic 0 on the INTA
control line to acknowledge the request.In response to logic 0 on the INTA line the requesting
device places the opcode of the required RST on the data bus.

e.g If the interrupting device wishes to vector the cpu to the address corresponding to RST 6
interrupt it places a hex value on the data bus .This causes the CPU to vector to the address
0030H.

The lower byte of the address to which the cpu is to be vectored by an RST is given by;

Decimal equivalent of RST number × 8

e.g RST 4 = 4 × 8 = 32

3210 =20H

Therefore the vector address =0020H

8085 HARDWARE RESTART INTERRUPT

It has five hardware interrupt input i.e INTR and this need INTA signal to be serviced. The
other 4 hardware restart are all vectored because the necessary hardware is already
implemented inside the 8085 microprocessor.

By connecting the hardware restart pin to the peripheral device one can use interrupt driven
input/output data transfer instead of progammed or polled input/output transfer.

Interrupt driven input/output data transfer is a process of data transfer whereby an external
device can inform the cpu that it is ready for communication and it requires attention.

When any of the 8085 pin are active the internal circuit of the 8085 produces a hardware
CALL to a predetermined vector location. Hence the 4 hardware restart (RST 4.5, RST5.5,
RST6.5, RST7.5 ) are all vectored interrupt.

Vector location for the hardware restart are axactly half way between software location i.e
 INTERRUPT VECTOR LOCATION

RST 4.5 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

INTR No vector location (Dictated by the interrupting device)

INTERRUPT INSTRUCTION AND CONTROL

Microprocessor normally has the facilities to enable the interrupt line and so allows the CPU
to respond to an interrupt signal or disable the interrupt line forcing the CPU to ignore any
interrupt.

Interrupt control is normally achieved by setting or resetting the interrupt status flag by use of
two instructions i.e DI (Disable Interrupt) and EI (Enable Interrupt). If the interrupt facility
has previously been enabled i.e (the status flag is reset) and an interrupt occurs the flag is set.
This has an effect of disabling the interrupt line and preventing the cpu from responding to
any other interrupt until the current Interrupt Service Routine has been completed.

After final execution of all instructions in the Interrupt Service Routine, the interrupt line is
enabled by EI instruction and this allows the cpu to respond to the next interrupt if it occurs.

Return (RET) is the last interrupt instruction in the ISR and it causes the cpu to return to the
main program.

FORMS OF INTERRUPT

1.NON MASKABLE

It is an interrupt that cannnot be disabled by means of an instuction (DI) in the

program.Therefore they need not be enabled by EI instruction. It is used to handle situation of
the highest priority (catastrophic events) such as power failure, parity error etc that requires
immediate attention. The 8085 has one non- maskable interrupt pin i.e RST 4.5 (TRAP.

When a non-maskable interrupt occurs, the cpu interrupt the operation of the main program
and transfer control to an ISR that deals with that interrupt.

2.MASKABLE INTERRUPT

This is one that can be masked out (Disabled ) by means of an instruction in the main
program. They are enabled under program control. They handle less catastrophic events. 8085
has three maskable hardware interrupts line on ist chip i.e RST 5.5 , RST6.5, RST7.5 . It also
has 8 maskable software interrupts i.e RST 0-----------------------------------------RST7.

A maskable interrupt is granted by the cpu if the interrupt line has been enabled by EI
instruction in the program.However if the interrupt line has been disabled by DI instruction in
the program the interrupt is ignored.
8085 INTERRUPT PRIORITY

Since each of the interrupt pin is connected to a different device, it is necessary for the
processor to ensure some means of priority when dealing with multiple devices. The order of
priority is ussually as follows:
RST 7.5 Highest priority
RST 6.5
RST 5.5
INTR lowest priority
NB Trap (RST 4.5) has the highest priority

INTERRUPT MASK/ I REGISTER

There are two processor registers associated with interrupt reffered to as mask register. One of
this register can be written into by executing the SIM instruction (Set Interrupt Mask) while
the other can be read from using the RIM (Read Interrupt Mask) instruction.

When the SIM instruction is executed the content of the accumulator are transferd to a mask
register.The information is bit mapped as shown below in the mask register.

SOD SOE R7.5 MSE M7.5 M6.5 M5.5

( Undifined)

Serial out Serial out RST 7.5 Mask Set Enable RST 7.5
Data Enable 0= Enable 0=Disable RST 6.5
1= Disable 1=Enable RST 5.5
0=unmask
1=mask
0=No serial data output
1=Serial output data

The SIM instruction output the content of the accumulator to define the interrupt mask bit and
the serial output data line. A logic 1 on any of the bit 0,1,2 mask out the bit whileas logic 0 un
mask the bit. The mask set enable MSE enable bits 0,1 & 2
NB The INTR interruptis not affected by SIM instruction.

The instruction sequence for enabling all the RST interrupt are as follows
EI
MVI A d8 ( any 8 bit data)
SIM
 or
MVI A d8
SIM
EI
The following instructions enable (unmask) RST 7.5 and RST 5.5 and disable (mask) RST 6.5
MVI A 0EH
SIM
EI
i.e
D7 D6 D5 D4 D3 D2 D1 D0
SOD SOE R 7.5 MSE M 7.5 M 6.5 M 5.5
0 0 0 1 1 1 0

ASSIGNMENT
Using the mask register describe which of the three vector interrupt will be masked or
unmasked by the following instruction
I MVI A 1AH
SIM
EI

II MVI A 09H
SIM
EI

The RIM instruction (Read Interrupt Mask ) load the accumulator with 8- bits to indicate
current status of the interrupt mask, the interrupt enable, the pending interrupt and serial input
data.
i.e
SID I 7.5 I 6.5 I 5.5 I.E M 7.5 M 6.5 M 5.5

Serial input pending interrupt Interrupt Interrupt bits for RST

Data Enable
Flag