IC APPLICATIONS & VLSI LAB R18 Regulation

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

IC APPLICATIONS & VLSI LAB MANUAL

B.TECH (ECE) –V SEMISTER

Prepared by

Mrs.M.Sirin Kumari
Assistant Professor, ECE

CMR COLLEGE OF ENGINEERING & TECHNOLOGY

(AUTONOMOUS)
Kandlakoya, Medchal Road, Hyderabad-501 401
2019-20

Department of ECE, CMRCET 1

IC APPLICATIONS & VLSI LAB R18 Regulation

LIST OF EXPERIMENTS
PART -1

EXP. PAGE
NO NAME OF THE EXPERIMENT NO
Introduction 03-05
1 Adder, Subtractor ,Comparator using IC 741 op-amp Trainer Kit 06-10
2 Integrator and Differentiator using IC 741 op-amp Trainer Kit 11-15
3 Active Low pass & High pass Butterworth (second order) Trainer Kit 16-21
4 RC phase shift & Wein-Bridge Oscillators using IC 741 op-amp Trainer Kit 22-27
5 IC 555 Timer in Mono stable Trainer Kit 28-30
6 Voltage regulator IC 723,3terminal voltage regulator 31-35
7805,7809,7812,7905,7909,7912 Trainer Kit

EXPERIMENTS BEYOND THE SYLLABUS

1 3-8 Decoder (74LS138) 37-39
2 4-bit Comparator(74LS85) 40-41
3 D- Flip Flop(74LS74)and JK Master Slave Flip Flop (74LS73) 42-47
4 Universal Shift Register(74LS194/195) 48-51

Department of ECE, CMRCET 2

IC APPLICATIONS & VLSI LAB R18 Regulation

INTRODUCTION
STUDY OF OP-AMPs IC 741, IC 555, IC 565 FUNCTIONING, PARAMETERS & SPECIFICATIONS

AIM: To Study about IC741 (Op-Amp), IC555 (Timer), IC565 (PLL).

COMPONENTS: IC741, IC555, IC565.

IC741 : (Operational Amplifier)

Symbol

Fig.a
Pin Configuration

Fig.b

Maximum Ratings:
Supply Voltage  18V
Internal Power Dissipation 310mw
Differential input voltage  30V
Input Voltage  15V
Operating temperature range 0ºC to 70ºC

Applications:
Non-inverting amplifier
Inverting amplifier
Integrator
Differentiator

Department of ECE, CMRCET 3

IC APPLICATIONS & VLSI LAB R18 Regulation

Low Pass, High Pass, Band pass and Band Reject Filters
Features:
No External frequency compensation is required
Short circuit Protection
Off Set Null Capability
Large Common mode and differential Voltage ranges
Low Power Dissipation
No-Latch up Problem
741 is available in three packages :- 8-pin metal can, 10-pin flat pack and 8 or 14-pin DIP

IC 555 : (Timer )
Pin Configuration

Fig.(c) Fig(d)
Functional block diagram:

Fig(e)

Specifications:
Supply Voltage 5V to 18V
Maximum Current rating 200mA
Minimum Triggering Voltage -(1/3) VCC
Operating temperature range 0ºC to 70ºC

Applications:

Department of ECE, CMRCET 4

IC APPLICATIONS & VLSI LAB R18 Regulation

1. Astable Multivibrator : Schmitt trigger, Free running ramp Generator, etc.,

2. Monostable Multivibrator: Frequency divider, Pulse structure
3. Bi stable multivibrator

Features :
555 timers are reliable, easy to use and low cost. The device is available as an 8 pin metal can, an
8 –pin mini DIP or a 14 Pin DIP

IC565 : ( Phase locked loop):

Pin configuration:

Fig.(f) Fig(g)
Specifications:
Minimum input for lock 1 mV
VCO Frequency 0.5MHz
Lock range 60%
VCC Minimum 10V
VCC Maximum 26 Volts

Applications:
Frequency multiplier,
Frequency Shift Keying (FSK) Demodulator
Frequency Translation or shifting
Frequency demodulation.

Features:
Extreme Stability of Center frequency
Very high linearity of De modulated output
TTL Compatible square wave output
Highly Linear tri angular output
Loop can be broken to insert digital frequency divider

Department of ECE, CMRCET 5

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO : 1

ADDER, SUBTRACTOR & COMPARATOR CIRCUITS USING 741 OP-AMP

AIM : To design an adder, Subtractor & comparator circuits using OP- AMP 741 IC.

APPARATUS : Bread Board.

741IC.
Resistors – R1 =10KΩ - 5No’s.
Connecting wires.
Dc Supply.
Signal Generator.
Multimeter.
CRO, Probes. Connecting Wires.
CIRCUIT DIAGRAM :
Adder :

Fig.(a)
Subtractor :

Fig.(b)

Comparator :

Department of ECE, CMRCET 6

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig.(c)

THEORY :

Adder : Adder circuit is a Summing Amplifier. Op-amp can be used to design a circuit whose
output is the sum of several input signals. Such a circuit is called a summing amplifier or a
summer. Summing amplifier can be classified as inverting & non-inverting summer depending
on the input applied to inverting & non-inverting terminals respectively. Fig shows an inverting
summer with two inputs. Here the output will be the linear summation of input voltages. Here the
feedback forces a virtual ground to exist at the inverting input . The output is equal to the negative
weighted sum of the input voltages. The summing operation depends exclusively on the sum of
the resistor ratios. Fig . shows the inverting configuration with three inputs Va, Vb, Vc depending
on the relationship between the feedback resistor RF and the input resistors Ra ,Rb and Rc , the
circuit can be used as either a summing amplifier, scaling amplifier, or averaging amplifier. By
connecting more than one input voltages to the inverting input, the resulting circuit is the Adder.
Va Vb Vc
I =------ + -------+ -------
Ra Rb Rc

V0 = - Rf.I

Va Vb Vc
V0 = -Rf ( ------+ ------+ ------- )
Ra Rb Rc

If Ra = Rb = R c = R

V0 = - (Rf/R) (Va +Vb + Vc)

This means that the output voltage is equal to the negative sum of all the inputs times the
gain of the circuit is called a summing amplifier. Obviously, when the gain of the circuit

is 1, that is , Ra = Rb = Rc = RF , the output voltage is equal to the negative sum of all input
voltages. Thus
V0 = - (Va + Vb + Vc)

Department of ECE, CMRCET 7

IC APPLICATIONS & VLSI LAB R18 Regulation

Subtractor : A subtractor is a circuit that gives the difference of the two inputs. Vo =V1-V2 ,
Where V1 and V2 are the inputs.
By connecting one input voltage V1 to inverting terminal and another input voltage V2 to the non
– inverting terminal then the resulting circuit is the Subtractor.
Output of a differential amplifier (subtractor) is given as
Vo=(-Rf/R1)(V1-V2)
If all external resistors are equal in value, then the gain of the amplifier is equal to 1. The output
voltage of the differential amplifier with a gain of 1 is
V0 = (V2-V1)
Thus the output voltage V0 is equal to the voltage V2 applied to the non – inverting
terminal minus the voltage V1 applied to the inverting terminal. Hence the circuit is called a
Subtractor.

Comparator : A Comparator is a non-linear signal processor. It is an open loop mode application

of Op-amp operated in saturation mode. Comparator compares a signal voltage at one input with
a reference voltage at the other input. Here the Op-amp is operated in open loop mode and hence
the input is ± Vsat. It is basically classified as inverting and non-inverting comparator. In a non
inverting comparator Vin is given to +ve terminal and Vref to –ve terminal. When Vin < Vref,
the output is –Vsat and when Vin > Vref, the output is + Vsat. In an inverting comparator input
is given to the inverting terminal and referenceis given to the non inverting terminal. The
comparator can be used as a zero crossing detector , window detector, time marker, phase meter.

Fig.(d)

PROCEDURE :
Adder :
1. Connect the adder circuit as shown in fig.(a) by connecting the appropriate resistors to 741 IC.
2. Switch on the trainer.
3. Apply dc voltages at each input terminals for V1 and V2 from the dc supply and check the
output voltage Vo at the output terminal.
4. Tabulate the readings.
5. Compare practical Vo with the theoretical output voltage Vo=-Rf[(V1/R1)+(V2/R2)].

Subtractor :
1. Connect the subtractor circuit as shown in fig.(b) by connecting the appropriate resistors to 741
IC.
2. Switch on the trainer.
3. Apply dc voltages at each input terminals for V1 and V2 from the dc supply and check the
output voltage Vo at the output terminal.
4. Tabulate the readings.
5. Compare the practical Vo with the theoretical output voltage Vo=(-Rf/R1)(V2-V1) value.

Comparator :

Department of ECE, CMRCET 8

IC APPLICATIONS & VLSI LAB R18 Regulation

1. connect the comparator circuit as shown in fig.(c)

2. Apply 1 KHz sine wave with 5 Vp-p at the inverting input terminal of 741 IC using a function
generator.
3. Apply 3V dc voltage as reference voltage at the non-inverting terminal of 741 IC.
3. Connect channel -1 of CRO at the input terminals and channel-2 of CRO at the output
terminals.
4. Observe the input sinusoidal signal in ch-1 and the corresponding output square wave in ch-2
of CRO.
5. Note the amplitude and timeperiods of Vin and Vo.
6. Plot the output square wave corresponding to sine input with Vref = 3V

TABULAR COLUMN;

Adder :

R1 = 10 K R2 = 10K Rf =10K
S.No V1 V2 Theoretical Practical Vo
Volts Volts Vo=-Rf[(V1/R1)+(V2/R2)] Volts

Subtractor :

R1 = R2 = Rf= 10K
S.No V1 V2 Theoretical Practical Vo
Volts Volts Vo=(-Rf/R1)(V2-V1) Volts

EXPECTED WAVEFORMS:
COMPARATOR INPUT & OUTPUT WAVEFORMS

Fig.(e)

Department of ECE, CMRCET 9

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig.(f)

RESULT : Verified the practical output voltage with theoretical value for adder and subtractor
circuits using 741IC. Plotted the output waveforms for comparator circuit using 741 IC for
positive and negative reference voltage.

VIVA VOCE:
1. What is an Op-Amp?
2. What are the different Linear IC Packages?
3. List five characteristics of an idal Op-Amp.
4. Define Common Mode Rejection Ratio.
5. What are the various DC Characteristics of an Op-Amp?

EXPERIMENT NO :2

Department of ECE, CMRCET 10

IC APPLICATIONS & VLSI LAB R18 Regulation

INTEGRATOR AND DIFFERENTIATOR CIRCUITS USING IC741 OP-AMP

AIM: To study the operation of the differentiator & Integrator and trace the output wave forms
for sine and square inputs.

APPARATUS: IC741 Op-Amp .

Resistors- 5.6K, 10K, 100K
Capacitors- 0.1 µF
Signal Generator.
CRO, Probes, Connecting wires
CIRCUIT DIAGRAM :
Differentiator:

Fig.(a)
Integrator :

Fig(b)

THEORY:
Integrator.
In the practical integrator to reduce the error voltage at the output, a resistor RF is connected across
the feedback capacitor CF. Thus, RF limits the low-frequency gain and hence minimizes the
variations in the output voltage.

Department of ECE, CMRCET 11

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig.(c)
The frequency response of the basic integrator is shown in the fig(c) fb is the frequency at
which the gain is 0 dB and is given by
fb = 1/2  R1Cf.
In this fig(c) is some relative operating frequency, and for frequencies f to fa the gain
RF/R1 is constant. However, after fa the gain decreases at a rate of 20 dB/decade. In other words,
between fa and fb the circuit of fig(b), acts as an integrator. The gain-limiting frequency fa is given
by
fa = 1/2  RfCf.

Generally, the value of fa and in turn R1Cf and RfCf values should be selected such that fa
< fb. For example, if fa = fb / 10, then Rf = 10R1. In fact, the fig(c), frequency response of basic
and practical integrators.
fa =1 / (2  RfCf ) and fb = /(2  RfCf).

The input signal will be integrated properly if the time period T of the signal is larger than
or equal to RfCf. i.e., T > RfCf
where RfCf = 1 / 2  fa.

Integrator has wide applications in

1. Analog computers used for solving differential equations in simulation arrangements.
2. A/D Converters

3. Signal wave shaping

4. Function Generators.
Differentiator:
The frequency response of the basic differentiator is shown in fig(c), in this fig(c), fa is
the frequency at which the gain is 0 dB and is given by
fa = 1/2  RfC1

Department of ECE, CMRCET 12

IC APPLICATIONS & VLSI LAB R18 Regulation

Both the stability and the high-frequency noise problems can be corrected by the addition
of two components: R1 and Cf, as shown in fig(a), This circuit is a practical differentiator, the
frequency response of which is shown in fig(c) by a dashed line.
From frequency f and fb, the gain increases at 20 dB/decade. However, after fb the gain
decreases at 20 dB/decade. This 40-dB/decade change in gain is caused by the R1C1 and RfCf
combinations. The gain-limiting frequency fb is given by
fb = 1 / 2  R1C1.

Where R1C1 = RfCf.

Thus R1C1 and RfCf help to reduce significantly the effect of high-frequency input,
amplifier noise, and offsets. Above all, it makes the circuit more stable by preventing the increase
in gain with frequency. Generally, the value of fb and in turn R1C1and RFCF values should be
selected such that fa<fb<fc

Where fa = 1 / 2  RfC1
fb = 1 / 2  R1C1 = 1 / 2  RfCf
fc = unity gain-bandwidth
The input signal will be differentiated properly if the time period T of the input signal is
larger than or equal to RfCf. That is, T> RfC1
Differentiator can be designed by implementing the following steps.
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Then, assuming a value of C1<1  F, calculate the value of Rf
2. choose fb = 20fa and calculate the values of R1and Cf so that R1C1=RfCf.

PROCEDURE:

Differentiator:
1. Connect the Differentiator circuit as shown in fig(a).
2.Apply 1 KHz sine wave with Vp-p = 5 V at the input terminals of the differentiator circuit using
function Generator.
3. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
4. Switch ON the kit, observe cosine wave at the output of the circuit on the CRO and record the
amplitude & timeperiod of Vin and Vo.
5. Now Apply square wave as input signal .
6. Observe the spike output voltage wave form on the CRO and note down the corresponding
values of amplitude and timeperiod of Vin & Vo.
7. Plot the output voltages corresponding to sine and square wave inputs.

Integrator:
1. Connect the integartor circuit as shown in fig(b).
2.Apply 1 KHz sine wave with Vp-p = 5 V at the input terminals of the differentiator circuit using
function Generator.
3. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
4. Switch ON the kit, observe cosine wave at the output of the circuit on the CRO and record the
amplitude & timeperiod of Vin and Vo.
5. Now Apply square wave as input signal .
6. Observe the triangular output voltage wave form on the CRO and note down the corresponding
values of amplitude and timeperiod of Vin & Vo.
7. Plot the output voltages corresponding to sine and square wave inputs.

Department of ECE, CMRCET 13

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPECTED WAVEFORMS:

Differentiator:

Integrator :

Department of ECE, CMRCET 14

IC APPLICATIONS & VLSI LAB R18 Regulation

RESULT: Studied about the Operation of Integrator and Differentiator using Op-Amp 741 and
output waveforms are observed on CRO for sine and square inputs.

VIVA VOCE:
1. List various Operational Amplifier parameters.
2. Define Slew Rate.
3. What are the various specifications of Op-Amp 741?
4. What are the various factors effecting the parameters of Op-Amp.
5. Define input offset voltage.

Department of ECE, CMRCET 15

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO : 3

ACTIVE LOW PASS & HIGH PASS BUTTERWORTH SECOND ORDER FILTER

(A) HIGH PASS SECOND ORDER BUTTER WORTH FILTER

AIM : To plot the frequency response characteristics of a second order Butterworth low
pass filter.

APPARATUS: IC 741 -- 1 No.

Resistor 10K  --- 2 No.
Capacitor 0.022  F --- 2No.
Function Generator, CRO, Dual Regulated Power Supply,
Connecting wires.

CIRCUIT DIAGRAM:

THEORY :

In case of Low Pass Filter, it is always desirable that the gain rolls off very fast after
the cut-off frequency i.e. in the Stop Band. In case of first order filter, it rolls off at a rate of 20
dB /decade. In case of second order filter, the gain rolls off at a rate of 40 dB/ decade. Thus, the
slope of the frequency response after f = fH is -40dB/ decade, for a second order low pass filter.

Department of ECE, CMRCET 16

IC APPLICATIONS & VLSI LAB R18 Regulation

A first order filter can be converted to second order type by using an additional RC
network as Shown in the fig. The cut-off frequency fH for the filter is decided by R2, C1, R3, and
C2. The gain of the filter is as usual decided by op-amp i.e. the resistance R1 and Rf.

Higher Cut off Frequency f H =

Af
Gain of the Second Order Filter A = | V0/ Vin | =
1 + ( f / fH )4
Where Af = Pass band gain of the Filter (1 + RF/ R1)
f = frequency of the Input Signal
f H = Higher Cut off frequency

DESIGN PROCEDURE: f H = 723Hz

Choose the value of ‘C ‘less than or equal to 1  f ; let C = 0.022  f

Then calculate R using the f H =

R2 = R3 = R
C1 = C2 = C
So f H = 1/ 2  RC
723 = 1/ 2  . R. 0.022 

R2 = R3 = R = 10KΩ .

PROCEDURE :

1. Make Connections as per the Circuit diagram

2. Set Vin(p-p) = 1V vary frequency from 5 Hz to 1 MHz and note down the Amplitude of
output wave form (Vo).
3. Calculate Gain and Gain in db.
4. Plot the frequency response curve and determine FH.
Also mark the pass band and stop band.

Department of ECE, CMRCET 17

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPECTED GRAPH:

Theoretical fH=
Practical fH=

RESULT: The frequency response of 1st order Low Pass Filter is plotted. The cut off
frequency is calculated and is verified with the theoretical value.

VIVA VOCE:
1.What is Filter ?
2.What is Low pass filter?
3.What is Paasband and Stopband?
4. What is the pass band voltage gain of the Butterworth Low pass filter?
5. How 1st order can convert the 2nd order Low pass filter

Department of ECE, CMRCET 18

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO :3

ACTIVE LOW PASS & HIGH PASS BUTTERWORTH SECOND ORDER FILTER

(B) HIGH PASS SECOND ORDER BUTTER WORTH FILTER

AIM : To plot the frequency response characteristics of a Butterworth second order high pass
filter using op-amp.

APPARATUS: IC 741 : 1 No.

Resistors : 10K  -1, 20K  -1.
Capacitor : 0.01  F -2No.
Function Generator, CRO, Dual Regulated Power Supply.

CIRCUIT DIAGRAM:

THEORY :In case of High Pass Filter, it is always desirable that the gain rolls off very fast before
the cut-off frequency i.e. in the Stop Band. In case of first order filter, it rolls off at a rate of 20
dB /decade. In case of second order filter, the gain rolls off at a rate of 40 dB/ decade. Thus, the
slope of the frequency response before f = fL is +40dB/ decade, for a second order high pass filter.
A Second order Low pass filter can be converted to second order High pass Filter
type by interchanging the positions of Capacitors and Resistors as given in fig. The cut-off

Department of ECE, CMRCET 19

IC APPLICATIONS & VLSI LAB R18 Regulation

frequency fL for the filter is decided by R2, C1, R3, and C2. The gain of the filter is as usual decided
by op-amp i.e. the resistance R1 and Rf

Lower Cut off Frequency f L =

Af
Gain of the Second Order Filter A = | V0/ Vin | =
1 + ( fL / f )4
Where AF = Pass band gain of the Filter (1 + RF/ R1)
f = frequency of the Input Signal
f L = Lower Cut off frequency.
PROCEDURE:
1. Make Connections as per the Circuit diagram
2. Set Vin = 1V(P-P) vary frequency from 5Hz to 1 MHz and note down the Amplitude of
output wave form (Vo).
3. Calculate gain, gain in db.
4. Plot the frequency response curve and determine fL.Also mark the pass band and stop band.

TABULAR COLUMN:Vin(p-p)=

Input Frequency(f) Vo Gain in dB

Gain ( )
in Hz Vo(in Volts) Vin Vo
20 log10 ( )
Vin

EXPECTED GRAPH:

Department of ECE, CMRCET 20

IC APPLICATIONS & VLSI LAB R18 Regulation

THEORITICAL PRACTICAL

Lower cutoff frequency fL

RESULT : The frequency response of 1st order High Pass Filter is plotted. The cut off
frequency is calculated and is verified with the theoretical value.

Viva Voice :
1.What is 3rd order fiter?
2. Draw the Circuit of Third Order Low Pass Filter.
3. Draw the Frequency Response of Band Pass Filter.
4.What is Frequency Response?
5.Draw the Ideal Frequency Response of All types of Filers.

Department of ECE, CMRCET 21

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO :4

RC PHASE SHIFT & WEIN BRIDGE OSCILLATOR USING IC-741 OP-AMP

(A)RC PHASE SHIFT OSCILLATOR USING IC-741 OP-AMP

AIM : To compare theoretical and practical frequency of oscillation of RC Phase Shift Oscillator.
APPARATUS : CRO
Probes
Connecting wires
R1=10KΩ,
Rf=10 KΩ,
Rcomp=5 KΩ
R=10 KΩ,C=.01µf

CIRCUIT DIAGRAM :

Fig(a)

THEORY :

Department of ECE, CMRCET 22

IC APPLICATIONS & VLSI LAB R18 Regulation

Oscillator is a circuit which generates output without any input. Oscillator can be defined
as a device that converts dc to ac.

Oscillators can be classified as Based on the components used.

RC Oscillators - RC Phase shift, Wein Bridge Oscillator
LC oscillators - Colpitts, Hartley, Clapp Oscillator
Crystal Oscillators
Based on the type of waveform
Sinusoidal Oscillators – RC Phase shift, Wein Bridge, Colpitts, Hartley….
Non-Sinusoidal Oscillators- UJT relaxation Oscillators
Based on frequency range
Audio frequency oscillator – RC oscillators
Radio frequency oscillator – LC oscillators

Barkhausen ‘s criterion for oscillations:

1) For sustained oscillations the phase shift around the circuit( amplifier and feedback
circuit) should be 360o or 0o.
2)The gain of the amplifier should greater than or equal to unity
A Phase shift oscillator consists of an Op-Amp as the amplifying stage and three cascaded
networks as the feedback circuit. The feedback circuit provides feedback voltage from the output
back to the input of the amplifier. The Op-Amp is used in the inverting mode, therefore any signal
that appears at the inverting terminal is shifted by 180o at the output. An additional 180o phaseshift
is provided by the 3 RC sections – each section providing a Phase shift of 60o. There fore feedback
circuit ( 3 RC-sections) provide additional around the loop 180o, totally giving 360o phaseshift
around the loop. A specific frequency when the phaseshift of the cascaded RC sections is 180 o
and the gain of the amplifier is sufficiently large, the circuit will oscillate at that frequency which
is called the frequency of oscillation fo and is given by
fo = 1/2πRC√6 = 0.065/ RC
At this frequency, the gain Av must be atleast 29
i.e., Rf/R = 29.
The circuit will produce a sinusoidal waveform of frequency fo if the gain is 29 and the total
Phase shift around the circuit is exactly 360o or 0o. For desired frequency of oscillation. Choose
a capacitor C, and then calculate the value of R.

PROCEDURE :
1. Connect the circuit as shown in fig(a).
2. Connect the output of the circuit to CRO through probes.
3. Calculate the practical frequency of oscillation f = 1/T by observing the timeperiod of the
output sinusoidal waveform on the CRO and compare it with theoretical frequency of Oscillation
f = 1/2πRC√6
4. Sketch the output waveform by noting the timeperiod and peak to peak voltage of the output
waveform

TABULAR COLUMN:

S.No R C Theoretical Timeperiod Practical

Ω µF fo= 1/2πRC√6 T fo = 1/T

Department of ECE, CMRCET 23

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPECTED WAVEFORMS :

Fig(b)

RESULT: Practical frequency of oscillation of RC Phase Shift Oscillator is compared with the
theoretical value.

VIVA VOCE:
1. Define Oscillator
2. What is the frequency of oscillation i.e f0 for RC Phase shift Oscillator.
3.What is the minimum gain required in RC Phase shift Oscillator.
4. What is the phase shift provided by each RC section at the frequency of oscillation.
5. What is Barkhusen’s criteria for oscillations

Department of ECE, CMRCET 24

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO :4

RC PHASE SHIFT & WEIN BRIDGE OSCILLATOR USING IC-741 OP-AMP

(B)WEIN–BRIDGE OSCILLATOR USING IC-741

AIM : To compare theoretical and practical frequency of oscillation of Wein Bridge

Oscillator.

APPARATUS : CRO
Probes
Connecting wires
Rf=100 KΩ (pot),R1=10 KΩ
R=4.7 KΩ,C=0.047µf

CIRCUIT DIAGRAM :

Fig.(a)

THEORY :
Many electronic devices require a source of energy at a specific frequency which may
range a few Hz to several MHz. This is achieved by an electronic device called an oscillator.
Oscillator is a circuit which generates output without any input. Oscillator can be defined as a
device that converts dc to ac. Oscillators can be classified as
Based on the components used.
RC Oscillators - RC Phase shift, Wein Bridge Oscillator
LC oscillators - Colpitts, Hartley, Clapp Oscillator

Department of ECE, CMRCET 25

IC APPLICATIONS & VLSI LAB R18 Regulation

Crystal Oscillators
Based on the type of waveform
Sinusoidal Oscillators – RC Phase shift, Wein Bridge, Colpitts, Hartley….
Non-Sinusoidal Oscillators- UJT relaxation Oscillators
Based on frequency range
Audio frequency oscillator – RC oscillators
Radio frequency oscillator – LC oscillators
This wein Bridge Oscillator is the standard oscillator circuit for low to moderate
frequencies, in the range of 5 Hz to about 1 MHz . This oscillator is preferred for commercial
audio generators and other low frequency applications. To avoid the damped oscillations at the
output the Wein Bridge oscillator it uses a feedback circuit called a lead – lag network. To
generate un damped oscillations, the positive feedback must be used because the output must
generate itself.
Barkhausen ‘s criterion for oscillations:
1) For sustained oscillations the phase shift around the circuit( amplifier and feedback
circuit) should be 360o or 0o.
2)The gain of the amplifier should greater than or equal to unity.
This type of RC oscillator’s is used for frequencies from 1 Hz to 5 MHz,
The commonly used audio frequency oscillator is Wein Bridge oscillator as shown in the
circuit. The feedback signal in this circuit is connected to the non-inverting terminal, therefore
the Op-Amp is working in non-inverting mode. Hence this amplifier doesn’t provide any phase
shift. There fore the feedback network need not provide any phase shift. The condition of zero
Phase shift around the circuit is achieved by balancing the bridge.
For sustained oscillations, the amplifier must have a gain of precisely 3. but practically Av
may be slightly less or greater than 3.
For Av < 3, the oscillations will either die down or fail to start.
For Av > 3, the oscillations will be growing.

PROCEDURE :
1. Connect the circuit as shown in Fig(a)
2. Switch ON the power supply.
3. Connect the output of the circuit to CRO through probes.
4. Calculate the practical frequency of oscillation f = 1/T by observing the timeperiod of the
output sinusoidal waveform on the CRO and compare it with theoretical frequency of Oscillation
f = 1/2πRC
5. Sketch the output waveform by noting the timeperiod and peak to peak voltage of the output
waveform

TABULAR COLUMN:

S.No R Theoretical Timeperiod Practical

Ω C fo= 1/2Πrc T fo = 1/T

µF

Department of ECE, CMRCET 26

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPECTED WAVEFORMS :

Fig(b)

RESULT: Practical frequency of oscillation of Wein Bridge Oscillator is compared with the
theoretical value.

VIVA VOCE:
1. What is the resonant frequency of the balanced wein bridge oscillator.
2. What is the relationship between RF and R1 in Wein bridge Oscillator.
3. What are the two requirements for oscillation.
4. Why RC oscillators are called low frequency oscillators
5. What is the advantage by using IC 741 op-amp in the oscillator circuit

Department of ECE, CMRCET 27

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO :5

IC 555 TIMER MONOSTABLE MULTIVIBRATOR

AIM : To generate a pulse waveform of required pulse width by using 555 timer.

APPARATUS : Monostable Multivibrator Kit

CRO
Probes
Connecting wires
C1=C2=0.01µF,C=0.1 µF
R=3.9KΩ.

CIRCUIT DIAGRAM :

Fig(a)

Fig(b)

Department of ECE, CMRCET 28

IC APPLICATIONS & VLSI LAB R18 Regulation

THEORY:
Monostable can also called as One – shot Multivibrator. when the output is low, the circuit
is in stable state, Transistor Q1 is ON and Capacitor C is shorted out to ground. However, upon
application of a negative trigger pulse to Pin – 2, transistor Q1 is turned OFF , which releases
short circuit across the external capacitor and drives the output High. The capacitor C now starts
charging up toward VCC through RA . However when the voltage across the external capacitor
equals 2/ 3 VCC comparator – 1’s (C1 ) output switches from low to high, which is turn derives
the output to its low state via the output of the flip flop turns transistor Q1 ON, and hence,
capacitor C rapidly discharges through the transistor. The output of the Monostable remains low
until a trigger pulse is again applied. Then the cycle repeats. The time during which the output
remains high is given by Tp = 1.1 R C

Fig.(c)
Waveforms for IC555 Monostable Multivibrator:

Department of ECE, CMRCET 29

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig.(d)

Once triggered, the circuit ‘s output will remain in the high state until the set time tp
elapses. The output will not change its state even if an input trigger is applied again during this
time interval tp.
PROCEDURE:
1. Connect the circuit as shown in fig(b).
2. Connect function generator at Pin 2 and Ch-1 of CRO at Pin 2 and ch-2of CRO at Pin 3.
3. Apply square wave from function generator and observe the output voltage Vo with respect to
input.
4. Now connect ch-2 of CRO across capacitor and observe the voltage across the capacitor Vc.
5. Note the timeperiod and amplitude of output voltage Vo and capacitor voltage Vc.
6. Find out the practical pulse width.

TABLE:

Theoretical value Practical value

tp =1.1RC tp
Pulse width

EXPECTED WAVEFORMS:

Department of ECE, CMRCET 30

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig (e)
RESULT: Theoretical and Practical frequency of oscillation of monostable multivibrator is
calculated and compared.

VIVA VOCE:
1. List various applications of 555 timer.
2. Explain the function of RESET in 555 timer.
3. What are the modes of operation of a timer.
4. What is supply voltage of 555 timer.
5. What are the various applications in Monostable mode.

EXPERIMENT NO : 6
VOLTAGE REGULATOR USING IC 723,THREE TERMINAL VOLTAGE
REGULATORS-IC 7805,7809,7812,7905,7909,7912

(A)VOLTAGE REGULATOR USING IC 723.

AIM : To verify the action of IC 723 as a voltage regulator and to find the values of load
regulation and line regulation.

APPARATUS : IC723 Voltage regulator

Connecting wires.
Multimeter.
DRB.
RPS.
CRO
Probes

CIRCUIT DIAGRAM :

Department of ECE, CMRCET 31

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig(a)
THEORY:
IC723 device is most versatile of monolithic regulators. It can be used to provide high and
low positive regulated voltages, negative regulated voltages and can be used as positive and
negative switching regulator.
IC 723 by itself can supply output current upto 120mA. External resistors can be
added to provide higher load currents. It takes input voltage upto 40 V. The output voltage is

adjustable from 2V to 35 V. This can be either a linear or switching regulator. This can be also
used as shunt regulator, a current regulator or a temperature controller.

PROCEDURE:

1. Connect the circuit as shown in figure(a)by connecting appropriate resistors and capacitors.
2. Measure the reference voltage at Pin 6(it should be greater than 7V)
3. The internal reference voltage are applied to the potential divider R1 & R2.
4. Keeping R1 constant, vary R 2 and R3 . The output voltage Vo is measured .
5. Compare this output voltage with the theoretical value
6. Tabulate the result for different values of R2 ,R3.
7. Calculate load Regulation & line regulation

Load Regulation : VNL –VFL X 100

VFL

Line Regulation : VO1 –VO2 X 100

VO1

VO1 =Ouput Voltage when Vcc = 25 V

VO2 =Ouput Voltage when Vcc = 15 V

Department of ECE, CMRCET 32

IC APPLICATIONS & VLSI LAB R18 Regulation

CALCULATIONS:

VNL = VFL =

VO1 = VO2 =

Load Regulation = VNL –VFL X 100

VFL

Line Regulation = VO1 –VO2 X 100

VO1
=

Where VO1 =Ouput Voltage when Vcc = 25 V

VO2 =Ouput Voltage when Vcc = 15 V

RESULT: Load Regulation & Line Regulation of IC 723 are calculated.

THREE TERMINAL VOLTAGE REGULATORS-IC 7805, 7809,7812,7905,7909,7912

AIM :To study about 3 pin regulators IC 78XX & 79XX.

APPARATUS : 3 Pin Regulator IC trainer.

Digital Multimeter.
Connecting wires.

CIRCUIT DIAGRAM :
78XX voltage Regulator

Department of ECE, CMRCET 33

IC APPLICATIONS & VLSI LAB R18 Regulation

Fig(a)
79XX voltage Regulator

Fig(b)

THEORY :

A three terminal voltage regulator is a regulator in which the output voltage is set at some
predetermined value. Such regulator does not require any external feedback connections. Hence
only three terminals are required for device of such type :
input Vin,
Output Vo &
a ground terminal.

The main advantage of three terminal regulators are :

1. Simplicity of connections to the external circuit and
2. Minimum pF external components ( in some cases no external components are required)
78XX THREE TERMINAL POSITIVE VOLTAGE REGULATORS.The 78XX series of
three terminal voltage regulators are available with output voltage of 5, 6, 8, 12, 15, 18 &

Department of ECE, CMRCET 34

IC APPLICATIONS & VLSI LAB R18 Regulation

24V with the designation of the 5V regulator being the 7805, the 6V being the 7806 and so
On.

The voltage regulators of 78XX series all have the same internal circuitry, expect for
different values of one resistor, which determines the output voltage level.
Fig represents the circuit connections for 78XX series. Pin 1 represents the input, Pin 2
represents ground and Pin3 represents the output terminal.

79XX THREE TERMINAL NEGATIVE VOLTAGE REGULATOR

The 79XX series of fixed output negative voltage regulators are complements to the 78XX series
devices. The negative regulators are available in the output voltage options -2, -5, -5.2, -6, -8, -
12, -15, -18 and -24 V. The maximum input voltage for Vo=24v is 40V, while for the remaining
options is -35V

PROCEDURE:
1. Connect the circuit as shown in fig.
2. Switch ON the 3 Pin regulator IC trainer.
3. Observe the o/p voltages for 78XX &79XX IC regulators at Pin 2 by applying input at Pin 1.
4. Tabulate the reading for different IC’s.

TABULAR COLUMN:

S.No Voltage Input Vin Output

(volts) Vo
Regulator (volts)
1 7805

2 7806

3 7812

4 7905

Department of ECE, CMRCET 35

IC APPLICATIONS & VLSI LAB R18 Regulation

5 7912

6 7924

RESULT: 78XX and 79XX 3 pin IC voltage regulators output voltages are observed.

VIVA VOCE:
1. In which period is the capacitor filter discharged through the load in a full-wave rectifier
2. What is the range of the voltage level of the LM317 adjusted voltage regulator
3. Switching regulator efficiencies can be greater than which percent.
4. What is the typical dropout voltage for the 7812 fixed positive voltage regulator
5. What is the ratio of the period of the output voltage to the period of the input voltage in a
full-wave rectifier

Department of ECE, CMRCET 36

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENTS BEYOND THE SYLLABUS

EXPERIMENT NO: 1
3 TO 8 DECODER (74LS138)
Aim: To verify operation of the 3 to 8 decoder using Ic 74LS138.
Apparatus : 1. 3 to 8 decoder Ic 74LS138 .
2. Patch chords
Theory:

Department of ECE, CMRCET 37

IC APPLICATIONS & VLSI LAB R18 Regulation

A decoder is a combinational circuit that connects the binary information from

‘n’input lines to a maximum of 2n unique out put lines .The IC 74138 accepts three binary
inputs and when enable provides 8 individual active low outputs . The device has 3 enabl inputs
.Two active low and one active high.

Circuit Diagram :

Fig.1

Truth Table: -

Department of ECE, CMRCET 38

IC APPLICATIONS & VLSI LAB R18 Regulation

INPUTS OUTPUTS
ENABLES
G G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
1
x 1 x x x x 1 1 1 1 1 1 1 1
x x 1 x x x 1 1 1 1 1 1 1 1
0 x x x x x 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
Logic Diagram:

Fig.2

Procedure :-
1. Make the connections as per the circuit diagram .
2. Change the values of G1,G2A,G2B,A,B,and C, using switches.

Department of ECE, CMRCET 39

IC APPLICATIONS & VLSI LAB R18 Regulation

3. Observe status of Y0, to Y7 on LED’s.

4. Verify the truth table.

Result:- Verified the Operation of 3 to 8 Decoder.

.

VIVA VOCE:
1. What are the applications of decoder?
2. What is the difference between decoder & encoder?
3. For n- 2n decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. What is even parity & odd parity?
7. Which gate can be used as parity generator & checker?
8. Using 3:8 decoder and associated logic, implement a full adder?
9. Implement a full subtract or using IC 74138?
10. What is the difference between decoder and demux?

EXPERIMENT NO: 2
4 – BIT COMPARATOR (74LS85)

Aim:- To study the operation of 4-bit Magnitude Comparator using Ic7485.

Department of ECE, CMRCET 40

IC APPLICATIONS & VLSI LAB R18 Regulation

Apparatus :- 1 . Power supply . 2. IC7485 4-bit Comparator .

Procedure:-
Theory :-
Magnitude Comparator is a logical circuit , which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B . IC 7485 is a high speed
4-bit Magnitude comparator , which compares two 4-bit words . The A = B Input must be
held high for proper compare operation.

1. Connect the circuit as shown in fig. Feed the 4-bit binary words A0, A1 , A2 , A3 and B0
, B1 , B2 , B3 .from the logic input switches.
2 . Pin 3 of IC 7485 should be at logic 1 to enable compare operation.
4 . Repeat the steps 1 ,2 and 3 for various inputs A0 ,A1 , A2 , A3 and B0 , B1 , B2 , B3 and
3 . Observe the output A>B, A=B , and A<B on logic indicators. The outputs must be 1 or 0
respectively.
observe the outputs at A>B , A=B and A<B .

Verification Table :
A3 A2 A1 A0 B3 B2 B1 B0 OUTPUT

1 1 1 1 1 1 1 0 A>B
1 0 0 0 1 0 0 0 A=B

Department of ECE, CMRCET 41

IC APPLICATIONS & VLSI LAB R18 Regulation

0 0 0 0 1 1 1 1 A<B

Result:- Verified the operation of 4-bit magnitude comparator using Ic 74LS85

VIVA VOCE:
1. What is Comparator?
2. What are the applications of Comparator?
3. Which logic is used as 1 bit comparator?
4. What are different arithmetic comparisons?
5. Can we use subtractor & divider as comparators?
6. What is the significance of 74 on IC’s?
7. Design a 5 bit comparator using a single IC 7485, and one gate?
8. Design a 2 bit comparator using a single Logic gates?
9. Design a 8 bit comparator using a two numbers of IC 7485?
10. Design a 24 bit comparator using a six numbers of IC 7485? .

EXPERIMENT NO: 3

RS FLIP-FLOP, JK FLIP-FLOP, D FLIP-FLOP & T FLIP-FLOP

Aim:To verify the truth table of

a) RS Flip Flop using Logicgates c) D Flip Flop-IC 7474

Department of ECE, CMRCET 42

IC APPLICATIONS & VLSI LAB R18 Regulation

b) JK Flip Flop-IC 7476 d) T Flip Flop using JKFlip-Flop.

Apparatus :-

1. RS, JK, D and T flip-flops Trainer Kit.

2. Set of Patch chords.

RS Flip-Flop:

Fig1. RS Flip-Flop

RS Flip-Flop Clocked version:

S
Q

CLK


Q
R Fig 2.

Truth table –1 for RS Flip Flop

INPUTS OUTPUT COMMENT

R S Q Q’

Department of ECE, CMRCET 43

IC APPLICATIONS & VLSI LAB R18 Regulation

0 0 1 1 Indeterminent

0 1 1 0 Set

1 0 0 1 Reset

1 1 Indeterminate No change

Procedure:
1. Construct the RS flip flop as shown in figure.
2. Feed the logic signals from the logic input switches observe the logic outputs on the logic
level LED indicators. Verify the truth table of clocked RS flip-flops.

JK Flip Flop:

Fig.3

Department of ECE, CMRCET 44

IC APPLICATIONS & VLSI LAB R18 Regulation

Truth Table-2 for JK flip-flop:

INPUTS OUTPUTS COMMENT

Set(s) Reset(R) Clock J K Q Q’

0 0 X X X 1 1 Indeterminent
0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 X 0 0 Q0 Q0| Previous
1 1 0 1 0 1 Reset
1 1 1 0 1 0 set
1 1 1 1 Toggle Race around

Procedure:
1. Connect S’ , R’, J and K terminals to the logic input switches.
2. Connect the clock terminals to bounceless pulser high or low.
3. Connect Q and Q’ terminals to logic output indicators.
4. Set the S’, R’, J and K Signals by means of the switches as per the truth table–2 verify
the Q and Q’ outputs .

D-Flip -Flop:

Fig .4

Department of ECE, CMRCET 45

IC APPLICATIONS & VLSI LAB R18 Regulation

D-flip-flop using Nand gates :

Fig.5

S’ R CLOCK D Q Q’ COMMENT
’
0 0 X X 1 1 Race

0 1 X X 1 0 Set

1 0 X X 0 1 Reset

1 1 1 1 0 Data Transfer

1 1 0 0 1 Data Transfer

Truth Table - 3

Procedure:
1.Connect S’, R’ and D terminal to the logic input switches.
2.Connect the clock terminals to bounceless pulser high or low.
3.Connect Q and Q’ terminals to logic output indicators.
4.Set the S’, R’ and D signals by means of the switches as per TruthTable–3. Verify the Q and
Q’ outputs.

Department of ECE, CMRCET 46

IC APPLICATIONS & VLSI LAB R18 Regulation

T – Flip Flop:

Fig.6

J S R CLOC Q Q’ COMMENT
& K (T)
K
1 0 0 X 1 1 Race

1 0 1 X 1 0 Set

1 1 0 X 0 1 Reset

1 1 1 Q’n-1 Qn-1 Data

Transfer
Truth Table - 4

Procedure:

1. Connect S’ and R’ Terminals to the logic input switches.

2. Set J and K permanently to high by means of input switches.
3. Connect the clock terminals (T) to the bounceless pulser high or low.
4. Connect Q and Q’ terminals to logic output indicators.
5. Set the S’ and R’ signals by means of the switches as per Truth Table – 4 verify the Q and Q’
outputs.
Result: Verified the truth tables of all Flip-Flops.

Department of ECE, CMRCET 47

IC APPLICATIONS & VLSI LAB R18 Regulation

VIVA VOCE :

1.What is the difference between Flip-Flop & latch?

2.Give examples for synchronous & asynchronous i/P’s?
3..What are the applications of different Flip-Flops?
4.What is universal flip-flop?
5.What is the advantage of Edge triggering over level triggering?
6.What is the relation between propagation delay & clock frequency of flip-flop?
7.What is race around in flip-flop & how to overcome it?
8.What are not allowed inputs for RS flip flop using NAND & NOR gates?
9.Connect the J K Flip-Flop into D flip-flop and T flip-flop?
10.List the functions of asynchronous inputs?

Department of ECE, CMRCET 48

IC APPLICATIONS & VLSI LAB R18 Regulation

EXPERIMENT NO: 4
UNIVERSAL SHIFT REGISTER (74LS194)

Aim :- To study the following applications of the Universal shift register using IC
74194.
a . Shift Right Logic
b . Shift Left Logic
c . Parallel Load

Apparatus :-
1. Universal Shift Register IC 74194.
2. 5v fixed DC power supply.
Circuit Diagram:-

Fig.1

Procedure:-

STEP : 1. MASTER RESET

Set the inputs as below and observe the out puts as per table 1

Department of ECE, CMRCET 49

IC APPLICATIONS & VLSI LAB R18 Regulation

M S S DS DSL C P0 P1 P2 P3 Q Q Q Q
R 1 0 R P 0 1 2 3
0 X X X X X X X X X 0 0 0 0

Truth table –1
A logic ‘ 0 ‘ on MR resets all outputs to logic ‘ 0 ‘ irrespective of other inputs.

STEP :2 PARALLEL LOAD

In this step we load the data parallel. Set the inputs as below and observe the outputs.

M S1 S0 DSR DSL CP P0 P1 P2 P3 Q Q Q2 Q3
R 0 1
1 1 1 x x CLK 1 1 1 1 1 1 1 1

Truth Table –2

Here when S1 & S0 are both logic ‘ 1 ‘ the input data is transferred parallely to output at the
clock positive transition change the input data and observe the change at the output .

STEP : 3 . SHIFT LEFT LOGIC ‘ 0 ‘.

Set Q0 , Q1 , Q2 , Q3 to ‘ 1 1 1 1 ‘ by putting DSL to Logic ‘ 1 ‘ .
While running the above step, change the logic input DSL to logic ‘ 0 ‘
And S0 to logic ‘ 0 ‘ in the same sequence .Observe the following outputs after each clock
pulse and verify .

CONDITIO n Q0 Q1 Q2 Q3
N CLOCK
PULSES
MR = 1 0 1 1 1 1
S0 = 0 1 1 1 1 0
S1 = 1 2 1 1 0 0
DSL = 0 3 1 0 0 0
DSR = X 4 0 0 0 0
Truth Table – 3

Department of ECE, CMRCET 50

IC APPLICATIONS & VLSI LAB R18 Regulation

In the sequence 4 clock pulses logic ‘ o ‘ s are shifted left successively with each clock
pulse .
STEP : 4 . SHIFT LEFT LOGIC ‘ 1 ‘ S
Set the Q0 Q1 Q2 Q3 to 0 0 0 0 by setting DSL input to logic ‘ 0 ’.
Now switch DSL input to logic ‘ 1 ‘ and observe the shifting of logic ‘ 1 ‘ s to left as below .
Observe the following outputs after each clock pulse and verify.
Truth Table – 4
CONDITIO n CLOCK Q0 Q1 Q2 Q3
N PULSES
MR = 1 0 0 0 0 0
S0 = 0 1 0 0 0 1
S1 = 1 2 0 0 1 1
DSL = 1 3 0 1 1 1
DSR = X 4 1 1 1 1

STEP : 5 . SHIFT RIGHT LOGIC ‘ 0 ‘

Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic ‘ 1 ‘ .
Repeat step 4 and parallel load logic ‘ 1 ‘ s in all the 4 outputs .
Change the logic inputs of DSR to logic 0 and then of S1 to logic ‘ 0 ‘
in the same sequence . Observe the following outpus after each clock pulse and verify .

CONDITION n CLOCK Q0 Q1 Q2 Q3
PULSES
MR = 1 0 1 1 1 1
S0 = 1 1 0 1 1 1
S1 = 0 2 0 0 1 1
DSL = X 3 0 0 0 1
DSR = 0 4 0 0 0 0
Truth Table –5
STEP : 6 SHIFT RIGHT LOGIC ‘1 ‘ s
Now at this condition of all ‘ 0 ‘ at the outputs switch DSR to logic ‘1’ this will enable all
logic as serial data and logic ‘ 1 ‘ s will be shifted successively with each clock pulse as
shown below .Observe the following table and verify the outputs .

Department of ECE, CMRCET 51

IC APPLICATIONS & VLSI LAB R18 Regulation

CONDITION n CLOCK Q0 Q1 Q2 Q3
PULSES
MR = 1 0 0 0 0 0
S0 = 1 1 1 0 0 0
S1 = 0 2 1 1 0 0
DSL = X 3 1 1 1 0
DSR = 1 4 1 1 1 1
STEP : 7 . In the above steps for shift left or shift right operation ,(step 3 4 5 6 ) if both the S0
&S1 switches are forced to logic ‘ 0 ‘, then shifting operation will cease and whatever is the
output data it will freeze or hold . Observe this condition and verify .
CONDITION n CLOCK PULSES Q0 Q1 Q2 Q3
MR = 1 1 Previous data just before
S0 = 0 1 S0 &S1 both switched to
S1 = 0 1 logic ‘ 0 ‘.
DSL = 0 1
DSR = 0 1
Truth Table –7

Result:- Verified the applications of the Universal shift register using IC 74LS194
Questions: -
1. What is the universal shift register?
2. In which circuits shifting and rotating circuits are used?
3. Which flip-flops are used in shift registers?
4. Which flip-flop is universal flip-flop?
5. What is the difference between shifting and rotating data?
6. What is register?
7. What is meant by parallel in & parallel out Shift register?
8. State various applications of Shift register?
9. List the basic types of shift register in terms of data movement?
10. Determine the output status of a 4-bit SIPO shift register, after 3 clock pulses if the I/P
terminal is held high?

Department of ECE, CMRCET 52