8-bit computer: micro-architecture

COMS10015: Computer Architecture

Tom Deakin
Lecture 3
University of Bristol
 Outline

1. Timing

2. Data Path

3. Decode

4. Modules and ModuleSim

5. Demo: Building the timing unit with Modules

6. ModuleSim

7. Demo: Building the timing unit in ModuleSim

©Tom Deakin [email protected] 1
Timing
Timing unit

• Start with a register (will use 4-bit).

Reg
Timing unit

• Start with a register (will use 4-bit).

• Use an ALU to add 1 to the value.
ADD 1

Reg
Timing unit

• Start with a register (will use 4-bit).

• Use an ALU to add 1 to the value.
• Want to feedback result back to add ADD 1
again — store in a second register.

Reg

Reg
Timing unit

• Start with a register (will use 4-bit).

• Use an ALU to add 1 to the value.
• Want to feedback result back to add ADD 1
again — store in a second register.
• Two-phase clock so registers update in
turn. Reg φ1

Reg φ2
 Timing unit

Fetch
DEMUX Inc PC
Execute
• Start with a register (will use 4-bit).
• Use an ALU to add 1 to the value.
• Want to feedback result back to add ADD 1
again — store in a second register.
• Two-phase clock so registers update in
turn. Reg φ1

• Use DEMUX to split 4-bit number

into signals.
Reg φ2

©Tom Deakin [email protected] 2

Timing unit: signals

φ1

φ2
Timing unit: signals

Fetch

φ1

φ2
Timing unit: signals

Fetch

Inc PC

φ1

φ2
 Timing unit: signals

Fetch

Inc PC

Execute

φ1

φ2

©Tom Deakin [email protected] 3

Data Path
Data Path

areg pc breg inst/oreg

Data Path

A MUX

areg pc breg inst/oreg

Data Path

A MUX B MUX

0 0

areg pc breg inst/oreg

Data Path

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

ALU

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

ALU From Control

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

rreg

ALU From Control

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

rreg

ALU From Control

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

rreg φ1

ALU From Control

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

Data Path

rreg φ1

ALU From Control

A MUX From Control B MUX From Control

0 0

areg pc breg inst/oreg

From Control + φ2 From Control + φ2 From Control + φ2 From Control + φ2

 Data Path

rreg φ1

From Control ALU From Control

A MUX From Control B MUX From Control

ALU COND
0 0

To Control
areg pc breg inst/oreg

From Control + φ2 From Control + φ2 From Control + φ2 From Control + φ2

©Tom Deakin [email protected] 4

 Data Path

• Data path contains the registers and functional blocks to compute.

• Multiplexers used to select input registers to ALU.
• Wires come from Control to choose operations.
• Result register hidden from ISA — implementation detail.
• Two phase clock:
φ1 : update rreg based on signals from Control.
φ2 : save result in areg /breg /oreg /pc, also based on Control.

©Tom Deakin [email protected] 5

Decode
 Decode

• Use DMUX to decode instruction. DEMUX

• Split 4-bit instruction from inst

register into two.
• Each 2-bit pair controls DMUX
DEMUX

selection.
DEMUX

Execute
DEMUX DEMUX

4-bit instruction, split into two 2-bit signals

©Tom Deakin [email protected] 6

 Decode

• Use DMUX to decode instruction. DEMUX

• Split 4-bit instruction from inst

register into two.
• Each 2-bit pair controls DMUX
DEMUX

selection.
• Example: Instruction 0110 → 01 10 DEMUX

Execute
DEMUX DEMUX

4-bit instruction, split into two 2-bit signals

©Tom Deakin [email protected] 6

 Decode

• Use DMUX to decode instruction. DEMUX

• Split 4-bit instruction from inst

register into two.
• Each 2-bit pair controls DMUX
DEMUX

selection.
• Example: Instruction 0110 → 01 10 DEMUX

• 10 selects third from top output on

right DMUXs.
Execute
DEMUX DEMUX

10

4-bit instruction, split into two 2-bit signals

©Tom Deakin [email protected] 6

 Decode

• Use DMUX to decode instruction. DEMUX

• Split 4-bit instruction from inst

register into two.
• Each 2-bit pair controls DMUX
DEMUX

selection.
• Example: Instruction 0110 → 01 10 DEMUX

• 10 selects third from top output on

right DMUXs.
• 01 selects second from top output Execute
DEMUX DEMUX

on left DMUX.
01 10

4-bit instruction, split into two 2-bit signals

©Tom Deakin [email protected] 6

 Decode

• Use DMUX to decode instruction. DEMUX

• Split 4-bit instruction from inst

register into two.
• Each 2-bit pair controls DMUX
DEMUX

selection.
• Example: Instruction 0110 → 01 10 DEMUX

• 10 selects third from top output on

right DMUXs.
• 01 selects second from top output Execute
DEMUX DEMUX

on left DMUX.
• On Execute signal, left DMUX 01 10

selects which right DMUX to 4-bit instruction, split into two 2-bit signals
activate — only one output signal.
©Tom Deakin [email protected] 6
Modules and ModuleSim
 Modules

Bristol has developed some Modules:

• Physical functional blocks that can be put together to build a computer!

• Each Module is a 4-bit unit.
• Module for register, MUX, DEMUX, ALU, etc.
• Connect two 4-bit Modules to get 8-bit.
• Control signals are propagated through.

©Tom Deakin [email protected] 7

 Module details

Details of what each module does at

https://teachingtechnologistbeth.github.io/ModuleSim/modules.html.
Need to check the specific control signals required to set registers, select ALU
operation, etc.
Lab classes
In the lab classes, you’ll build the Hex 8 computer out of the modules (in simulation).

©Tom Deakin [email protected] 8

 Big Hex Machine

Modules were once used to construct a giant 16-bit computer called The Big Hex
Machine.

• Used to be on display in the Merchant

Venturers Building.
• Design is very similar to the Hex 8
machine.

More details: https://bighexmachine.github.io

©Tom Deakin [email protected] 9
Demo: Building the timing unit
with Modules
ModuleSim
 ModuleSim

• You’ll use ModuleSim to build the Hex 8 computer instead of the physical
modules.
• See lab sheet for details.

©Tom Deakin [email protected] 10

Demo: Building the timing unit in
ModuleSim