Semiconductor Materials

and
Process Technology
Handbook
for
Very Large Scale Integration (VLSI)
and
Ultra Large Scale Integration (ULSI)

Edited by

Gary E. McGuire
Microelectronics Center of North Carolina
Research Triangle Park, North Carolina

I 1

L-l "P
NOYES PUBLICATIONS
Westwood, New Jersey, U.S.A.
Copyright 01988 by Noyes Publications
No part of this book may be reproduced in any form
without permission in writing from the Publisher.
Library of Congress Catalog Card Number: 87-31529
ISBN: 08155-l 150-7
Printed in the United States

Published in the United States of America by

Noyes Publications
Fairview Avenue, Weshvood, New Jersey 07675

1098765

Library of Congress Cataloging-in-Publication Data

Semiconductor materials and process technology.

Bibliography: p.
Includes index.
1. Integrated circuits--Very large scale
integration--Design and construction--Handbooks,
manuals, etc. I. McGuire, G.E.
TK7874S4178 1986 621.395 87-31529
ISBN 08155-1150-7
MATERIALS SCIENCE AND PROCESS TECHNOLOGY SERIES

Editors

Rointan F. Bunshah, University of California, Los Angeles (Materials

Science and Technology)
Gary E. McGuire, Microelectronics Center of North Carolina (Elec-
tronic Materials and Processing)

DEPOSITION TECHNOLOGIES FOR FILMS AND COATINGS; Develop-

ments and Applications: by Rointan F. Bunshah et al

CHEMICAL VAPOR DEPOSITION FOR MICROELECTRONICS; Principles,

Technology, and Applications: by Arthur Sherman

SEMICONDUCTOR MATERIALS AND PROCESS TECHNOLOGY HAND-

BOOK; For Very Large Scale Integration (VLSI) and Ultra Large Scale Integration
IULSI): edited by Gary E. McGuire

SOL-GEL TECHNOLOGY FOR THIN FILMS, FIBERS, PREFORMS, ELEC-

TRONICS, AND SPECIALTY SHAPES: edited by Lisa C. Klein

HYBRID MICROCIRCUIT TECHNOLOGY HANDBOOK; Materials, Proc-

esses, Design, Testing and Production: by James J. Licari and Leonard R.
Enlo w

HANDBOOK OF THIN FILM DEPOSITION PROCESSES AND TECH-

NIDUES: Principles, Methods, Equipment and Applications: edited by
Klaus K. Schuegraf

Related Titles

ADHESIVES TECHNOLOGY HANDBOOK: by Arthur H. Landrock

HANDBOOK OF THERMOSET PLASTICS: edited by Sidney H. Goodman

HANDBOOK OF CONTAMINATION CONTROL IN MICROELECTRONICS;

Principles, Applications and Technology: edited by Donald L. To/liver
Contents

INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Gary E. McGuire
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1. SILICON MATERIALS TECHNOLOGY. ...................... .8

William C. 0 ‘Mara
Introduction. ..................................... .8
Silicon Crystal Growth. .............................. .8
Crystal Growth Equipment and Process. ................. .9
Dopant and Impurity Incorporation ................... .15
Incorporation of Oxygen .......................... .19
Incorporation of Carbon. .......................... .21
Wafer Preparation ................................. .22
Mechanical Shaping Procedures ...................... .22
Wafer Etching. ................................. .23
Polishing ..................................... .25
Cleaning ..................................... .25
Material Properties. ................................ .26
Crystal Structure. ............................... .26
Electrical Properties. ............................. .27
Optical Properties ............................... .30
Mechanical Properties. ............................ .31
Process-Induced Defects ............................. .32
Oxidation-Induced Stacking Faults. ................... .32
Saucer Pits. ................................... .33
Carbon-Related Defects ........................... .34
Oxygen in Silicon ................................. .35
Oxygen in As-Grown Silicon ........................ .35
Quantitative Analysis of Oxygen in Silicon. ............ .35

vii
viii Contents

Interpretation of infrared Absorption Spectra. .......... .36

Solid Solubility ............................... .38
Diffusion Coefficient ........................... .39
Donor Formation ............................. .40
Precipitation from Solid Solution. .................... .41
Denuded Zone Formation. ......................... .42
Device Application .............................. .43
References. ..................................... .43

2. THE THERMAL OXIDATION OF SILICON AND OTHER SEMI-

CONDUCTOR MATERIALS. ............................. .46
Bruce E. Deal
Introduction and Background ......................... .46
Silicon Thermal Oxidation Kinetics. ..................... .47
General Relationship ............................. .48
Thin Oxide Formation. ........................... .54
Properties of Thermal Oxides. ......................... .54
Process Variable/Oxidation Reaction Dependencies. .......... .55
Effects of the Oxidation Reaction on Surface Properties. ..... .55
Oxide Charges. ............................... .55
Dopant Redistribution. ......................... .61
Effects of Surface Properties on the Oxidation Reaction. ..... .62
Silicon Orientation ............................ .62
Dopant Concentration .......................... -63
Surface Preparation ............................ .64
Effects of Ambients on the Oxidation Reaction ........... .65
Ambient Type ............................... .65
Chlorine Additions ............................ .65
Nitridation. ................................. .66
Oxidant Pressure. ............................. .67
Oxidation Mechanism. .............................. .68
Atomic Reactions ............................... .68
Structure of the Si-SiOz Interface. .................... .70
Other Oxidation Processes. ........................... .72
Assisted Oxidation. .............................. .72
Silicon-Containing Materials ........................ .73
Other Semiconductors ............................ .74
Future Trends. ................................... .75
References. ..................................... .77

3. CHEMICAL VAPOR DEPOSITION OF SILICON AND ITS

COMPOUNDS.. .................................... ..8 0
Kenneth E. Bean
introduction. .................................... .80
Epitaxial Deposition ............................... .82
HCI in Situ Etching ................................ .86
Gettaring. ...................................... .Ql
Selective Deposition. ............................... .94
 Contents ix

CVD of Dielectric Films. ............................ 105

X-Ray Lithography Mask Fabrication .................... 115
References. .................................... .125

4. CHEMICAL ETCHING AND SLICE CLEANUP OF SILICON. ...... .I26

Kenneth E. Bean
Introduction. .................................... 126
Orientation Dependent Cleaving of Silicon. ................ 129
Orientation Dependent Etching and Orientation Dependent
Deposition. ................................... .I49
(110) Orientation Dependent Effects .................... 157
Defect Delineation Etching ........................... 172
Slice Cleanup ................................... .I83
Precleanup Solvent Rinse ............................ 187
Choline Cleanup Process. ............................ 189
References. .................................... .190

5. PLASMA PROCESSING: MECHANISMS AND APPLICATIONS ..... 191

W.C. DautremontSmith, Richard A. Gottscho and R.J. Schutz
Introduction. ................................... .I91
Fundamental Aspects. .............................. 192
Plasmas and Sheaths. ............................. 193
Response Time and Screening Distance ............... 193
Equivalent Circuits ............................ 195
Feedstock Composition ..... ; .................. .210
Pressure, Flow-Rate, and Residence Time. ............. 213
Power Density .............................. .217
Plasma-Surface Chemistry ......................... .217
Chemical Vapor Transport ...................... .218
Plasma Modified Chemical Vapor Transport ........... .224
Mechanisms. ............................... .230
Modeling. ................................... .241
Plasma Etching. ................................. .242
Introduction. ................................. .242
Outline ................................... .242
Pattern Definition and Transfer ................... .242
An Illustration of Plasma Etch Patterning. ............. 244
Equipment. .................................. .244
Parallel Plate Etchers .......................... .244
The Hexagonal Cathode Etcher ................... .247
Single Wafer Etcher. .......................... .248
Endpoint Detection. ............................ .249
Voltage/Power .............................. .249
Optical Emission Spectra ....................... .249
Laser lnterferometry .......................... .249
Defining Process Parameters and Goals ................ .249
Material to Be Etched. ......................... .251
Feature Edge Profiles. ......................... .252
x Contents

Uniformity. ................................ .253

Selectivity .................................. .254
Throughput ................................ .256
Defect Introduction. .......................... .257
Radiation Damage Effects. ...................... .257
Specific Etching Processes. ........................ .258
Silicon and Silicides. .......................... .258
Etching of Thermal and LPCVD Oxide .............. .260
Etching of Aluminum Metallization ................ .263
Silicon Nitride .............................. .264
Etching of Group III, V Compound Semiconductors ..... .264
Plasma Deposition. ............................... .265
Introduction. ................................. .265
Applications of PECVD Materials. ................. .268
General Aspects of PECVD and PECVD Reactors ......... .268
Reactor Designs ............................. .273
Source Gases ............................... .280
Uniformity Considerations and Interaction of PECVD
Variable Parameters. ......................... .281
Film Properties and Their Control ................. .284
Materials Deposited and Their Applications .............. 289
Silicon Nitride .............................. .289
Silicon Oxide ............................... .301
Amorphous Silicon ........................... .305
Other Semiconductors, Including Epitaxial Growth ....... 308
Metals. ................................... .311
Silicides. .................................. .312
Other Materials. ............................. .312
Interface Properties .............................. 315
Summary and Conclusions .......................... .318
References. .................................... .320

6. PHYSICAL VAPOR DEPOSITION. ........................ .329

John A. Thornton
Introduction. ................................... .329
The Vacuum Environment .......................... .330
Evaporation. ................................... .336
Introduction. ................................. .336
Evaporation Rate .............................. .337
Evaporation Sources ............................ .340
Wire and Metal Foil Sources ..................... .340
Crucible Sources. ............................ .341
Sublimation Sources .......................... .343
Baffle Type Sources. .......................... .343
Knudsen Cell Sources. ......................... .343
Electron Beam Sources. ........................ .344
Other Types of Evaporation Sources. ............... .345
Deposit Thickness Uniformity ...................... .345
 Contents xi

Evaporation of Alloys, Compounds and Mixtures ......... .346

Introduction. ............................... .346
Evaporation of Alloys ......................... .347
Evaporation of Compounds. ..................... .347
Special Evaporation Methods. ...................... .348
Flash Evaporation. ........................... .348
Hot-Wall Evaporation. ......................... .349
Close-Spaced Sublimation. ...................... .350
Multi-Source Evaporation ....................... .351
Reactive Evaporation. ......................... .352
Deposition Rate and Flux Monitors .................. .354
Evaporation Source Material ....................... .355
Molecular Beam Epitaxy. ........................... .355
Introduction. ................................. .355
Apparatus Configuration. ......................... .356
Deposition Procedure. ........................... .358
Coating Growth ............................... .360
Applications. ................................. .362
Sputtering ..................................... .364
Introduction. ................................. .364
Basic Sputtering Mechanisms. ...................... .385
Sputtered Species .............................. .369
The Sputtering Yield ............................ .371
Sputtering Alloys and Compounds ................... .376
Glow Discharge Sputtering Apparatuses. ................ 378
Planar Diodes ............................... .378
Assisted-Discharge Devices, Triodes. ................. 381
Magnetrons ................................ .382
Ion Beam Sputtering ............................ .392
RF Sputtering. ................................ .394
Reactive Sputtering. ............................ .400
Target Fabrication. ............................. .409
Thin Film Growth and Properties. ..................... .410
Coating Nucleation and Growth. .................... .410
Condensation. .............................. .410
Nucleation ................................. .412
Evolution of Microstructure ....................... .415
Growth of Compound Semiconductors from Multicomponent
Vapors.....................................41 9
The Use of Ion Bombardment for Substrate Cleaning and
to Influence Coating Growth. ..................... .422
Internal Stresses ............................... .429
Metallization of Semiconductor Devices. ................. .438
Introduction. ................................. .438
Metallization Materials Considerations. ................ .438
Step Coverage. ................................ .440
Radiation Damage. ............................. .443
References. .................................... .445
xii Contents

7. DIFFUSION AND ION IMPLANTATION IN SILICON ........... .455

Richard 6. Fair
Introduction. ................................... .455
Continuum Theory ............................... .456
Special Cases ................................. .456
Predeposition ............................... .456
Redistribution or Drive-In. ...................... .461
Diffusion Coefficients ........................... .463
Atomic Theory of Diffusion ......................... .465
Diffusion Mechanisms ........................... .465
The Flux Equation in Diffusivity .................... .466
Multiple Charge State Vacancy Model ................. .47O
The Role of Point Defects in Silicon Processing. ............ .472
The Silicon Processing Balancing Act. ................. .472
Point Defects ................................. .473
The Monovacancy. ............................. .473
The Silicon Self-Interstitial Atom. .................... 475
Point Defect Models of Diffusion in Silicon ............. .476
Experimental Observations ........................ .4i’7
Diffusion in the Presence of Excess Point Defects ........... ,479
Oxidation-Enhanced Diffusion. ..................... .479
Doping Dependence of Oxidation-Enhanced Diffusion ...... .482
Effect of Chlorine on Oxidation-Enhanced Diffusion ........ 483
Characteristics of Silicon Self-Diffusion. ................. .485
Dopant Diffusion in Silicon. ......................... .488
Arsenic Diffusion Models ......................... .491
Phosphorus Diffusion Models. ...................... .496
Boron Diffusion Models .......................... .501
Design Considerations for Implanted-Diffused Layers. ........ .505
Arsenic Diffusion .............................. .506
Phosphorus Diffusion. ........................... .510
Ion Implantation. ................................ .512
Ion Implant System. ............................ .515
Simple Range Theory. ........................... .515
Nuclear Stopping. .............................. .519
Electronic Stopping. ............................ .519
Critical Energy ................................ .520
Projected Range ............................... .521
Implantation Masking. ........................... .522
Ion Channeling. ............................... ,527
Modeling Implanted Dopants in Silicon ................ .528
References. .................................... .538

8. MICROLITHOGRAPHY FOR VLSI. . . . . . . . . . . . . . . . . . . . . . . . .541

R. Fabian Pease
Introduction. . . . . . . . . . . . . . , . . . . . . . . . . .. . . . .. . . . . .541
Forming the Resist Film. . . . . . . . . . . . . . . . , . . . . . . . . . . . .542
Generation of the Aerial Image for Electron Beam Mask Making. . .543
Interaction of Electrons with the Workpiece. . . . . . .. . . . . .. . . 545
 Contents xiii

Exposure and Development of Photoresist on Semiconductor

Wafers ..................................... ..55 1
Formation of the Aerial Image in Projection Mask Aligners ...... 556
Interaction of Ultra-Violet Light with Photoresist ............ 559
Exposure and Development of Photoresist Films on Reflective
Substrates. ................................... .564
Emerging New Technologies ......................... .567
Multiple Level Resist .............................. 568
Electron-Beam Direct Write. ....................... .570
X-Ray Lithography ............................. .57 1
Vote Taking Lithography ......................... .573
References. .................................... .574

9. METALLIZATION FOR VLSI INTERCONNECT AND PACKAGING . .575

Paul S. Ho
Introduction. ................................... .575
Wiring Structure ................................. .581
Impact of Device Scaling. ........................... .587
Electrical Characteristics. ........................... .589
Material Reaction ................................ .595
Metallization Reliability ............................. 598
Junction and Gate Contacts. ....................... .598
Electromigration. .............................. .604
Summary. ..................................... .607
References. .................................... .667

10. CHARACTERIZATION OF SEMICONDUCTOR MATERIALS. ..... .610

Gary E. McGuire
Introduction. ................................... .610
Surface Analysis Techniques ......................... .611
Auger Electron Spectroscopy. ...................... .611
Photoelectron Spectroscopy ....................... .618
Secondary Ion Mass Spectroscopy ................... .624
Resonance Ionization Spectroscopy .................. .632
Rutherford Backscattering Spectroscopy ............... .635
Summary.....................................64 0
Imaging Analysis Techniques. ........................ .640
Scanning Electron Microscopy. ..................... .640
Scanning Transmission Electron Microscopy. ............ .647
X-Ray Topography ............................. .653
Bulk Analysis Techniques ........................... .654
Fourier Transform Infrared Spectroscopy .............. .654
Deep Level Transient Spectroscopy. .................. .659
Photoluminescence Spectroscopy. ................... .666
Neutron Activation Analysis ....................... .664
References. .................................... .666

INDEX..............................................669
Introduction

Gary E. McGuire
Tektronix, Inc.
Beaverton, Oregon

There has been a majorthrust throughout the semiconductor industry

to establish the capability to process Very Large Scale (VLSIC) and Ultra
Large Scale (ULSIC) Integrated Circuits, as well as, Very High Speed
Integrated Circuits (VHSIC). The generally accepted goals of VLSI tech-
nology are to produce devices with 1 O6 gates or memory bits per circuit
with geometries of less than 1 micrometer. The goal of ULSI is to produce
deviceswith 107-10ggatesormemorybitspercircuit.1ThegoalsofVHSlC
are to develop the technology to produce devices with 1 micrometer
features that have an equivalent gate clock frequency product exceeding
5 X 10” gate Hz/cm2 and a minimum clock rate of 25 MHz. The goals of
ULSI andVHSlC area natural evolution of current IC technology since the
number of devices on a single IC have nearly doubled every year for the
past twenty years. Similarly, as shown in Figure 1, the minimum horizontal
dimension has been reduced throughout the past decade byafactorof two
about every seven years. Even though the minimum horizontal dimension
has been reduced the overall chip length has increased as illustrated in
Figure 2.
The device parameters of gate length, junction depth and gate oxide
thickness have all decreased with each succeeding generation of product.
There is significant interaction between these parameters and device
performance.2 As shown in Figure 3, the gate oxide thickness has de-
creased with scaling of the active channel length. The device speed,
minimum gate delay, has also decreased with gate length, Figure 4,
yielding improvements in device performance. Part of the improved per-
formance is a direct result of shorter distances that signals must travel

1
2 Semiconductor Materials

LSI -+--VLSI -jcSUPER VLSI -

I

lo- 0
4K DRAM
1 K SRAM
7‘ .O
5- 6K DRA: &? 4K SRAM
4. 16K DRAM
3. 00 16K SRAM

MINIMUM FEATURE 2 64K DRAM

0 .256K DRAM
SIZE b) 64K SRAM
00 1M DRAM
1 .o- 256K SRAM 1M SRAM
0
0.7- .4M DRAM
0.5. 0
0.4. 4M SRAM
I-
1970 1975 1960 1965 1990
YEAR

Figure 1: Projected decrease in feature size for dynamic and static random access
memories as a function of the year of introduction.

2 s 4 S 6 7 8
CHIP LENGTH (MM)

Figure 2: Plot of transistor channel length versus overall chip size showing the
trend toward larger chips even though the feature sizes have decreased.
 Introduction 3

27
Eo lOOO-

b
rn
0) 600-

d
3 600 -

%
5 400 -

0 1 2 3 4 5 6

ACTIVE CHANNEL LENGTH (Microns)

Figure 3: Plot of gate oxide thickness as a function of the active channel length.

3-

2-

l-

0 I I I I
0 1 2 3 4 5

ACTIVE GATE LENGTH (Microns)

Figure 4: Plot of minimum gate delay as a function of the active gate length.
4 Semiconductor Materials

between circuits. Miniaturization also plays a large role in the steady

decrease in the energy utilized per switching operation. The trend in his
parameter, the product of power per circuit and logic delay is shown in
Figure 5.3

I I I I
1960 1970 1860

Figure 5: Plot of the decreasing powerdelay time product as a function of the

year of component introduction.

Additional device related concerns arise as a result of devicescaling.

The subthreshold scaling problem is one that posses significant techno-
logical barriers.4 A plot of the drain current versus gate voltage for a
reference and scaled device, Figure 6, shows that when the gate voltage is
decreased to below the threshold value, the channel current does not drop
linearly to zero but decreases exponentially. This rate of decrease in the
channel current in the subthreshold region is dependent on the gate
voltage and independent of the channel length at a given temperature. If
the designed threshold of thescaled device is too low, asignificant amount
of current continues to flow in the channel when the gate voltage is
reduced to zero. As a result, the stored charge of a capacitor on a dynamic
random access memory(DRAM) will leak off between refresh cycles. This
phenomenon precludes scaling of DRAM threshold voltages according to
the dictates of scaling theory, and therefore precludes accurate scaling of
power supply voltages. As DRAM’s are made smaller and gate insulators
aremadethinner,itmaybenecessarytooperateathigherfieldsacrossthe
oxide, increase the storage capacitor area to increase the total charge
stored or replace the SiO, with a higher dielectric constant material in
order to minimize the effects of leakage current across the channel.2 The
current leakage in the channel is also complicated by current leakage
around the periphetyof the device. The leakage rate of DRAM cellsaround
the periphery has increased with scaling as a result of the change in the
perimeter-to-area ratio of the cell, Figure 7.5
 Introduction 5

VDS = 0.1 v

DRAIN
CURRENT
(IDS)

bATE

GATE VOLTAGE

Figure 6: Plot of the drain current versus gate voltage illustrating the lack of a
sharp cut-off voltage for VLSI devices. Reference: VLSI Technology and Design,
IEEE, 0. Folberth and W. Grobman (1984).

JL (nAlcm2) @

P/A (X 10 cm - 1)

Figure 7: Dependence of the current leakage rate of a dynamic random access

memory cell as a function of the periphery-to-area ratio. Reference: P.K. Chatter-
jee et al ., IEEE Trans. Electron Devices ED-26:486 (1979).

The shear complexity of the design of chips containing many circuits

impedes progress. Interconnecting and packaging these devices is another
area of device technology that requires significant development to circum-
vent the problems that arise as a result of device scaling. For example, the
resistance of interconnecting wires increases asdimensionsare reduced.
The increasing length of interconnections on a chip as a result of the
increasing number of circuits accentuates this problem.3
The methodology necessary for achieving ULSI and VHSI circuit
densities and dimensions are related to traditional horizontal scaling, as
well as vertical scaling. Feature sizes have historically been limited by the
6 Semiconductor Materials

lithographic techniques. However, all the available lithographies(optical,

x-ray, ion and electron beam) are capable of patterning geometries less
than 1 micrometer while maintaining acceptable alignment tolerances
and defect levels.(j The shrinking feature size has also necessitated a
reduction in film thickness in order to achieve the desired physical dimen-
sions and electrical parameters. This has generated new materials and
process technologies to meet these changing requirements.
There are several common themes behind the emergence of these
particular technologies. Foremost among these are small area pattern
definition, registration and replication as driving forces for the various
lithographies and etching techniques. For example, anisotropic etching
removes material in the vertical direction with minimal or no etching in the
horizontal direction. This provides precise replication of the exposed
pattern. Implementation of plasma or reactive ion etching requires thor-
ough characterization of the etch rate selectivity, anisotropy, uniformity
and process reliability. Once the desired material has been deposited and
patterned, there isaneedtominimizeanysubsequent processconditions
that will alter these properties. One approach that has been taken is to use
lowertemperature processes which minimize diffusion of dopants, impuri-
ties and contact metallization or reduce the nucleation of stacking faults,
dislocations and precipitates and dimensional changes in the substrate.
Implementation of ion implantation, chemical vapor and plasma deposition
have lowered the temperature required for many process steps. An alter-
nate approach which reduces the solid state interaction of materials is
rapid thermal processing. The process temperature is ramped up and
down quickly so that the substrate is exposed to an elevated temperature
for only a short period of time.
In addition to the new process technologies, there has been increasing
demands placed on materials. The increasing demands have pushed
some materials beyond their fundamental limits and created a search for
new or improved materials. For example, the electrical conductivity and
associated electromigration problems of Cu of Si doped Al contacts was
clearly unacceptable for VLSI circuits. This led to the development of low
resistivity refractory silicide and doped polysilicon interconnects. Smaller
geometries also dictate higher sensitivity substrates, with fewer defects
and better dimensional control.
In an ultra-small electronic structure, the device is approaching the
dimension of long-range order in the material. For this reason one must be
concerned with diffusion, microstructure and phase transitions within the
host material. The nucleation of thin films is generally governed by non-
equilibrium thermodynamics resulting in questions about solid phase
reactions, segregation and agglomeration. Our lack of understanding of
physical phenomena on the microscopic scale has created the need for
extensive characterization.
At the same time device geometries diminished, the analytical tools
with high spatial resolution flourished. The surface and thin film analysis
techniques x-ray photoelectron spectroscopy, Auger electron spectros-
copy, secondary ion mass spectroscopy and Rutherford backscattering
spectroscopy have grown in popularity in parallel to the decrease in the
 Introduction 7

vertical dimension of 0s. The new trace analyses technique Fourier

transform infrared, photoluminescence, deep level transient and reso-
nance ionization spectroscopy have emerged to compliment the more
traditional trace analysis technique, neutron activation analysis, reflecting
the need tocharacterize the higher purity materials. The low defect density
requirements for IC materials has given a boost to the defect imaging
techniques, transmission electron microscopy and x-ray topography. The
increased complexity of ULSI and VHSI circuits has been an incentive in
the development of the electrical evaluation technique voltage contrast.
At each new stage of miniaturization physical effects and phenomena
are encountered which were previously unknown orcould be neglected. It
is easy to imagine that this tendency will continue with each new level of
miniaturization. One might expect that the obstacles will be more difficult
to overcome the closer one gets to the ultimate limitations of the technology.
Although the majority of the material in this text does not directly address
these fundamental barriers, it does review the presentstate-of-the-art and
future directions which is in itself a reflection of the barriers that have
already been overcome.

REFERENCES

1. J.D. Meindl. IEEE Transactions on Electron Devices, ED-31 # 1 1, 1555 (1984).

2. A. Reisman, in VLSI: Technology and Design, Otto G. Folberth and Warren D.
Grobman, eds, IEEE Press, New York (1984).
3. R.W. Keyes, /EEE Transactions on Electron Devices, ED-26 #4,271 (1979).
4. F.H. Gaenssien, V.L. Rideout, E.J. Walker and J.J. Walker, /EEE Transactions on
E/ectron Devices, ED-24, 2 18 (1977).
5. P.K. Chatterjee, G.W. Taylor, A.F. Tasch, Jr., and H-S Fu, IEEE Transactions on
Nectron Devices, ED-26,564 (1979).
6. A.N. Broers, IEEE Transactions on Electron Devices, ED-28, 1268 (1981).
Silicon Materials Technology

William C. O’Mara
Aeolus Laboratory
Palo Alto, California

1. INTRODUCTION

This is the silicon age. Just as previous historical periods were named
by the characteristic material, we may assume that silicon will be seen as
paramount in importance to the era to which some refer as the second
industrial revolution. Certainly the transformation in the way people both
workandrelaxis beingchangedsignificantlybyelectronicdevicessuchas
computers, control systems, and audioandvideo products. These electronic
devices are all based on silicon, especially as used for integrated circuits.
Although a large amount of technical literature exists on silicon devices,
comparatively little has been written on the material itself. This is especially
true of material of an introductory nature. Thischapterattemptsasurveyof
the way silicon is made, and includes information on material properties,
especially as modified bythe presence of small amounts of oxygen. Silicon
turns out to be a fascinating substance, and readers of thisvieware invited
to turn to the references for further information.

2. SILICON CRYSTAL GROWTH

Pure silicon crystallizes from the melt in an open network of atoms

termed the diamond structure. It occupies the Group IV position below
carbon in the periodic table and has the same arrangement of tetrahedral
bonds found in the crystalline form of that element. Fortunately, synthetic
silicon crystals are much easier to prepare than those of carbon. They also
form the basis for the $30 billion, in 1984, semiconductor-device industry.
8
 Silicon Materials Technology 9

The method for single-crystal silicon growth was invented by Teal and
Beuhler in 1951.’ It was an extension of earlier work by Teal and Little in
which single crystals of germanium were prepared for transistor manufac-
turing.Germanium,likesilicon,occupiesaGroupIVposition in theperiodic
table, and has semiconductor properties that facilitated the initial device
manufacturing. However, the superior properties of silicon were soon
realized and the method was extended to this element. Pure material was
melted in a quartz crucible in an inert ambient, and a seed crystal was
lowered to begin controlled freezing of the melt. Dopants were added as
needed to control the electrical properties of the material. Reference 1
describes this early work in detail.
Production of silicon ingots today follows this same method, although
extensive improvements have been made in equipment, starting material
and process control. This section describes current practice, with emphasis
on material perfection andcontrolled impurityincorporation.Some people
refer to this method as Czochralski silicon growth, after an earlier experi-
mental method. However, this method was not designed for, nor did it
produce, single-crystal material.2 The ability of Teal and Little to make
single crystals repeatably was crucial to the growth of the solid-state-
device industry.
Other processes have been developed forsilicon-crystal growth. The
most important of these is the floating-zone method, in which thecrystal is
solidified from a small molten zone resting on the crystal itself. A polycrys-
tallinefeed rod is lowered from above into an RF induction coil which melts
its lower end. The rate of lowering is matched to the rate of withdrawal of
the crystal from below in order to maintain a constant melt volume. This
method differs from that of Teal and Little in that no crucible is employed;
the melt is suspended and maintained by surface tension. Because the
melt is not in contact with quartz, no oxygen is incorporated into thesilicon.
Some devices, such as high-voltage, high-power transistors, rectifiersand
thyristors require oxygen-free starting material. The majority of devices,
however, including virtually all integrated circuits, benefit from the presence
of dissolved oxygen and therefore require silicon grown from a quartz
crucible.
Several other processes have been investigated for the manufacture
of silicon devices.3 These include sheet-growth methods using dendrites
or fast-growing silicon-crystal forms, growth from dies or free-form crystal-
lization. Casting has also been employed to prepare ingots of large-grain
polycrystalline material. One product of these novel growth methods is
infrared window blanks for various applications. The main thrust of work in
this area, however, has been to prepare low-cost starting material for
photovoltaic applications. Currently, casting of polycrystafline ingots is
the most common way to prepare photovoltaic substrates.

2.1 Crystal Growth Equipment and Process

An example of the equipment used for silicon-crystal growth is shown
in Figure 1, and is represented schematically in Figure 2. The photograph
in Figure 1 shows a large water-cooled chamber which contains the
IO Semiconductor Materials

Figure
Figure 1:
1: Photograph
Photograph of
ofaamodern
modern silicon-crystal
silicon-crystal puller
puller (courtesy Kayex-Hamco).
(courtesy Kayex-Hamco).
 Silicon Materials Technology 11

HEATER

HEATER
CONNECTOR
ELECTRODE

Figure 2: Schematic cross-section of crystal puller.

heater, susceptor and molten-silicon charge. Mounted above the “hot

zone” chamber is the chamber intowhich the ingot is pulled. It is raised by
means of a chain mechanism which lifts the seed to which the ingot is
attached. The chain mechanism sits at the top of the crystal-growth
apparatus. To the right of the growth chamber, an electronic console
provides controls for heater power, seed lift, crucible and seed rotation, as
well as means for recording these for reference.
Modern crystal pullers product cylindrical silicon ingots ranging from
100 mm to 150 mm in diameter, from polysilicon charges ranging from 20
kgm to 40 kgm, with an ingot length of approximately one meter. Purified
polycrystalline starting material is loaded into a quartz crucible of 12”-14”
indiameter,alongwithsmallamountsofdopantneededtogivethedesired
electrical properties to the finished material. Because quartz is quite soft
at the melting point of silicon, 1425”C, the crucible is supported by a
graphite susceptor, which mounted on a graphite support which can be
rotated. This rotation helps to minimize the effects of temperature fluctua-
tions which arise from non-uniformities in heater resistance. The heater
itself is graphite formed into a cylinder and machined into a”picket fence”
which surrounds the susceptor. This forms a continuous resistive path for
current which heats it to greater than 1500°C.
12 Semiconductor Materials

In order to accomplish single-crystal growth, three things are needed.

First, aseed crystal must be used in orderthat thedesired atomicarrange-
ment will be achieved. The seed crystal is suspended from the chain and
lowered into the melt. It is typical to rotate the seed in a counter sense to
the crucible rotation. This promotes a homogeneous solid-liquid interface,
needed for microscopic uniformity of dopant distribution. The second
requirement for crystal growth is to locate the melt surface with respect to
the heater so that the proper temperature gradient is achieved along the
growing ingot. This is done by raising or lowering the susceptor support.
Initially this is somewhat of a trial-and-error procedure, but once the start
position is established it remains constant for a given puller. During ingot
growth, the crucible and susceptor are raised to maintain a more or less
constant melt position with respect to the heater as the melt volume
decreases. The third requirement for crystal growth is that the central
portion of the melt be cooler than the outer portion, so that freezing can
occur locally while the melt remains in a liquid state. Because heating
occursfrom theoutside, thisisautomaticallyaccomplished. However,very
precisecontrol of heatercurrent is required to bring the temperature at the
center to just the freezing point and not lower.
Molten silicon must be contained in a non-oxidizing atmosphere so
that SiO, formation is avoided. Nitrogen cannot be used because of silicon
nitride formation. Argon is most commonly used as the gaseous ambient,
although helium can be employed. Hydrogen, used originally by Teal and
Little, significantly modifies the properties of the material. As the molten
silicon continuously erodes the quartz crucible, silicon monoxide vapor is
evolved from the melt surface. Because of this continual vaporization,
crystal yields can be improved by reducing the pressure over the melt
surface. The reduced pressure, on the order of 30 torr, allows SiO to be
swept away from the furnace into a suitable trap where it cannot interfere
with crystal growth.
Automatic power supplies bring the heater temperature to a value
sufficient to melt the silicon, 1425°C. The seed is lowered into contact with
the melt, and the melt temperature is reduced slightly so that freezing can
begin onto the seed. Freezing proceeds laterallyfrom the!51 0 mm diameter
seed until the final ingot diameter of 100-l 50 mm diameter is reached. At
this point the seed lift is engaged, and further freezing adds to the ingot
height, but does not increase the diameter. Seed-lift rates of 50-l 00 mm
per hour are common for these ingot diameters. The upper portion of the
crystal-growth chamber contains an infrared sensor and lens which mon-
itors the bright edge of the solid-liquid interface during growth. Anydevia-
tions in the diameter of the crystal are translated into changes in seed lift
rate. These changes are automatically made in a way that brings the
dimensions of the crystal back within prescribed limits. If the diameter
increases beyond the control limit, seed lift is increased to reduce it and
vice versa for a diameter decrease. Crystal growth proceeds over the
course of several hours until 80-90% of the melt has solidified. At this point
the ingot diameter is reduced by raising the temperature. Diameter reduc-
tioncontinuesuntilthecrystaltailresemblesaninvertedconewithasharp
point. This practice prevents the thermal shock of furnace shutdown from
 Silicon Materials Technology 13

introducing dislocations into the lower end or tang of the crystal. These
dislocations, if introduced, could propagate upward and destroy crystal
perfection in much of the ingot.
An important improvement in crystal growth was made in the late
1950s by Dash,4 which allowed the production of ingots free of dislocations,
termed zero-D growth. The process, represented schematically in Figure
3, involves special growth conditions during the initial seeding process.
The seed is a single crystal of silicon, usually oriented along a <l OO> or
<l 1 1> direction. Although it is a single crystal, in general it will contain
dislocations or extended disruptions of the lattice. As material isadded to
the seed by freezing, the dislocationswill propagate. By reducing the seed
diameterto mm or half the initial diameter, and making useof the fact that
dislocationsvirtuallyalwaysmakeat leastasmallanglewith respecttothe
vertical axis, the seed can be grown to the point at which all dislocations
havereacheditssurface.Onceadislocationisatthesurface,itis“pinned”,
and substantial energy is required to initiate a new one. Subsequent
growth of the crystal is routinely maintained in the dislocation-free condi-
tion, and all silicon substrates are supplied in this state. The method of
Dash was crucial to the production of ingots of three-inch diameter and
larger, avoiding the tendency of large dislocated crystals to become
polycrystalline. Figure4 shows the stages of crystal growth in a production
puller, while Figure 5 shows a completed ingot ready for further processing.

I
I
L-SEED
I
I I

Figure 3: Method of Dash for dislocation-free crystal growth. Any dislocations

in the seed are allowed to grow to the surfaceand are pinned.4
14 Semiconductor Materials

Figure 4: View of silicon crystal being solidified from the melt.

Figure 5: Photograph of finished ingot.

 Silicon Materials Technology 15

2.2 Dopant and Impurity incorporation

Silicon is a good electrical insulator at room temperature in the pure
state. Dopantsareintentionallyaddedtolowertheresistivitytovaluesthat
approach metallic conductivity. Silicon also possesses the property of
conducting electricity by free electrons, as in metals, or by “holes”-the
absence of avalence electron. The hole representsawell-definedconduc-
tor because the crystal lattice is essentially perfect throughout the speci-
men.
Excess holes or electrons for the appropriate conductivity can be
introduced into the lattice by adding specific dopants or impurities during
crystal growth. Elements of Group III of the periodic table cause silicon to
be p-type, or positivelyconductingviaa hole mechanism. GroupVl elements
add free electrons to the material and result in negatively conducting, or n-
type silicon. Boron is used for p-type doping, while phosphorus, arsenic
and antimony can be used for n-type silicon. The incorporation of these
elements into the melt isafunction primarily of thesegregation coefficient,
a number unique to the material (silicon) and the impurity or dopant in
question.
When a relatively pure material freezes, any impurity is preferentially
rejected. The amount rejected is expressed bythe segregation coefficient,

where k = segregation coefficient = C,/C,

C, = concentration of impurity in the solid
C, = concentration of impurity in the liquid.

The segregation coefficient, k, is less than one forvirtuallyall impurities in

silicon except for oxygen. Some common elements and their segregation
coefficients are listed in Table 1. Because the impurity is rejected by the
freezing solid, theconcentration in the liquidgrowsasthe ingot iswithdrawn.
This is expressed by the following relation:

C, = C,k(l - g)k-’

where C, = concentration of impurity in the solid being frozen

CO = initial impurity concentration in the liquid
k = segregation coefficient
g = fraction of melt solidified.

This relation is shown graphically for a number of different values of the

segregation coefficient in Figure 6. The implication is that the seed end of
theingotislessheavilydopedwithimpuritythanthetang.Becauseofthisa
resistivity variation will occur along the length of the ingot. For boron-
doped ingots this variation is a factor of two, while for phosphorus it is a
factor of three.
Figure 7 shows the resistivity variation from seed to tail of a boron-
doped ingot. The first part of the ingot contains relatively little boron, so the
resistivityis high.Asthemeltfreezes,the boronconcentration buildsinthe
melt; none is lost by evaporation. Subsequent portions of the ingot contain
ever-increasing amounts of boron, so the resistivity decreases smoothly
from seed to tang. Figure 8 shows the axial resistivity variation of a
16 Semiconductor Materials

Table 1: Segregation Coefficients and Solid Solubilities

of Some Elements in Silicon

Element k Solubility (atoms/cm31

Electrical Dopants

Boron
Phosphorus
Arsenic
Antimony

Ubiquitous Impurities

Oxygen 1.25
Carbon 0.07
Nitrogen 7 x 10-4

Metals

Iron B x 1O-6
Nickel 2.7 x 1O-6
Copper 4 x 10-4
Gold 6 x 10-6
Aluminum 2 x 10-3

[concentro

06

001
0 01 02 03 04 05 06 07 08 (
Froctlon solldlfled,l

Figure 6: Incorporation of impurities as a function of melt fraction solidified.

Curves are shown for various values of the segregation coefficient.’
 Silicon Materials Technology 17

P-TYPE (100)
100mm DIAMETER

0 0.2 0.4 0.6 0.8 1.0

FRACTION GROWN

Figure 7: Plot of resistivity of boron-doped silicon as a function of distance from

seed end. Boron segregation during growth results in a decrease in resistivity
from seed to tang end of the crystal.

N TYPE (111)
3 INCH DIAMETER

I I I I
0 5 10 15 Xl

DISTANCE FROM SEED (inches)

(BREIlWISER)

Figure8: Plot of resistivity of phosphorus-doped silicon as a function of distance

from seed end. Resistivity dip near seed end is a result of fast growth rate here
and an effective segregation coefficient greater than the equilibrium values6
18 Semiconductor Materials

phosphorus-doped ingot.6 The lower segregation coefficient of 0.35,

compared to 0.8 for boron, leads to a steeper resistivity gradient along the
ingot. In addition, this particular ingot shows a resistivityvariation near the
seed end which does not follow the impurity incorporation expression for
normal freezing. After the ingot has reached the desired diameter, the
initial portion of the ingot is often withdrawn at agreaterrate than the lower
portion. This fast freezing causes impurities, especially those with low
segregation coefficients, to be incorporated in a non-equilibrium fashion.
The deviation is always towards an “effective” segregation coefficient
which is larger than the equilibrium value, which explains the high phos-
phorusconcentration (low resistivity) in the seed end of the ingot of Figure
8.
In addition, local fluctuations of dopant concentration can occur be-
cause of changes in growth rate or temperature. These can cause a
sudden increase in dopant level as the process deviates from equilibrium.
As a result, the uniformity of resistivity across a silicon wafer may vary by
f20%, forthe case of phosphorus. This variation is shown on a local scale
by means of spreading resistance measurements in Figure 9. Local vari-
ations of boron are typically less than +lO%.

=-1
LI

52
;=
4.5
(, ‘..~‘-..~,_:...,‘-...:
A,, 111’
. ..~ . . .. ” . ..-.. ,, _ ,,,_,._ I . “.,_, _.,:______:..,_‘-2

‘-
>2 6
Zi 5
Ei; A,, r2w, ... . . .-, ....> _.
;;‘ 4 .-.,a.. _,“,.._
__.,_./_._
#., ...,... ..A.” _.,..-‘~‘*
_.,.‘_‘ . . .. .;‘: ., .. .: : .;_.. ..

z
o 3
J CLOCHRALSKI GROWN N FWOSPHORUS HIII 3” WAFER

Figure 9: Fluctuations in resistivity from center to edge of a phosphorus-doped

wafer. Instantaneous growth-rate fluctuations also change the effective segrega-
tion coefficient.
 Silicon Materials Technology 19

2.3 Incorporation of Oxygen

In addition to intentionally added dopants, oxygen is incorporated into
siliconcrystalsduetothedissolutionofthequartzcrucible.Anymaterialin
contact with molten silicon will dissolve, with vitreous silica dissolving at
one of the lowest rates. It is the only material suitable to contain the melt,
and provides a source of oxygen to the melt throughout the growth
process. The rate of dissolution of the crucible is a function of the tempera-
ture at the crucible wall, and the stirring currents which sweep the oxygen
into the interior. An added factor is the escape of oxygen from the melt
surface in the form of SiO. This latter factor is a constant while the oxygen
sourcediminishesthroughoutthegrowthprocess.Thesourceofoxygenis
a function of the surface area of the crucible wetted by the melt which
decreases throughout the growth process.
This means that the oxygen incorporated into the crystal at the seed
end is the maximum amount possible for a given set of growth conditions.
Given fixed seed and crucible rotations, the oxygen level will decrease
from seed to tang end of the crystal. This is shown in Figure 10 fora3-inch-
diameter ingot. Modeling of this behavior has been presented bycarlberg
et al.’ Because SiO is escaping from the edge of the solid-liquid interface,
the oxygen level is lower at the edge than the center. This fall-off in oxygen
level is shown in Figure 11. This data was obtained from the same 3” dia-
meter ingot as Figure 10.

SEED 3 6 9 12 15 18 TAIL

DISTANCE FROM SEED (INCHES)

Figure 10: Axial gradient of oxygen in a silicon crystal. Oxygen measured accord-
ing to ASTM F 121430.
 Semiconductor Materials

a _ j . - . SEED

0 10 20 30 40

DISTANCE FROM CENTER OF INGOT (mm)

Figure 11: Radial variation in oxygen level.

Ingot manufacturers have attempted to develop ways to control the

level of oxygen in crystals. This is because the oxygen level affects wafer
performance in several ways, some beneficial, others harmful to device
yield and performance. Oxygen at some level is essential forthe majority of
devices, and is the reason why float-zone silicon, which is oxygen-free,
cannot be used in the vast majority of device applications. In the standard
crystal-growth method of Teal and Little, the control of oxygen level is
primarily obtained by the variation of seed and crucible rotations.8 In this
way, the stirring currents that sweepoxygen into the melt and past thesolid-
liquid interface are controlled. The limits on this control are due to the fact
that seed and crucible rotations also control the uniformity of dopant
incorporation for electrical resistivity. This limits the oxygen levels to a
range of 1O-20 ppmA for standard crystal-growth processes.
The direct determination of the segregation coefficient of oxygen in
silicon byyatsurugi et al. indicatedavalueof k= 1 .25.gThisvalue has been
thesubjectofrecentdispute,withindirectdeterminationsorestimatesofk
= 0.3 to k = 1.4.1° A value of k greater than one suggests two distinct
oxygen species, since the “interstitial” oxygen incorporation was shown
by Yatsurugi to have k = 1.O. The predominant form of oxygen in silicon is
this interstitial species, which actually consists of oxygen lying between
two near-neighbor silicon atoms, forming a nearly linear Si-0-Si structure
in place of the Si-Si bond. It is not a true interstitial species. If the segregation
coefficient of this species is 1 .O, and the overall segregation coefficient is
1.25, then a second form of the atom in the lattice is indicated. The original
suggestion for the form of this second species was small oxygen clustersg.
I have suggested that the second oxygen species exists in the form of a
fully substitutional atom, which is incorporated into the lattice with a
segregation coefficient of 0.25.” This ideacan help to explain many of the
puzzling features of oxygen in silicon, such as the existence of oxygen
striations in silicon,12 and the striated distribution of the oxygen donor in
the material.13 Effects related to precipitation of oxygen from solution are
discussed in a later section.
 Silicon Materials Technology 21

2.4 Incorporation of Carbon

Carbon has a low segregation coefficient of 0.07, which means it is
stronglyrejected bythefreezingsilicon. It isneverintentionallyaddedasa
dopant, but may be present from one of three sources. The polysilicon
charge itself may contain carbon, but this is unusual. At times, the silicon
charge may contain previously melted silicon, or “remelt.” This remelted
silicon is enriched in carbon from the previous segregation. Finally, the
melt mayentraincarbonfromCOgaspassingoverit.Thesourceofthisgas
is a water or oxygen leak in the furnace which reacts with hot graphite.
The three situations are depicted in Figure 12. The maximum level of
carbon is due to remelt in the original charge. The next-lower level of
carbon is due to standard polysilicon in a furnace operated at one atmos-
phere pressure. When the overpressure is reduced to 30 torr, the CO
entrained in the melt is much reduced, and the lower curve of carbon
incorporation is obtained. As will be shown later, high levels of carbon are
uniformly detrimental to material and device performance.

.2 .4 .6 .0 1.0
FRACTION GROWN

Figure 12: Carbon concentration versus fraction of melt solidified for three con-
ditions of crystal growth: circles represent the maximum level of carbon due to
remelt in the original charge, triangles represent crystals grown with standard
polysilicon at atmospheric pressure and squares present data for material grow.n
with standard polysilicon but a reduced pressure of 30 torr.
22 Semiconductor Materials

3.0 WAFER PREPARATION

3.1 Mechanical Shaping Procedures

As-grown silicon ingots are subjected to a number of mechanical and
chemical operations to prepare slices or wafers ready for device manufac-
ture. The mechanical steps begin with grinding of the ingot to make it
perfectly cylindrical, followed by the grinding of one or more flats along its
length. The flats define specific crystal planes in the material such as the
(100) or (1 10) planes, and serve to identify wafer orientation and type. The
flatting procedure is guided by X-ray orientation of the ingot. Diamond-
tipped grinding tools similar to those in many machine shops are used for
thisprocedure.Grindingandflattingoperations,aswellasthesubsequent
mechanical operations of slicing, lapping and edge rounding, introduce
subsurface work damage into the material. Great care is taken to avoid
cracks and fractures, and the remaining damage issubsequently removed
by etching.
Silicon ingots are produced with flats for two purposes. Originally,
finished die on a waferwereseparatedfor packaging by scribing along the
directions of crystal planes and breaking the wafer into squares along
directions of easy cleavage. The orientation flat at one side of the wafer
served to guide the alignment for scribing. Although die separation is now
more commonly done by means of a diamond saw, the crystal planes are
still chosen for sawing. In addition, automatic handling equipment makes
use of the flat for wafer orientation in photolithographic mask alignment
and other operations.
An additional function of wafer flats is the use of a second, minor flat in
combination with the primary(1 10) flat to identifywafertypeand orientation.
This function has been standardized by the Semiconductor Equipment
and Materials Institute (SEMI), a trade organization of suppliers to the IC
industry. Figure 13 showsschematicallythefourcombinationsofflats that
identify p- and n-type, and (1 1 1) and (100) orientations. This allows visual
verification of these parameters and helps to avoid mixing of wafer lots.
After grinding, the ingot is mounted on a graphite beam for slicing.
Again, X-ray orientation serves toensure that cutsare madeon thecorrect
crystal orientation. Most (100) oriented ingots are cut parallel to the (100)
plane. (111) oriented crystals can either be sliced on orientation, or39 off
orientation towards (110). The latter choice is made when an epitaxial
silicon layer will be grown on the wafer in order to improve the growth
kinetics of the layer. Figure 14 shows a schematic diagram of the slicing
process. The mounted crystal is held near a thin stainless-steel blade
which is coated with diamond grit on its innersurface. The blade resembles
a drum head with a central hole, and is rotated in a spindle at several
thousand RPM. The blade is lowered at a rate of 1-3 inches per minute
through the silicon, cutting a wafer or disk from the ingot. Indexing equip-
ment allows the setting of wafer thickness. If the blade does not cut true,
either bow ortaper can be introduced into the slice as shown in the figure.
These undesirable deviations from flatness can be detected by an eddy
current sensor, shown mounted above the blade near the crystal. The
 Silicon Materials Technology 23

-I-
PRIMARY f? PRIMARY

-l FLAT
I
FLAT

SECONDARY
FLAT

11 111 n-TYPE
(3 111 P-TYPE

FLAT

( 1 100 ~-TYPE
{
100) p - TYPE

Figure 13: Semiconductor Equipment and Materials institute (SEMI) standard

flat locations for silicon wafers.

sensor indicates blade deviation which can be corrected by appropriate

dressing of the grit.
Sliced wafers receive two additional mechanical operations. The wafer
edge is rounded orcontoured to reduce edgechipping in subsequent use.
In addition, the front and rear surfaces are made flat and parallel by
planetary lapping. In this operation, a Sic or Al 203 slurry is used to remove
a small amount of silicon while the wafers are rotated between two steel
plates. This operation leaves wafers flat to as little as 1 pm deviation of
flatness over the entire wafer diameter.

3.2 Wafer Etching

Mechanical machining to produce a wafer of the desired thickness
and flatness produces a layer or skin on the waferwhich is workdamaged,
containing numerous dislocations. The damaged layer is removed by a
chemical etching step, which may also reduce work-induced stress and
remove contaminants introduced into the material. Etching can be done
usingamixtureof hydrofluoric, nitricandaceticacids,orbyusingacaustic
KOH bath. The former technique produces a smooth, featureless surface,
whereas the latter etch leaves the surface with microscopic pits and a
specular appearance. KOH etching is finding favor because of its ease of
handling and disposal.
24 Semiconductor Materials

i Blade

i Axial Blade
l4Movement
3
:.

blade
/

Figure 14: Schematic of ingot-slicing operation. Blade mounting and condition-

ing are done carefully to allow for straight cuts. Blade deviation can result in
either bow (cuts 1 and 3) or taper (cuts 1 and 2) in the slice.

Chemical etching is sometimes followed by are-introduction of damage

in a controlled fashion on the backside of the wafer. Damage is introduced
by sandblasting with fine quartz spheres, or by abrasion with sandpaper. A
shallow networkof dislocations is introduced into the wafersurface. Some
users find this damaged layer helpful in preventing haze formation on the
front side of the wafer during initial oxidation. As a result, wafers treated in
thiswayaresupplied at customer request. A recent alternativeapproach is
to deposit a layer of polysilicon on the wafer backside, which functions in a
similar way to abrasion.
A new operation is being introduced into wafer manufacturing, often
after the etching step, in which a laser is used to mark the wafer surface
withanidentificationcode.Thiscodecontainspertinentinformationabout
 Silicon Materials Technology 25

the wafer characteristics, and can be read visually or with an automated

reader. The code number is generally placed on the front surface near the
major flat.

3.3 Polishing
Front-surface polishing of the wafer leaves it with a mirror finish
needed for device fabrication. Wafers are mounted on carriers for this
operation, held either by a thin wax layeror byafriction bond to thecarrier.
These carriers are pressed onto a rotating polishing pad of polymeric
material while a polishing slurry isapplied. Generally the processconsists
of two steps on two different polishing machines. In the first step, perhaps
0.001”oronemilofsiliconisremovedfromthesurfaceinaprocesstermed
stock removal. The carrier is then moved to a machine with a smoother pad
surface for final, mirror-finish polishing.
The polishing slurryconsistsof a solution of colloidal silica maintained
atapHof 11 forstockremovalandapHof9forfinishpolish.Thefunctionof
the silica in the polishing process is not understood. It is probable that the
product of the polishing process is silica itself. That is, the surface of the
wafer is oxidized and hydrated to form a silica that can be wiped away by
the pad. It is curious that one must add the reaction product to initiate the
polishing process. The silica acts as some sort of catalyst, and the primary
polishing agent is probably water!15

3.4 Cleaning
Thefinalstepinwaferpreparationisacarefulc1eaningofthesurface.A
sequence of acids and bases is used to remove any contaminants, including
wax residues, if any, and metallic contaminants in the polishing medium.
The cleaning process is assisted by adding hydrogen peroxide to oxidize
these materials, and by heating the liquid baths. The basis for chemical
cleaning has been established by Kern.16
The final bath in chemical cleaning process is usually chosen so that
the wafersurface is hydrophilic, orwater-loving. This means that thewater
wets the surface as the wafer is withdrawn from the bath, and can be
removed uniformly. Acombination of ammonium hydroxide and hydrogen
peroxide is an example of such a bath. On the other hand, a wafer
withdrawn from a hydrofluoric acid bath will be hydrophobic, and waterwill
bead on its surface. This beading can lead to spots on the surface afterthe
water dries. The difference between a hydrophilic and hydrophobic surface
consists of the difference in the native oxide thickness. Silicon will instantly
grow a thin oxide upon emerging from a chemical bath. In the hydrophobic
case, the oxide thickness is 1OA or so, while for the hydrophilic case the
oxide thickness can range from 155OA, depending on bath characteristics.
This can lead to variations in thickness of a subsequent thermal oxide
layer. This variation is important for thin gate-oxide-layer growth in MOS
device fabrication.
Throughout the fabrication process, wafers are inspected for a variety
of parameters including physical dimensions, electrical resistivity, flatness
and surface perfection. Afterfinal inspection, most wafers are packaged in
 Next Page

26 Semiconductor Materials

Class 100 clean rooms in such a fashion that the cleanliness will be
maintained until use by the customer.

4. MATERIAL PROPERTIES

4.1 Crystal Structure

Silicon crystallizes in an open, low-density structure termed the diamond
lattice structure, which it shares with the gemstone modification of carbon,
the single-crystal form ofgermanium, and one of the crystalline forms of tin.
In this structure, each atom is bonded to four near neighbors arranged
tetrahedrally about the central atom. The local arrangement is repeated
throughout the crystal, giving rise to the unique properties of the material.
Atoms are joined to each other by Sp3 hybrid covalent bonds, which are
quite stable. The bond strength is25 kcal permoleforsilicon, and the near-
neighbor spacing is 2.35.&.. If one looks at a silicon lattice containing
several atoms, he can see that a cubic structu re is formed. A diagram of this
structure is shown in Figure 15. There are actually two interpenetrating
cubic structures, with an atom at each cube face. The cube side has a
dimension of 5.43.&..
The regular crystal structure of covalent bonds is quite inert. Very pure
silicon is a good electrical insulator with an energy of 1.11 eV required to

Figure 15: Silicon lattice structure,

2

The Thermal Oxidation of Silicon

and Other Semiconductor Materials

Bruce E. Deal
Research Center
Fairchild Semiconductor Corporation
Palo A/to, California

1. INTRODUCTION AND BACKGROUND

The thermal oxidation process associated with semiconductor tech-

nology has been used primarily in conjunction with silicon and silicon
containing materials. Attempts to thermally oxidize germanium and com-
pound semiconductors have been generally unsuccessful, except by
employing a field-assisted process such as anodizing. More often,
deposited oxides and dielectrics have been used to passivate compound
semiconductors, while germanium is not a significant factor in today’s
semiconductor industry. A description of CVD (chemical vapor deposition)
and other deposition processes used for dielectric films in semiconductor
applications is included in other chapters of this volume.
Silicon semiconductortechnology has depended heavily on the thermal
oxidation process since the 1950’s, when silicon devices were first
developed. Initially, thermal oxides were used toselectively mask dopants
during the fabrication of diffused transistors.’ Additional investigations at
that time byAtalla, Liginza, Spitzer, and otherworkersat Bell Laboratories
provided considerable information about silicon thermal oxides, especially
their passivation properties. *f3 These investigations led in 1960 to two of
the most important developments of semiconductortechnology: the Planar
process invented by Hoerni,4 and the MOS transistor which was first
disclosed by Kahng and Atalla.
46
 Thermal Oxidation 47

Many investigations related to silicon thermal oxidation and other

types of dielectric films have been undertaken since 1 960.6n7These have
resulted in a number of technological developments and have helped to
makepossibletheamazinggrowthofthesemiconductorindustrSomeof
the uses of thermal oxides and dielectric films in today’s semiconductor
technology are listed in Table 1. Thermal silicon dioxide is and will most
likely continue to be the mainstay of silicon device technology, even as we
move into the realm of sub-micrometer VLSI and beyond.

Table 1: Uses of Dielectric Films in Semiconductor Technology

. COMPONENTS IN DEVICES
. CORROSION PROTECTION

. DEVICE ISOLATION
. DOPANT DIFFUSION SOURCE

. GETTER IMPURITIES
. INCREASE BREAKDOWN VOLTAGE

. INSULATE METAL LAYERS

. MASK AGAINST DOPANTS
. MASK AGAINST IMPURITIES
. MASK AGAINST OXIDATION
. MECHANICAL PROTECTION
. PASSIVATE JUNCTIONS
. SMOOTH OUT TOPOGRAPHY

This chapter deals primarily with the thermal oxidation of silicon. The
kinetics of silicon thermal oxidation is first reviewed, with emphasis on the
general oxidation relationship and the thin oxide regime. Important oxide
properties are then summarized. Following is the most important part of
the chapter, a description of process variable-oxidation reaction inter-
dependencies. Some of the variables included are effects on silicon
surface properties (dopant redistribution, charges), surface property
effects on the oxidation process (orientation, doping, cleaning), and
ambient effects (type, chlorine addition, pressure). After a discussion of
oxidation mechanisms, the chapter concludes with a section on other
oxidation processes and an indication of thermal oxidation applications
and trends with respect to future semiconductor devices.

2. SILICON THERMAL OXIDATION KINETICS

The thermal oxidation process provides superior passivating charac-

48 Semiconductor Materials

teristics for silicon devices as compared to the various deposited dielectric

processes. Used in combination, however, with other dielectrics (e.g.
deposited silicon nitride over thermal oxide), the most stringent require-
ments can be met. In the thermal oxidation process, silicon reacts with
either oxygen or water vapor (steam) at temperatures between 600” and
1250°C to form silicon dioxide.The oxidation reaction may be represented
by the following two reactions:

Si 4. O2 -c Si02 I 11

Si + 2H20 + SiO 2 t 2H2 I 21

Special marker experiment9 have demonstrated that oxidation pro-

ceeds by the diffusion of either an oxygen or water species through the
oxide already formed which then reacts with the silicon at the Si-SiO,
interface. As oxidation continues, the interface moves into the silicon and a
new, clean silicon surface is produced. As a result, original silicon surface
states(unsatisfied bonds) and contamination are consumed and optimized
device passivation is achieved. From the densities and molecularweights
of silicon and amorphous silicon dioxide, it can be shown that for every
thickness x, of oxide formed, 0.45 x, of silicon is consumed. The exact
nature and charge of the diffusing oxidation species (0,, 0, O,-, O-, H,O,
H30+, OH-, etc.) have not yet been identified. It is known, however, that for
steam oxidation, considerable exchange occurs between the already
formed silicon dioxide and the diffusing water species. On the other hand,
very little exchange takes place between oxygen and the oxide network.
Thermal oxidation of silicon is normally carried out in a fused quartz
tube in a resistance heated furnace. The silicon wafers are placed vertically
in slots in a flat quartz “boat,” most present day furnaces accommodating
up to200 four to six-inch diameterwafers. Fordry 0, oxidation, high purity
oxygen from a liquid source is transported into the furnace tube through
suitable regulators, valves, traps, filters, and flowmeters. For a number of
years, water or steam oxidation was carried out by bubbling 0, or N,
through a flask of deionized water maintained at a particular temperature.
Thusaspecifiedvaporpressureofwatercould beprovidedintheoxidizing
ambient. More recently, however, pyrogenicsystemsg have been employed
which permit H, to react with 0, at the inlet end of the oxidation tube, thus
providing water vapor of much higher purity and control.
Silicon oxidation data are obtained by determining oxide thickness
(x4 as a function of oxidation time(t) and other variables such as oxidation
temperature and silicon orientation. Typical results are given in Figure 1
and 2, which contain plots of log x0 vs log t for silicon oxidation at various
temperatures in dry 0210 and pyrogenic steam.”

2.1 General Relationship

As indicated earlier, silicon thermal oxidation proceeds by thediffusion
 Thermal Oxidation 49

1.0 10.0
OXIDATION TIME (hr)

Figurel: Oxide thickness vs oxidation time for silicon oxidation in dry oxygen
at various temperatures (after Hess and Deal”).

2.0
1.5

1.0

-z 0.5

,i
4n
2 0.2
5
u
z 0.1

8
z 0.05
0

0.02

0.01
0.1 0.2 0.5 1.0 2 5 10 20 30
OXIDATION TIME hr)

Figure 2: Oxide thickness vs oxidation time for silicon oxidation in pyrogenic

steam t-640 Torr) at various temperatures (after Deal”). Reprinted by permis-
sion of the publisher, The Electrochemical Society, Inc.
50 Semiconductor Materials

of an oxidizing species through the oxide already formed. This process is

indicatedinFigure3. It hasbeenproposed byDealandGrove12thatduring
thermal oxidation three consecutive reactions occur whose fluxes are
equal under steady-state conditions. These are denoted in Figure3 and are
summarized below, along with the expressionswhich represent the fluxes
(flux (F) is defined as the number of molecules-in this case oxidant-
crossing a unit surface area in a unit time).

02
(a)

Figure 3: Schematic illustration of tie silicon thermal oxidation process.

(a) Transfer of the oxidant from the gas phase to the oxide
outer surface:

Fl = h (C’ - Co) c 31

where h is a gas-phase transport coefficient, C, is the

concentration of the oxidant in the outer oxide surface,
and C* is the equilibrium concentration of the oxidant in
the oxide, and assumed to be proportional to the partial
pressure of the oxidant in the gas ambient.
lb) Diffusion of the oxidizing species through the oxide to the
silicon:
Co-Ci
F2 = -Deff x0

where D,,, is the effective diffusion coefficient of the

oxidizing species in the oxide, C, is theoxidantconcentra-
tion in the oxide near the Si-SiO, interface, and x0 is the
oxide thickness.
(c) Reaction of oxidizing species with silicon at the Si-SiO,
interface to form SiO,:

= kCi I 53
*3

where k is the interface reaction rate constant.

 Thermal Oxidation 51

By assuming all the above fluxes to be equal, the following general

oxidation relationship has been derived.12
2
xO + Axo
= B(t+T)
C 6a3
also written in the form

I 6bl

where x0 = oxide thickness, t = oxidation time, and A, B, r, and xi are

constants as defined below:

A = 2 Deff (l/k + l/h) [ 71

B = 2 Deff C./N1 c 81
T = $2 + Axi)/B c 93

where D,rr = effective oxidant diffusion constant in the oxide;

kh = rate constants at the Si-SiO, and gas-oxide interfaces;
C* = equilibrium concentration of the oxide species in oxide;
N, = number of oxidant molecules in the oxide unit volume; and
‘i
= oxide thickness at the start of oxidation.

Two limiting forms of Equation 6 can be noted. At large oxidation

“times,” i.e. tnA2/4B and tur

= Bt 1103
X02

This equation represents a parabolic oxidation and B is the parabolic

rate constant.
For small oxidation “times,” t ((A2/4Band the linear oxidation expression
is obtained:

X o = B/A(t+r) 1111
B/A is the linear rate constant.
From Equations 7 and 8 it can be noted that when the oxidation
process is controlled primarily by the parabolic rate constant (at high
temperatures or thick oxides), the kinetics are affected by changes in the
diffusion process or oxidant solubility in the oxide. The latter is proportional
to ambient pressure. On the other hand, at low temperatures or for thin
oxides, where the linear rate constant predominates, the oxidation is also
sensitive to oxidant solubility in the oxide (and ambient pressure) but
depends on those factors affecting the interface rate constants h and k.
These effects will be discussed in more detail later.
Special mention should be made of the correction factor r which is
related to initial oxide thickness x, in Equation 9. It has been noted that for
oxidation in dry O,, an initial thickness region does not appear to be
satisfied by the general relationship Equation 6. Rather, the plot of oxide
thickness versus oxidation time tends to extrapolate through the thickness
52 Semiconductor Materials

axis at about x= 15OA. Thus, in the absence of a model for oxidation in this
region, the practice has been to assign a value of r corresponding to xi=
15OA. Further discussion on the mechanism of thermal oxidationforthese
very thin oxides is presented in the next section.
The thermal oxidation of silicon can be represented by Equation Gfora
wide range of temperatures, oxide thicknesses, orientations, and oxidation
ambients, provided the dependence of the rate constants 6 and B/A as a
function of these variables is known. Values of the rate constants have
been determined by rearranging the general relationship Equation6 intoa
linear expression, plotting x0 vs (t+r)lx, and extracting B as the slope and
-A as the intercept from the resulting plots. Arrhenius expressions of the
form

c s +E’kT 1123

have been used in plotting log B and log B/A vs l/T. Such plots are
presentedin Figures4and5,andvaluesoftheconstantsfortheArrhenius
expression are tabulated in Table 2. These data can be used to determine
any thickness-time relationship for a given set of oxidation conditions.
Similar data are incorporated in the SUPREM program13 and related
computer process modeling programs.

1.0 1 I I 1 1

‘;:
f

% HZ0 (640 Tow)

El\ = 0.78 eV
al
\
+
-- 0.1 \ ‘\ -
5
k
8

P
2
” O.Ol-

O.OOl
0.6 0.7 0.6 09 1.0
1000/T (OK)

Figure 4: Dependence of the parabolic rate constant B on temperature for the

thermal oxidation of silicon in pyrogenic steam (-640 Torr) and dry oxygen
(after Deal”). Reprinted by permission of the publisher, The Electrochemical
Society, Inc.
 Thermal Oxidation 53

1o.c

z
‘E l.O-
s
s
I- Ol-
i

w O.Ol-

5
%
y O.ool-
2

O.cool I I I 1

0.6 0.7 0.6 0.9 1.0 1.1

1000/T (OK)

Figure 5: Dependence of the linear rate constant B/A on temperature for the
thermal oxidation of silicon in pyrogenic steam l-640 Torr) and dry oxygen
(after Deal” 1. Reprinted by permission of the publisher, The Electrochemical
Society, Inc.

Table 2: Dependence of Silicon Oxidation Rate Constants on Temperature

PARABOLIC B = C, ,qWkT

LINEAR B/A = C2 6+2/kT

(111) SILICON
DRY 02 Cl ~7.72~10~ pm’/hr
Cp 26.23 x lo6 pm/hr
El = 1.23 eV
E2 = 2.0 eV

STEAM Cl = 3.86x lo2 pm2/hr

(PYR~GENIc)
C2 = 1.63 x lo* pm/hr
El =0.78 eV
E2 = 2.05 eV

(100) SILICON cp (100) = cp (111)/1.7

54 Semiconductor Materials

2.2 Thin Oxide Formation

As indicated above, considerable experimental evidence is available
which suggests a different or modified reaction mechanism for dry 0, thermal
oxide formation below 2OOA This difference has resulted in the requirement
(in the case of dry 0, oxidation) for the use of a constant, r, in the general
relationship, Equation 6. A number of investigators have attempted to
model the thermal oxidation process in the very thin regime, but as yet no
one satisfactory relationship has been established. Likewise, the exact
characterization of thin oxide properties, electrical, physical, etc., has not
yet been accomplished. These properties are undoubtedly related to the
kinetics of thin oxide formation and also makeaccurate thickness measure-
ments quite difficult.
Among the first to investigate the mechanisms involved in the initial
stages of silicon thermal oxidation were van der Meulen and Ghez.14.15
They proposed complex reactions at the Si-SiO, interface involving both
molecularand atomic reactions with silicon. Thus, various reported pressure
dependencies of the oxidation reaction on oxygen partial pressures could
be explained,with P’.Odominatingforthickeroxidesand Po.5being prevalent
in the thinner oxide regime. Blanc16 has proposed a similar model but with
only a Po.5dependence for thin oxide formation. This, however, does not
satisfy pressure dependencies observed for thicker oxides.
More recently Massoud and Plummer17 have suggested that the initial
stages of silicon oxidation in dry 0, may be represented by the following
equation:

ax [I31
Ois
dt & + Cl-p
0

In this expression, the first term on the right-hand side is the contribution
from the original linear-parabolic model. The second term incorporating L,
is possibly related to effects of residue left on the silicon surface from the
cleaning treatment (X, 5 15A). The contribution of L, has not yet been
explained. Subsequently, Han and Helms18 have proposed that a mechanism
based on parallel diffusion reactions provide even a better fit to oxidation
data over the entire thickness range.
It is important for future applications of devices having sub-micrometer
feature sizes and film thicknesses in the nanometer range (especially
MOS gate and capacitoroxides), that reaction mechanisms be understood
and characterized for oxides in the very initial stages of formation. The
investigations described are a good step in that direction.

3. PROPERTIES OF THERMAL OXIDES

Thermalsilicon dioxide(Si0,) produced bytheoxidationof silicon in0,

or H,O at elevated temperatures is essentially amorphous silica. Its proper-
ties are almost identical to those of the fused quartz tubes in which most
oxidations are carried out. The molecular structure is a random version of
 Thermal Oxidation 55

crystalline quartz with each silicon atom tetrahedrally surrounded by four

oxygen atoms. In turn each oxygen atom is bonded to two silicon atoms.
Thermal oxides act as somewhat of a barrierto high-temperature diffusion
of the common dopants 6, P, As, and Sb and can be used as a mask against
ion implantation. Forthese cases, masking is limited and suitable masking
data curves must be used to ensure that the species are prevented from
penetratingintothesubstrate.On theotherhand,alkaliimpurityions,such
as Li+, Na+, K+, and even H+ or Hz0 can diffuse rapidly through thermal
oxide, even at relatively low temperature. In general, other more dense
dielectric films, such as silicon nitride or phosphosilicate glass, are used in
combination with thermal oxide to passivate against these impurities.
Thermal SiO, is normally quite stable chemically. The most common
etchant is an HF-based solution. Optical and electrical properties are
similar to those of fused quartz.
Electrical properties of thermal oxides are extremely critical with
respect to device performance and reliability. Such parameters, as conduc-
tivity, carrier trapping characteristics, and oxide charges, can have an
appreciable effect on today’s small-geometry integrated circuits. These
properties have been evaluated by appropriate techniques for varying
preparation conditions.lg Also critical to devices is the defect density of
passivating oxides. Many investigations have been reported that are
related to dielectric strength, pinhole density, and other oxide properties
which result primarily from impurity incorporation during processing.20 A
number of common properties of thermal SiO, are listed in Table 3.
Various techniques are used to measure properties of thermal oxide
films. One of the most important properties, thickness, is determined
primarily by ellipsometry or other spectrophotometric or interferometric
methods. Typical film thicknesses range from over 1 pm to below 1OOAin
special devices. Since structural and optical properties of the thinner films
maydifferfrom bulk properties, somedifficultiesarise in thin oxide measure-
ments.

4. PROCESS VARIABLE/OXIDATION REACTION DEPENDENCIES

The silicon thermal oxidation process has been found to be a direct

functionofanumberof processvariablesincludingsiliconsurfaceproper-
ties. Conversely, some important silicon surface propertiesaredependent
on the oxidation process. In Figure 6, one form of the general oxidation
relationship (Equation 6b) is re-presented, with an indication of some of
thephysicalvariableswhichcontributetotheoxidationreactionthrough the
individual components of the rate constants. In this section, some of the
important inter-relationships between processvariablesand theoxidation
process are discussed.

4.1 Effects of the Oxidation Reaction on Surface Properties

4.1 .l OxIdeCharges. At leastfourgeneraltypesofelectricalcharges
have been observed to be associated with the thermally oxidized silicon
56 Semiconductor Materials

Table 3: Properties of Thermal Silicon Oxides (25% unless indicated)

Physical Properties

Formula Si02

f4alecularweight 60.08

Molecules/cm3 2.3 x 1O22

Density 2.27 gm/cm3

Melting point ..1700=x

Specific heat 1.0 Jouls/g"c

-3
vapor pressure 10 Torr at 145OOC

Thermal conductivity 0.014 watt/cm'C

Linear coefficient of 0.5 Y lo-60c-'

expansion

Young's modulus 1 X 10' psi

Electrical Properties

Resistivity 5 x 10l5 n-cm

Dielectric constant 3.9

Dielectric strength -1 x lo7 v/cm

Energy gap -8 cv

optical Properties

Refractive index 1.462 at 5459 ;

Absorption coefficient SO for E < 8 eV

Chemical Properties

Etch rate (1:lO HF:H20) 5 :/se,

Oxygen solubility 5.5 x 1016 cl?&-3

at 1OOO~C
19
water so1ubi1ity 3.4 x 10 cm-3 at 1000v

structure.21s22 These charges and their locations are indicated in Figure 7,

which is a representation of an oxide cross section similarto that shown in
Figure 3. The symbols selected to denote these charges23 are based on
the following:

Q = effective net charge per unit area at the Si-SiO, interface

G/cm*),
N = Q/q = net number of charges per unit area at the Si-SiO,
interface (number/cm*),
D = net density of interface trapped charges per unit area and
energy (number/cm*-eV),
q = charge of an electron.
 Thermal Oxidation 57

GENERAL RELATIONSHIP

( x02 - Xi21 + (Xg- Xi)

= t
0 B/A

PARABOLIC RATE CONSTANT

B = 2DC*/N,
+I
OXIDIZING SPECIES PRESSURE
I
L SOLUBILITY OF OXIDANT IN OXIDE
OXIDANT DIFFUSION COEFFICIENT IN OXIDE

LINEAR RATE CONSTANT

B/A =

AT SiOe -AMBIENT INTERFACE

REACTION AT Si-SiOe INTERFACE

SOLUBILITY OF OXIDANT IN OXIDE

Figure 6: Relationship of process variables to oxidation general relationship.

TRANSITION
REGION

y INTERFACE
TRAPPED CHARGE, Q,t

\ t
\
\

0 N$
MOBILE IONIC
t
CHARGE Om ++++ +
---- +

i
OXIDE TRAPPED + .FIXED OXIDE
+ CHARQE. Of
CHARGE. Oet

Figure 7: Names and location of charges associated with the thermally oxidized
silicon structure.
58 Semiconductor Materials

A brief description of the four types of charges is presented. As may be

noted, all of them are directly related to the oxidation and associated
processing. Techniques for measuring the charge densities are also
indicated.
Fixed Oxide Charge; Q,, N,. As indicated in Figure 7, the fixed oxide
charge is positive and located in the oxide very close to the Si-SiO,
interface (<20 ). It is due primarily to structural defects (ionized silicon) in
the SiO, lattice and directly dependent on conditions of oxidation. For
instance, its density which ranges from lOlo to lo’* cm-* depends on
oxidation ambient and temperature, anneal/cooling conditions, and silicon
orientation.** Its density normally does not vary with surface potential
which distinguishes it from interface trapped charge-hence the name
fixed oxide charge.
An important Q, process relationship is that the density of Q,for either
steam or dry 0, oxidation increases with decreasing temperature.21~22~24
However, a subsequent anneal in an inert ambient such as argon will
decreasethedensityofQ,toaminimumequilibriumvalue,givingrisetothe
“Cl, triangle” effect?’
Another important property of fixed oxide charge is that its effective
density can be increased by the application of high negative fields to
fieldplates of an MOS structure at moderate temperatures (1 Oo”-4OO”C).*’
This increase is proportional to the applied field as well as the initial Q,
density. The interface trapped charge density also increases as a result of
negative field application. Such an effect can lead to instabilities in p-
channel MOS devices.
Mobile Ionic Charge; Cl,,,, N,. The mobile ionic charge is primarily due
to the positive alkali ions, Li+, Na+, K+, and also possibly H+. In addition, it is
possible to observe charge effects due to the larger negative ions such as
F-, Cl-, and also Cs+, Au+, and the like. These latter ions normally do not
migrate at typical device temperatures, however, and will not lead to
instabilities. Likewise, their presence is more difficult to detect. The field-
induced “drift” of the alkali ions is the leading cause of instabilities in MOS
devices25 and the rate of drift is inversely proportional to ion size(Li+> Na+
> K+).
Almost every semiconductor device fabrication step can be a source
of ioniccontamination. Elaboratesteps have been established to minimize
their effect. Since this is impossible on an absolute basis, special “gettering”
processes have been developed.26 These involve the use of phosphorus
glass, chlorine species, or other materials which can complex or getter
impurity ions from the oxide and render them inactive. Dense dielectric
films such as silicon nitride are also used to mask ionic impurities from
entering the oxide.
Interface TrappedCharge; QjI, Nit, Di,. Closely related in physical origin
to the fixed oxide charge is the main form of interface trapped charge. Both
chargesarisefrom the formation of partially ionized silicon species during
the thermal oxidation process. The main difference is that Q, may be
charged or discharged as a function of surface potential, while Q, is not in
electrical communication with the silicon and remains charged. Interface
trapped charge does have many of the same process dependencies as Q,
 Thermal Oxidation 59

such as oxidation temperature, silicon orientation, annealing conditions,

etc. One significant difference between the two charges, however, is that
interface traps can be complexed at low temperatures (300”-500°C) with
an active hydrogen species and thus their effective density reduced
significantly. As- oxidized N, densities are normally in the 1 012cm-2 range,
while after a 400°C forming gas anneal their values drop to below 1010cm-2.
Other types of interface trapped charges result from ionizing radiation,
and the presence of heavy metals (Fe, Cu) at the Si-SiO, interface. Both
result in the same kind of charge formation with respect to the silicon band
gap.
Oxide Trapped Charge; Q,,, N,,. The fourth type of oxide charge is due
to the presence or generation of trapped holes or electrons in the oxide.
Generally these are produced by ionizing radiation, avalanched junctions,
high currents through the oxide, or other reactions which either tend to
breakSi- bonds in the oxide or otherwise lead tocarrier trapping on sites
or traps already present in the oxide. 27 Charge trapping, either due to
ionizing radiation or the presence of high fields leading to avalanching,
have been causeforconcern in the past and will be even more of a problem
as device geometries shrink and radiation producing processes are
employed. Some of these, such as sputtering, plasma deposition and
etching, and electron beam/x-ray lithography, result in considerable
electron-hole trapping and these trapped charges often are not easily
removed. It is possible, however, to modify oxidation processes such that
oxide charge trapping is minimized. Several studies have been reported
which indicate process effects on oxide trapping.28*2g
Measurement and Control of Oxide Charges. A number of methods
have been developed for measuring the effective density of charges
associated with thermally oxidized silicon. It is beyond the scope of this
chapter to discuss them all but the reader is referred to reviews by
Nicollian and Brews,’ Bartelink30 and Goetzberger et al.31 These and other
reviews describe measurements particularly of the interface trapped
charge density Ni, and include quasistatic capacitance-voltage analysis,
deep level transient spectroscopy, conductance-voltage analysis, and
others. These methods generally permit measurement of interface trap
charge density as a function of energy across the middle portion of the
silicon band gap.
The high frequency capacitance-voltage (C-V) technique, however, is
the most suitable for on-line measurement and control of charges in
oxidized silicon structures .32133It generally involves a high frequency (1
MHz) capacitance measurement as a function of dc bias across an MOS
capacitor. The latter consists of an evaporated metal field plate (normally
an aluminum dot evaporated through a metal mask) over a 0.1 to 0.2 pm
thermal silicon oxide. The substrate should be medium doped (1015 to
1016cm-3) silicon of the appropriate orientation. Fixed oxide charge N,
mobile ionic charge N,, and oxide trapped charge N,,can all be determined
rapidly using C-V analysis. N, is determined by the expression
60 Semiconductor Materials

where Vrs= flatband voltage

@MS
= metal-semiconductor work function difference
c, = oxide capacitance
q = electronic charge
k, = oxide dielectric constant
% = permittivity of free space
x0 = oxide thickness in micrometers
In the case of N,, a bias-temperature stress test is used to measure total
impurity ion content. N, is determined by the following expression which is
based on Equation 14:

Cl51

where AV is the difference between flatband voltages of C-V plots after

positive and negative stress tests. The conditions for the test are normally
+50 and -25 V/pm at 300°C for 2 minutes. An example of N, and N,
measurement using C-V analysis is presented in Figure 8, where C-V plots
before and after bias-temperature stress tests are shown.

POS. BIAS \ INITIAL

c/co

I I
0
VG

Figure 8: The determination of fixed oxide charge density Qf and mobile ionic
charge density Q, in thermal silicon dioxide using the MOS capacitance-voltage
technique.

Oxide trapped charge density N,, is normally determined following a

procedure similar ts that used for ionic contamination. In the case of N,r,
however, the C-V plots are compared before and after the charge trapping
process and no elevated temperature is employed.
As gate oxides for VLSI MOS devices approach the 2OOA thickness
range, the selection of a proper value of work function difference rJMSin
Equation 14 becomes quite critical. In factjt has been determined that the
effective value of +MS can depend on the processing sequence34 so that
the proper choice of $MS becomes especially difficult.
 Thermal Oxidation 61

4.1.2 Dopant Redistribution. It has been known for many years

thatsilicondopantssegregatepreferentiallyononeortheothersideofthe
Sk30, interface during thermal oxidation. This dopant pile-up ordepletion
at the silicon surface can affect several critical device characteristics,
such as MOS threshold voltage, junction breakdown voltage, and others.
The amount and nature of the dopant segregation depends on several
factors, the most important being the dopant segregation coefficient m (m
= ratio of equilibrium concentration of dopant in the silicon to that in the
oxide), the oxidation rate, and the relative dopant diffusion rates in the
oxide and silicon.35 In general, n-type dopants such as phosphorus pile up
(m>l) and p-type dopants such as boron deplete (m<l). Four possible
redistribution effects are shown in Figure 9.35 Cases A and C represent
normal p-type depletion and n-type pile-up. However, the presence of
hydrogen causes increased boron diffusion in the oxide (case B) and
greater depletion. In case D, increased gallium diffusion in the oxide leads
to depletion, even though m>l for this p-type dopant.

OXIDE SILICON

A. m< 1 0. mc 1
DIFFUSION IN DIFFUSION IN
OXIDE SLOW OXIDE FAST
IBORON) (BORON IN Hz)

C. m >l D. m >l
DIFFUSION IN DIFFUSION IN
OXIDE SLOW OXIDE FAST
~PHOSPflORuS. ARSENIC, (GALLIUM)
ANTIMONY 1

Figure 9: Schematic illustration of the dopant distribution as a function of posi-

tion is the SiOJSi structure indicating the redistribution and segregation of
dopants during silicon thermal oxidation (after Grove et a13’).
62 Semiconductor Materials

Because of the various factors affecting redistribution mentioned

above (segregation coefficient, oxidation rate, dopant diffusion rates),
oxidation variables such as temperature, ambient type, and others will
determine the amount of depletion or pile-up. For instance, steam ambients
and/or loweroxidation temperaturesgenerally result in more redistribution.
Furthermore, oxidation pressures which do not allow equilibrium to be
established also result in modified redistribution profiles. The overall
mechanism of dopant redistribution remains unclear due to its complexity,
and computer techniques will be required to properly model the process.

4.2 Effects of Surface Properties on the Oxidation Reaction

4.2.1 Silicon Orientation. It has been observed for a number of
years that the silicon thermal oxidation process is dependent on the
substratesilicon orientation (see Figures 1 and2), and that thisdependence
is more pronounced at lower temperatures (9OOOC).The effect was first
reported by Ligenza36 and later verified by Pliskin.37 It is now established
that the orientation dependence is reflected primarily through the linear
rate constant and is undoubtedly associated with the Si-SiO, interface
reaction (see Figure 6). While a quantitative mechanism has still not been
established, it is assumed that the effect is based on the bond density or
“availability,” and it is observed that the (111) orientation results in the
fastest interface reaction while(lO0) silicon is the slowest. As the oxidation
temperature decreases and the oxidation process becomes more surface
reaction controlled, the orientation effect thus becomes more pronounced.
An orientation effect related to oxide charge density(Q,and O,,) similar
to that for the interface oxidation reaction has also been observed. The
similarity of these two effects leads to the conclusion that oxide charge
origin (Q,and C&Jis directly related to the oxidation process at the Si-SiO,
interface. A comparison of these two orientation dependent effects is
shown in Table 4.

Table 4: Dependence of Oxidation Linear Rate Constant and

Oxide Fixed Charge Density on Silicon Orientation

DRY 02 1200 (III) 1.12 1.7x10”

(110) 0.90 0.6
(100) 0.56 0.2

WET O2 1200 (Ill) 14.40 4.0

(95% (110) 12.0 1.7
Ii,01
(100) 7.2 1.2
 Thermal Oxidation 63

Aspredictedfromthegeneralrelationship,theparabolicrateconstant
is relatively independent of silicon orientation. However, there is some
indicationthatforlowertemperaturesorthinneroxidesthesiliconsubstrate
may cause some oxide structural effect, which in turn might result in an
orientation dependence of the parabolic rate constant.
4.2.2 Dopant Concentration. It was observed some time ago that
areas of semiconductor devices having surface dopant concentrations
greater than 101gcm-3, i.e. emitter regions in bipolar transistors, exhibit
higher oxidation rates than ajoining lightly doped silicon.37*38 Experiments
indicated that the effect for n-type dopants is more pronounced at lower
temperatures or thinner oxides, while for boron doping, an oxidation
increase is noted to some extent over the entire temperature range. These
results implied that high concentrations of phosphorus affect the oxidation
process primarily through the surface reaction rate constant WA, while for
boron both B and B/A contribute to the increase in oxidation rate.
More recently Ho and co-workers3g investigated in more detail the
effect of phosphorus concentration on the thermal oxidation process.
They have attributed this effect to vacancy generation resulting from high
phosphorus concentrations in silicon. These vacancies provide a driving
force for increased interface reaction ratesand relate to the more recently
proposed atomic model of oxidation to be discussed in a later section of
this chapter. Boron tends to segregate into the oxide and will therefore
tend to affect the parabolic rate constant which is more important at higher
temperatures. As boron concentration increases, however, that at the
silicon surface will also increase and therefore raise the interface oxidation
reaction rate. Typical oxide thickness- time data are shown in Figure 10 for
phosphorus.3g Note that the increase of oxidation rate is more pronounced
at lower temperature (800°C) and for thinner oxides, which reflects the
greater contribution of the linear rate constant B/A under these conditions.

’ ’ “I

OXIDATION TIME (min)

Figure 10: Oxide thickness vs oxidation time for oxidation time for silicon oxi-
dation in dry oxygen at 800” and 1100°C using (111) silicon substrates doped
with phosphorus up to solid solubility (after Ho et a139).
64 Semiconductor Materials

4.2.3 Surface Preparation. Some of the effects mentioned above

relating silicon surface properties to oxidation rate indicate that such
effects are more prevalent at lowertemperatures. Asimilareffect has been
notedforthesurfaceconditionofthesiliconpriortooxidation.Ifthesilicon
surface is not cleaned uniformly it is much more likely that resulting
patches of non-uniform thickness of oxide can be observed at 1000°C or
less as opposed to 1200°C. Likewise, if differences in oxidation rate due to
variations in physical treatments such as polishing, lapping, etc., occur,
they will more likely occur at lower temperatures or in the thinner oxide
regime. This again reflects the fact that surface related effects are associ-
ated with the linear rate constant which is much more oxidation rate
controlling at lower temperatures.
Somewhat related to these effects is the observation made by Schwett-
mann and others that the type of pre-oxidation cleaning treatment can
affect the subsequent oxidation rate. An example of this effect is indicated
in Figure 11, where oxidation thickness-time data are shown for three
different cleaning treatments. MSincethe treatment incorporatingammon-
ium hydroxide results in the slowest oxidation, it is postulated that an
inhibiting nitride layer isformedon thesilicon which retardsthesubsequent
oxidation process. More work is necessary to better understand the
mechanisms involved in these effects, since the use of very thin oxides for
VLSI applications will require more stringent control of thin oxide thickness
and uniformity.

1400 I I I I 1 I I I I

1200-

3 lOOO-

%
$j 800- NH40H : H202: Hz0

z
: 600-
x
fz 400- DRY 02
1OOO’C
(100) si
200- n-TYPE, 2-8&I cm

0 I I I I I I I I I
0 20 40 60 80 100 120 140 160 180 200
OXIDATION TIME (mid

Figure 11: Effect of pre-oxidation cleaning process on oxide growth rate (after
Schwettmann et ala).
 Thermal Oxidation 65

4.3 Effects of Ambients on the Oxidation Reaction

4.3.1 Ambient Type. The data presented in Figures 1 and 2 and in
Table 2 demonstrate the considerable difference in silicon oxidation rates
between dry oxygen and steam ambients. While several physical factors
related to Equation 6 can contribute to such differences, in this case the
primary effect appears to be oxidant soiubiiity in the oxide. The soiubiiity of
water in thermal SiO, is three orders of magnitude greater than that of
oxygen.12 As indicated earlier, investigations are now being conducted to
determine mechanisms of oxidant diffusion through the oxide and other
reactions which occur during silicon thermal oxidation. From a practical
consideration, dry oxygen is more commonly used for preparing thinner,
reproducible oxides, such as MOS gates, while steam is employed for
thicker oxides normally used for isolation outside the active junction area.
Variations in 0, or H,O partial pressures are employed for optimizing
thickness control in certain applications, while small amounts of chlorine
are sometimes added for impurity gettering. Otherwise, no other types of
oxidation ambients have been reported.
4.3.2 ChlorineAdditions. intheeariy1970’sitwasreportedthatthe
addition of a small amount of a chlorine species, either HCI, Cl,, or some
organochioro component, to the oxidation ambient can provide several
beneficial effects with respect to the resulting oxide.41.42 These benefits
include improved oxide charge stability, fewer pinholes, reduced interface
trapped charge density, and betterdevice performance in general. it is now
quite common to add a few percent (l-5%) of a chlorine-containing com-
pound, such as HCI, to oxidation ambients used for both MOS and bipolar
devices. It is also common to “clean” oxidation tubes with oxygen- or
nitrogen-chlorine mixtures prior to oxidation.
it has been determined that acertain amount of chlorine remains in the
oxide after oxidation in a chlorine-containing ambient, and that this chlorine
residing very near the Si-SiO, interface can provide improved passivation.
If too much chlorine is present, however, device properties become degrad-
ed and the oxide may blister and peel off the silicon. in most cases the
oxidation rate increases due to chlorine additions-the greaterthe chlorine
content and the higher the oxidation temperature, the greater the rate
increase.
The mechanism for chlorine oxidation is not completely understood,
but it is believed that the reaction:

202+ 4HCl - 2H20+2C12 Cl63

occurs. it follows that Cl, must be the primary chlorine species incorporated
in the oxide and is driven to the Si-SiO, interface by a field in the oxide
during oxidation. If water is added to the ambient, the above chemical
reaction is driven to the left and less chlorine is incorporated in the oxide.
This is supported by the fact that little chlorine is observed in steam
produced oxides. Figure 12 includes an Auger profile of an 11 OOCchiorine-
66 Semiconductor Materials

containing oxide as well as a plot of chlorine concentration at the Si-SiO,

interface as a function of oxide thickness. 43 The latter demonstrates that
chlorine content in the oxide increases with oxidation time.

50

A. AUGER CHLORINE PROFILE

I 1 I I I I
OO 500 loo0 1500 2000
x.J (11
B. CHLORINE CONCENTRATION VS OXIDE THICKNESS

Figure 12: Auger sputter profile (A) and chlorine concentration vs oxide thick-
ness (6) for thermal oxide prepared in 5% HCl/02 ambient at 1100°C using (100)
silicon (after Rouse et a143).

4.3.3 Nitridation. So-called inert gases, such as nitrogen, argon,

and others have been used for many years to dilute oxygen ambients,
reduce charge densities, promote dopant diffusion, and to provide an
oxygen-free ambient for cooling and pulling wafers. It was determined,
however, that while argon and helium are inert, nitrogen will react at
elevated temperatures with silicon. In fact, Raider found that a silicon-
nitrogen reaction occurs at the Si-SiO, interface even in the presence of
appreciable thicknesses of thermal oxides. 44 In general, however, attempts
to produce silicon nitride films by direct thermal reaction were not success-
ful.
More recently, improved gas purity and techniques have permitted
 Thermal Oxidation 67

reasonably good silicon nitride films to be produced by reacting N, or NH,

directly with silicon at elevated temperatures (lOOO”-13Oo”C), with or
without the use of plasmaexcitation. 45n46These thinfilmsexhibit improved
properties over thermal oxides (increased breakdown, fewer pinholes,
higher dielectric constant) and are in the thickness range, 50-l OOA, which
isrequiredforadvancedVLSl MOSstructures.However,continuingprocess
and reproducibility problems appear to preclude their use in actual devices.
On the otherhand, it has beensubsequentlyreported47 that advantagesof
the silicon nitride might be achieved while still maintaining the superior
interface properties of thermal SiO, by converting the outer portion of the
oxide to nitride using an NH, anneal at temperatures greater than 900°C.
The resulting oxy-nitride structures exhibit greatly improved dielectric
breakdowns, resistance to subsequent oxidation impurity, and dopant
diffusion, and improved integrity-all of which make them much more
suitable for submicrometer MOS device application.46 Auger analysis has
indicated that the actual amount of nitrogen in these nitrided oxide films is
fairly low, most of it concentrated at the outer surface of the oxide or near
the Si-SiO, interface.4e
4.3.4 Oxidant Pressure. High pressure oxidation of silicon was first
employed more than twenty years ago by Ligenzaand SpitzeP in order to
accelerate the oxidation process at lower temperatures. They employed a
stainless steel “bomb” which contained the silicon wafer in a steam
ambient. While devices were passivated by this method, it did not become
widely accepted in the industry. More recently, Panousis and Schneideeg
reported a high pressure oxidation system more suitable for production.
Thissystem allowedcontinuousflow of the pressurized ambient through a
quartz tube and was the basis for today’s commercial systems.50-52These
systems can be used for dry 0, or steam up to 25 atm, and have capacities
of up to 200 four-inch diameter wafers. Other experimental systems,
similar to the closed bombs of Ligenza and Spitzer, employing dry0, up to
750 atm, have been reported,52 but are not used commercially.
As indicated in Fig. 6, the general relationship predicts that both the
parabolic and linear rate constants should be directly proportional propor-
tionaltoambientpressurethroughC*,theequilibriumconcentrationofthe
oxidant in the oxide. Thus, the time required to produce a given oxide
thickness should be inversely proportional to pressure. This will provide
several advantages, especially with regard to today’s small geometry
devices having very shallow junctions. Junction movement during oxidation
as well as dopant redistribution will be minimized. It has also been found
that defect levels are reduced. These improvements are either due to the
shorter times and lower temperatures eployed for the high pressure
oxidation process, or because of the increased oxidation rate.
Recent kinetic studies of silicon oxidation in steam up to 20 atm have
indicated that both the linear and parabolic rate constants are directly
proportional to steam pressure from 800” to 1000% as predicted above.53
For dry O,, however, while the parabolic rate constant has a linear (B a P)
dependence, the linear rate constant falls off with pressure54 (B/A a PO.‘).
Typical thickness-time oxidation data for high pressure steam are shown
in Fig. 13.
 68 Semiconductor Materials

Figure 13: Oxide thickness vs oxidation time for silicon oxidation in pyrogenic
steam (-640 Torr) at 900°C and various pressures (after Razouk et als3). Re-
printed by permission of the publisher, The Electrochemical Society, Inc.

Reduced partial pressures of O2 and H20 in inert carrier gases have

been used for producing thin, controlled oxide films. In general, rate
constants are proportional to oxidant pressures down to about 0.1 atm.
However, as film thicknesses approach 200A, the deviation in oxidation
kinetics mentioned earlier occurs and pressure dependencies are not
clearly understood.

5. OXIDATION MECHANISM

5.1 Atomic Reactions

As indicated in Section 2 above, the thermal oxidation of silicon in
either dry oxygen or steam can be characterized by the general relationship
Eq. 6. However, the actual atomic reactions at the Si-SiO2 interface during
thermal oxidation have not been well understood in the past. More recently
efforts have been made to better characterize these reactions, especially
the mechanisms associated with the rate constant k in Eq. 6. It has been
proposed55,56that at least three individual phenomena occur at the Si-SiO2
interface as oxidation proceeds. These are shown in Fig. 14, and are also
proposed to contribute to other effects observed du ring thermal oxidation.
First, each SiO2 molecule produced occupies considerably more volume
than that of the silicon reacted. Thus, appreciable strain results at the
interface region as is indicated in the upper box of Fig.14. This compressive
 Thermal Oxidation 69

Si+O2--SiO2

02 -DIFFUSION

I
902 I SI
1

Figure 14: Proposed mechanisms occurring at the Si-Si02 interface during sili-
__
con thermal oxidation (after Plummer’“). These figures were originally presented
at the Spring 1981 Meeting of The Electrochemical Society, Inc., held in Minne-
apolis Minnesota.

stress accounts in part for the excellent passivation property of thermal

silicon dioxide, but can also lead to lattice mismatch and other defects, if
some mechanism does not permit the stress to be relieved.
One of the ways of relieving this stress is shown in the lower box of
Figure 14, which is the generation and diffusion away from the interface of
silicon interstitials. Silicon interstitials produced by the oxidation process
have been proposed to cause enhanced diffusion of dopants in the silicon
during thermal oxidation-OED,57 as well as to promote stacking fault
formation-01SF.58*5g It has also been proposed that they contribute to
charges such as Q, or Qi, in the oxide.55.60 For the enhanced dopant
diffusion effect, a relationship relating the oxidation rate and effective
diffusion coefficient has been developed5’ which agrees reasonably well
with experimental data:
dx n
D =D. +X-
eff 1 I dt 1 1173

where Di = the normal diffusion coefficient due to vacancy mechanisms

and K(dx/dt)“= the silicon interstitial contribution. The value of n has been
determined to range from 0.2 to 1.0. An expression for stacking fault
generation and retrogrowth has also been proposed:5g

dt
;if [181

where dl/dt = the growth/retrogrowth rate, K, = the shrinkage rate in the

absence of oxidation, and K,(dx/dt)” = the interstitial contribution to the
70 Semiconductor Materials

growth rate. The best value of n appears to be 0.4. A number of process

variables in addition to oxidation rate dx/dt, such as ambient type, silicon
orientation, HCI presence, and mechanical damage, have been shown to
affect oxidation-enhanced diffusion and stacking fault generation through
the formation of silicon interstitials during oxidation.55
The third reaction or mechanism proposed to occur at the Si-SiO,
interface indicated by the middle portion of Fig. 14, involves the possible
contribution of silicon vacancies to the oxidation reaction. Under normal
conditions(lightlydoped silicon) thevacancyconcentration is reasonably
low and oxidation proceeds, giving rise to the mechanisms already discussed
(strain generation and silicon interstitial effects). However, for heavier
dopant concentrations (C, = 21 0z0cmY3) enough silicon vacancies are
present so as to provide additional free volume which can accommodate
additional interstitials and as a result, the oxidation rate increases. This
mechanism has been discussed and modeled by Hoand Plummer3g which
helps to explain the well-known heavily doped oxidation effect discussed
earlier.
An understanding of the detailed mechanisms of reactions occurring
at the Si-SiO, interface during thermal oxidation, such as those described
above, and the relationship to associated reactions occurring during the
oxidation process, should provide the basis for producing and controlling
the thin oxides required forVLSl circuits. It will also be necessary, however
to understand the details of the diffusion of oxidizing species through the
oxide. Various techniques, such as radioactive exchange,61n62 are being
used for this purpose. Finally, an actual physical “picture” of the oxidized
silicon interface region will be required if all the observed effects and
mechanisms of oxidation are to be explained. The current status of the
clarity of the picture is presented in the next section.

5.2 Structure of the Si-SiO, Interface

Forat least twenty-five years, investigators havespeculated about the
nature and physical structure of the Si-SiO, interface region associated
with thermally oxidized silicon. Most of the earlier speculations were
based on electrical characteristics of the interface and MOS devices. It
was initially believed that the interface region depth was less than 2OOA
but lack of sensitive instrumentation prevented any detailed knowledge
about how much less it might be. It was also believed that some of the oxide
charges which resided in this region were due to disrupted Si-Si or Si-0
bonds or other similar defects. Not much more was known about the Si-
SiO,interface.
In the 1970s and early 1980s the sophistication and resolution of
analytical tools have improved considerably. As a result, and because of
the increased emphasis of complex device structures, many investigations
regarding the structure of the Si-SiO, interface have been carried out.
These have involved Auger spectroscopy, x-ray diffraction, electron miro-
scopy, x-ray photoelectron spectroscopy, Rutherford backscattering,
secondary ion massspectrometry, electron spin resonance, ellipsometry,
photo emission, and numerous others. In addition, theoretical computer
modeling has been used to predict interface properties. The results obtained
 Thermal Oxidation 71

from these various types of analysis have been correlated with those
obtained using improved electrical techniques such as quasistatic C-V,
DLTS, and conductance-voltage measurements. All of these plus actual
device measurements have provided considerable insight into the exact
nature of the Si-SiO, interface. It is not possible here to reference even a
small number of the papers concerning the evaluation of the Si-SiO,
interface; however, some of the more comprehensive reviews on the
subject of surface and interface analysis may be consulted.63-65
The current understanding of the nature of the Si-SiO, interface in
thermallyoxidizedsilicon may be summarizedasfollows. First, it isgenerally
agreed that the transition region between silicon and the bulk oxide is no
more than 1Odor even one or two monolayers. In this region, the composi-
tion changes rapidly from Si to SiO,; and the oxide isapparentlycrystalline
in nature immediately adjacent to the silicon. As a result, the physical,
electrical, and chemical properties of the oxide in this transition region are
markedly different from those of amorphous SiO, and affect the net
properties of oxides up to 200Aor more. There is also a good possibility
that the Si-0 bond angles in the transition region and beyond (up to 50&
are strained, which can also affect oxide properties.
Depending on the oxidation conditions and the silicon orientation, a
limited number of silicon atoms at the silicon surface (as few as one in 1 05)
might not be bonded to oxygen and thus could act as trapping sites (Cl,&
Similarly, some of the silicon atoms on the oxide side of the interface might
be disconnected from adjacent oxygen ions (or certain oxygen atoms
might be missing) and these silicon species could also act as charge or
trapping sites (Cl,). Although these specific defects or trapping sites have
yet to be positively observed, the evidence for their presence is fairly
conclusive as a result of recent investigations.18~1g~66~6gA proposed cross
section structure of the Si-SiO, interface region is presented in Fig. 15,
which includes the possible origin of the four types of oxide charges. This

‘-\
,I-.\ I ’ \
:,
:‘O\ \I
0 ( Na" 0
I I Qf, /’
THERMAL I\ +Nou
S102 -Si - 0 -4, SitO-Si-O-Si-
I I “\I_/’ I I
--LO 0 0 0

I- ”
TRANSITION
I
- ’ -
I
Si - 0 -1
,/I-‘\
Si+ +- 0 -
I
Si-
REQION ‘\’ Qf// I

-L ,

SILICON
-9i - ffi - si - Fji - qi - si - Cfi -

Figure 15: Idealized structure of thermally oxidized silicon interface region

showing possible origins of four types of oxide charge.
72 Semiconductor Materials

concept of the Si-SiO, interface structure is the most likely to date. As more
sophisticatedanalysisequipment isdeveloped, it is reasonable toassume
that a more accurate description of the Si-SiO, interface will emerge.
Under any consideration, this interface will play a most important role in
future semiconductor devices.

6. OTHER OXIDATION PROCESSES

6.1 Assisted Oxidation

It is known that various types of radiation can affect the thermal
oxidation process. The radiation can involve electrons, protons, x-rays,
photons(including laser, UV or IR radiation), gamma rays, ions, microwave,
and various types of plasmas. Generally, the net effect of the radiation is to
increase the rate of oxidation. This can occur by either the activation of the
oxidizing species in the gas phase, whereby both the parabolic and linear
rate constants are increased, or by breaking Si-0 bonds in the oxide which
could cause increased diffusion of the oxidant through the oxide. It is also
possible that the interface reaction might be increased. Radiation processes
may therefore be employed to increase the rate of thermal oxidation at
lower temperatures. An example of the use of plasma to form thermal
oxides of reasonable thickness at very low temperatures is demonstrated
in Figure 16.‘O

2 34ooc

p”:’ ;
,” 160

120

60

40 1

20 I I I I I I I
0 1 2 3 4 5 6 7 0

TIME (hrs)

Figure 16: Oxide thickness vs oxidation time for silicon oxidation in dry oxy-
gen plasma (30 mTorr, 1 kW, 0.5 MHz) (after Ray and Reisman%). Reprinted by
permission of the publisher, The Electrochemical Society, Inc.
 Thermal Oxidation 73

On the other hand, these radiation effects might lead to undesirable

results, such as excess oxide charge formation and non-uniform oxide
growth. In fact the use of many radiation-producing processess in VLSI
device fabrication has been the basis for considerable concern by investi-
gators studying the effects of plasma etching, sputtering, electron beam
and x-ray lithography, and other advanced types of processes.71
Electric fields similar to radiation influence the oxidation mechanism.
Electric fields have been used to both affect the oxidation reaction and to
study its mechanism. It has been known since the original experiment of
Jorgensen6 that an electric field is probably present in the oxidizing
silicon system. Furthermore, the application of an external field on the
structure can accelerate or retard the oxidation reaction. The complete
picture is still not clear, although some of the radiation processes described
above (plasma, ions, etc.) include the effects of an electric field as part of
the means of accelerating oxidation. In addition, the anodization process
has also been reported to be effective in oxidizing silicon and compound
semiconductors at low temperatures.72

6.2 Silicon-Containing Materials

Typically, over the past twenty-five years, the chemical elements used
to fabricate silicon semiconductor devices have consisted of silicon,
oxygen, and aluminum, with added dopants. More recently, silicon-containing
materials such as silicon nitrides and refractory metal silicides have been
employed as device components. As it turns out, these alternate materials
can be thermally oxidized to form SiO, in a manner similar to silicon
oxidation. In fact, the oxide formed is essentially identical to SiO, associated
with silicon.
The mechanisms involved in three different silicon-containing materials
used in devicesare illustrated in Figure 17.The oxidation of polycrystalline
silicon (used for MOS gates and interconnects) most closely resembles
single crystal silicon oxidation, except for the presence of grains and grain
boundaries in the poly-Si (Figure 17A). This tends to make the process
more complex and less controllable. 73.74Nevertheless, thermal oxides are
used successfully to passivate and insulate polycrystalline silicon in
today’s device structures. In the case of silicon nitride (Si,N,) (used to
mask oxidation and impurity ions) the mechanism of conversion to SiO, is
similartothat ofsilicon, but nitrogen produced bythereaction mustdiffuse
out of the oxide (Figure 17B). The kinetics of Si,N, oxidation appears to
follow the general oxidation relationship but the rate is at least an orderof
magnitude less than for silicon. 75n76 The SiO, produced is identical to that
obtained by silicon oxidation.
The refractory metal silicides (WSi,, TaSi,, TiSi,, MoSi,) are currently
used in devices in combination with polycrystalline silicon as interconnects
and MOS gates. An oxidized TaSi,/poly-Si structure is shown in Figure
17C. Thermal oxidation of thesilicideapparently proceeds bythediffusion
of silicon atoms from the underlying poly-Si layer up through the metal
silicide.77-7g Assuming a sufficient supply of substrate silicon, stoichiometric
SiO, is produced over the silicide, the latter not being consumed by the
74 Semiconductor Materials

SiO2
Poly-Si
POLYCRYSTALLINE SILICON
502
Si+O2 --SiO2
Si

SiO2

Si3N4
SILICON NITRIDE
B.
SiO2 Si3N4 + 3 02 --r3 SiO2 + 2 Np

Si
i i

SiO;,
To52

Poly-Si TANTALUM SlLlClDE

SiOp ToSi2 + Si + 02 4 SiO2 +ToSQ

Si

Figure 17: Schematic illustration of thermal oxidation of silicon-containing ma-

terials in which silicon dioxide is reaction product: (A) polycrystalline silkon,
(6) silicon nitride, (C) refractory metal silicide.

reaction. Analysis of the data indicates that the rate determining step is
primarily diffusion of the oxidizing species through the oxide. Values of B,
the parabolic rate constant are almost identical to those obtained for
conventional silicon oxidation, while B/Avalues are much higher.77-7g If no
silicon is present beneath the silicide, the resulting oxides are mixtures of
refractory metal and silicon oxides and are generally not stable or repro-
ducible.
Typical thickness-time data for the thermal oxidation of tantalum
silicide deposited over polycrystalline silicon are shown in Figure 1 8.77
Single crystal silicon oxidation dataare included in thefigurefor comparison.

6.3 Other Semiconductors

One of the reasons that germanium did not become asignificant factor
in semiconductor device technology was that it could not be passivated
through thermal oxidation. Thermal germanium oxides are generally un-
stable and decompose during subsequent high temperature processing.
Alternate approaches, such as anodizing or deposition of silicon oxides,
have been attempted, but the almost ideal passivating properties of
thermally oxidized silicon have helped to make this semiconductor the
main device material over the past twenty-five years.
 Thermal Oxidation 75

1.0 I I I I I I I I

0 (100) Si
0.5 A TaSi2 on Poly-Si

0.1 0.2 0.5 1.0 2 5 10 20 SO 100

OXIDATION TIME. 1 (hr)

Figure 18: Oxide thicknessvsoxidation time for thermal oxidation of TaSi2/poly-

Si structure in dry oxygen at various temperatures (after Razouk et al”).

Compound semiconductors, such as gallium arsenide, indium anti-

monide, gallium phosphide, and others, have also been difficult to passivate
by thermal oxidation. Like germanium, the oxides formed are not generally
stable. Inaddition,thepresenceoftwoormorespeciesinthesemiconductor
causes competing reactions during the oxidation process and leads to
non-uniform films which depend on such factors as composition, orientation
and other variables. Some success has been achieved using anodic
oxidation for passivating some of the compound semiconductors. In addi-
tion, chemical vapordeposited SiO, or Si,N, provide satisfactory diffusion
masks and passivating layers for compound semiconductors used for
devices of various kinds. Because the nature of the interfaces associated
with these passivated structures is so complex, much less is known about
their chemical and electrical properties. Perhaps as more commercial
applications are developed involving compound semiconductors, more
efforts can be devoted to understanding their surface and interface proper-
ties. In certain cases it might even be possible to develop a suitable
thermal oxidation process. Several informative reviews which deal with
thermal and anodic oxidation of compound semiconductors are avail-
able 72,80,81

7. FUTURE TRENDS

Considerably more stringent requirements will be placed on thermal

oxides as silicon integrated circuit feature sizes move from micrometer
76 Semiconductor Materials

intothesubmicrometer region. Continuing devicescaling will requireeven

thinner, more reproducible oxides for gates in MOS structures. This implies
improvements or modifications in several areas. First, oxide thickness will
have to be controlled to even closer dimensions than it is now. Because of
differences in optical and electrical properties of thin thermal oxides,
improved or new thickness measurement techniques will have to be
developed. Equally important will be the need to better understand the
oxidation kinetics in the thin region so that control and reproducibility of
the oxide thickness can be achieved.
It will also be necessary to control and understand the effects of
processvariables on otheroxide propertiessuch aselectrical conductivity
and oxide charge formation. Equally important will be minimization of
defects, pinholes, and the like in these ultrathin films. Control of all these
oxide properties implies a better understanding of the Si-SiO, interface
region. As device dimensions reach a critical minimum size, statistical
variations in individual oxide charge densities may not permit specific bits
of the device to function.
With respect to thicker oxides used in future device structures, pro-
cedures will have to be developed to minimize or even eliminate oxide
encroachment. Up to now, oxides used to isolate the individual devices
have exhibited some form of “birdsbeak.“Since this encroachment can be
of the order of a micrometer, it is obvious that this much “lost” area cannot
be tolerated in submicrometer structures. These oxide isolation problems
are being solved in part by (1) the use of other types of nitride masking
procedures which retard encroachment,82 (2) the fabrication of etched
trenchstructureswhichcan befilled byvarioustypesofdielectricmaterials,83
or(3) selective epitaxial growth of silicon within insulating walls of silicon
oxide.84
The final answer to controlling all the above properties may lie in our
ability to properly model the oxidation process itself and the resulting
effects on the oxide properties, and ultimately, the device parameters.
Since most future devices will involve very complex, three dimensional
configurations, our ability to model multidimensional aspects (two and
three dimensional) of oxide formation must be greatly improved. Such
modeling will of course be based on advanced computer techniques.
The trend for all semiconductor processing of the future includes
lower temperatures and shorter times-required for maintaining the ex-
tremely small structures in VLSI devices. This may be accomplished bythe
use of high pressure and/or plasma-assisted oxidation. More reliable
devices with better performance and tighter specifications have been
produced by the use of chlorine in the oxidation ambient. More of these
types of improved oxidation techniques can be expected in the future.
Finally, although thermal oxides, and silicon semiconductors, have
been the mainstay of device technology for more than twenty-five years, SiO,
will only be used in the future if it continues to satisfy the technological
requirements. For specific applications involving MOS gate structures,
other dielectrics such as thermal silicon nitride are being investigated.
Whether these or other materials replace thermal oxides in certain cases
remains to be seen. Similarly, it is reasonably certain that other semi-
 Thermal Oxidation 77

conductors, e.g. GaAs, GaAIP, etc., will be used for various applications,
including integrated circuits. It is reasonably certain, however, that both
silicon and thermal silicon dioxide will continue to play major roles in
semiconductor technology.

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78 Semiconductor Materials

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 Thermal Oxidation 79

58. S.P. Murarka, Phys. Rev. B 16: 2849-57 (1977).

59. A.M. Lin, R.W. Dutton, D.A Antoniadis and W.A. Tiller,J. Elecfrochem. Sot. 128:
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3
Chemical Vapor Deposition of Silicon
and Its Compounds

Kenneth E. Bean
Texas Instruments Incorporated
Dallas, Texas

INTRODUCTION

The process technology of chemical vapor deposition (CVD) is today

and hasformanyyears been one of the keytechnologies in semiconductor
processing. CVD technology is used throughout the various processing
steps in today’s semiconductor manufacturing, starting with the synthesis
of the elemental silicon through thin epitaxial and polycrystalline silicon
films extending on through the oxidation process, the deposition of dielec-
tricfilmsof nitrides, carbides, and silicidesand metallization films. Tables 1
and 2 list these various CVD technologies categorically in their order of
use in the semiconductor process flow. In Table 3 we list the technology,

Table 1: Chemical Vapor Deposition of Silicon and Its Compounds

. SYNTHESIS
. THIN FILMS
EPITAXY
POLY
. OXIOES
. NITRIDES
. CARBIDES
. SILICIDES
80
 Chemical Vapor Deposition 81

Table 2: CVD Processes and Products

. SILICON SYNTHESIS
Sic4 + Hz
SiHCI3 + Hz
CVDlFLUlD BED
SiH4 + Hz I

. EPITAXIAL SILICON AND POLYSILICON, PROCESSES

H2 + Sic14
Hz + SiHCI3
H2 + SiH2Cl2
H2 + SiH4
Hc + SiH4

l SILICON NITRIDE PROCESSES

SiH4 + NH3 + H2
SiH2Cl2 + NH3 + H2

l SILICON OXIDATION PROCESSES

THERMAL OXIDE --Si + 02 or Hz0 (steam)
lR.D.O...SiHCI3 + 02 + ti2
SILANE OXIDE ..SiH4 + 02

l SILICON CARBIDE PROCESSES

SiClr + C7He OR C3Ha

. BORON NITRIDE PROCESS

B2H6 + NH3 + N2
BCI3 + NH3 + H2

l R.D.O. = Reactor Deposited Oxide

Table 3: Chemical Vapor Deposition for Silicon Device Processing

TfCWNOLOG” PROCESS “SfS

sItIcoY oloxlot soIfALlOf

OR WYORlOf O,fr”slOll OR IkwLAvr MASK
6 OXIOANI 0IfLf(.1RIC‘l,M.
lOI. co,. NZOI tfIOsO”fRCOLI

SILICON CAlSlOf SlllCON nAtlo WfPR RfSISTANT SURIACf.

*110 THfN FILM TRANsoUtf R HfMSRAllf
““DROCARSON PROCfSS CONIROL
fTCHOR POtISnlSG STOP
x RA” ,II”OGRAP”” HA*K

SORON NITRIOt O~SO”~Mf AN0 AMMONIA 011 f USlOU SOURCfS

lS2MS L NH,) I RI” VASR
a2 Semiconductor Materials

the process by which the technology is formed, and the uses of this
technology in silicon manufacturing. In the synthesis of ultra-high purity
elemental silicon for today’s semiconductor manufacturing, we may begin
the process with the hydrogen reduction of an ultra-high purity silicon
halide, such as (SiCI,) or (SiHClJ1-4 by CVD of the elemental silicon, on a
high purity silicon rod such as that shown in (a) of Figure 1. This high
temperature reduction takes place in an all quartz system under very
precisely controlled high purity gas flow conditions. When this CVD reaction
has reached completion we will have obtained a polycrystalline rod similar
to the section shown in (b) of Figure 1. This high purity polycrystalline
silicon material is then broken into small pieces, placed in a high purity
quartz liner or crucible which is then heated to the melting point of silicon,
1420”C.Afterthethermalstabilityofthemoltensiliconpoolisestablished,
a carefully oriented seed, cut from single crystal silicon of the desired
crystal orientation, is dipped into this molten silicon and then slowly
rotated and withdrawn to grow the single crystal of the desired diameter.5
This melt is carefully doped to provide the desired conductivity type and
resistivityfortheslicesorsubstrates. Figure lcshowsthetop,orseedend,
of a single crystal of silicon and Figure 1 d shows a sawed slice from such a
crystal. The standard diameter of the silicon slice used by most silicon
device or integrated circuit manufacturers today is 125 mm plus or minus
25 mm while 200 mm is being developed. After the crystal is grown and
sliced by the use of diamond saws the slices are ground, lapped and
chemically/mechanically (chem/mech) polished to remove all surface
damage introduced by the sawing, lapping and polishing operation.

EPITAXIAL DEPOSITION

Shortly after the invention of the transistor in 1947 it became evident

that methods other than diffusion or the grown junction would become
necessary for the production of abrupt junctions of semiconductors from
germanium and then latersilicon. Theepitaxial process providesa method
of producing these abrupt changes in concentration of doping atoms, or
even in type of conductivity.
Epitaxy is the process of producing a layer of material with exactly
controlled crystallographic, chemical, physical, and electrical parameters.
Thesinglecrystalnucleationofthislayeriscontrolled bythe hostcrystalor
substrate which is of a desired and carefully oriented crystallographic
orientation. It also has the proper conductivity type, and carrierconcentra-
tion to fit the device or circuit design. In silicon epitaxy,6’10 the epitaxial
layer is usually formed by the hydrogen reduction of a highly purified
silicon halide or hydride. Table 4 defines the epitaxial process and lists
some of the characteristics needed for the epitaxial substrate. The epitaxial
film is usuallyacontinuousfilm deposited over a continuous single crystal
substrate as in Figure 2. However it may in some cases be a preferentially
depositedfilmoritmaybedepositedoverapreferentiallydoped(incertain
areas) substrate such as that depicted in Figure 3.
 Chemical
Vapor Deposition
83
Figure 1: Silicon processing: polysynthesis, single crystal, sawed and polished slice (125 mm diameter crystal).
84 Semiconductor Materials

Table 4: Epitaxy

.Epitaxy is the process of producing a layer of material with con

trolled crystallographic, chemical, physical and electrical param.
eters.

.In silicon epitaxy. the layer is usually formed by chemical vapor

phase deposition on a carefully polished and cleaned substrate.

.This substrate also has very exactly controlled crystallographic,

chemical, physical and electrical parameters.

.The sil icon epitaxial layer, or layers, is usually the only active
semiconductor material in the device or circuit.

Epitaxial Film

Substrate

The epitaxial growth process involves the deposition of a thin layer

of material onto the surface of a single crystal slice in such a manner
that the layer has the same crystallographic orientation as the
original crystal and becomes an extension of the substrate. If the
layer materials are the same as the substrate, e.g., Si on Si, it is
known as homoepitaxy, or just plain epitaxy. If they are different,
e.g., Si on sapphire, the combination is termed heteroepitaxy.

During the deposition (growth) of semiconductor layers, the conven-

tional N and P-type impurities can be incorporated into the layer .
The control of their concentration, as well as the layer thickness, to
the necessary tolerances, makes the silicon epitaxial process one of
the most demanding steps in the IC manufacturing process. In fact,
epitaxial processes and technologies are listed in the latest DoD
mil itary critical technology I ist as being of such mil itary importance as
to warrant export controls.
 Chemical Vapor Deposition 85

POLISHING DAMAGE LAYER

SINGLE XTAL SUBSTRATE (111) 3.5” OFF, (100) 0” OFF

OAMAGE LAYER REMOVED

HCI VAPOR ETCH IN SITU

EPITAXIAL FILM OEPOSITEO

Figure 2: Epitaxy.

J OXIDE PATTERN
- POLISHING DAMAGE LAYER
- SINGLE CRYSTAL SUBSTRATE
(111)3.5” OFF, (100) 0’ OFF.

OIFFUSION OR IMPLANT (OUF)

N OR P OOPANT

OXIOE PATTERN REMOVE0

- OAMAGE LAYER REMOVED BY

HCI ETCH IN SITU

EPITAXIAL FILM
OUF
SUBSTRATE

Figure 3: “DUF” epitaxy.

In the early days of silicon epitaxy most of the work or efforts were
aimed towards the deposition of thin films on (1 11)” silicon substrates by
the hydrogen reduction of silicon tetrachloride (SICI,), or the silicon tetra-
bromide (SiBr,). In other attempts silicon tetraiodide (Sil,) was also used.
Table 5 lists the silicon bearing halides and silicon hydrides in the order of
use historically and also in the order of descending energy or temperature
required for the reduction. In production today most people use silicon
dichlorosilane (SiH,CI,). This material readily decomposes at about 1050°C.
Silicon hydride(SiH,) decomposes at an even lowertemperature. However
there are problems in the epitaxial deposition of thick films ,using (SiH,)
dueto thermal decomposition in thevapor phase. When thisoccursabove
the epitaxial substrate particles form in the gas phase which fall on the
substrate resulting in the formation of spurious nucleation sites. It should
also be noted that trichlorosilane(SiHClJ, tribromosilane(SiHBr,), Silane
86 Semiconductor Materials

Table 5: Silicon Epitaxy

l Silicon Source-Halides-Hydride

l SiCL, -Early

SiBr4

Sit4

l SiHC13

SiHBr3

l SiH4

l SiHzClz

l Reduction Source-H2

l Vapor Etching-HCI

l Sic14

l SF6

. Hz0

’ Hz

(SiH,) and dichlorosilane(SiH,Cl,J all may be thermally decomposed. This

is due to the fact that there is a hydrogen atom which is liberated at high
temperatures. However this is not true in the case of the silicon tetrachloride
or the silicon tetrabromide. These two do not thermally decompose, and
therefore must have a reducing agent, such as hydrogen, present to bring
about the reaction.

HCI IN SITU ETCHING

Shortlyafterthebeginningofattemptstodosiliconepitaxyintheearly
1960s it was learned that the substrate was of prime importance and must
be extremely clean and free of defects at the beginning of epitaxial
nucleation.Allattemptstoclean thesubstratepriortoplacing thesubstratein
the epitaxial reactor met with high density defect levels in the epitaxial
material. Due to this problem the in situ HCI chemical vapor etching (CVE)
process was developed in 1963. In this process the substrates were
initially cleaned and then placed in the epitaxial reactor. The final cleanup,
removal of contaminants and crystallographic defects, is then done at
approximately 1150-l 250°C by high temperature in-situ etching, using
HCI as the etchant.‘*-l3 Other etches which have been experimentally
used are listed in Table 5. However, the development of in-situ HCI vapor
etching was a key development in the history of silicon epitaxial technology
and allowed the production of large volume, low defect epitaxial material.
With the development of today’s better cleaning and polishing processes,
 Chemical Vapor Deposition 87

epitaxial layers may in some cases be deposited directly on the substrate

without HCI vapor etching. However, in most cases in-situ HCI vapor
etching is still required and in use throughout the industry.
In Figures 4 and 8 we plot the deposition rate of the halides, and the
hydride as a function of mole percent halide and temperature. In Figure 8
we note that the deposition rate versus temperature is a double energy
curve. In general one wants to operate in the left portion, or in the stable
part, of this curve. This allows larger fluctuations in temperature with
smaller affect on deposition rate. Also, in order to deposit high quality
single crystal epitaxy material with a minimum number of defects one
shouldoperateinthel to2 micronperminuteorlessdepositionraterange
as shown in Figure 4.
Figure 5 is a comparative listing of the processes involved in building
both MOS and Bipolar devices or circuits using epitaxial material. In the
Bipolar process described in Figure 5, the epitaxial film is deposited on a
substrate which has been previously patterned and diffused. This process
allows for the production of very high speed Bipolar devices and/or
circuitry. In the MOS process shown in Figure 5, a p+ substrate is used.
This p+ substrate does not interact as an active component in the MOS
structure but only provides a carrier for the epitaxial film in which all of the

DEPOSITION
12
11

2
1
0 '______---_--_-_t-----\--- \

-1 ” ” ” ” ’ ” ’ “I’
4 2 4 6 9 10 12 14 16 18 20 22 24 26 29 30 32
ETCHING MOLEXSiHALlDE

Figure 4: Deposition and etch rate vs mol % silicon halide. The deposition rate
is also affected by reactor design. Curves A and B are from a vertical reactor.
Curve C is from a multiple slice vertical reactor in which each slice rotates on its
own susceptor. Curve Cl is data from Henry Therur of Bell Labs using a single
slice vertical reactor.
 MOS PROCESS BIPOLAR PROCESS
REGROWN

11 (IDO) I’+ SUBSTRATE

;
L
DRAIN
fiREFLOW
J
1) SELF ALIGNEO.SOURCE-

OXIOE
1
I
!izz= N*
J
OXIDE
/ el BASE DIFFUSIDN
3

bl HCI ETCH & P- EPITAXY

ibS
g) PHOS OXIDE
0 EMITTER DIFFUSION

cl OXIDATION
c) N.EPI GRDWTH

I
0) CONTACT OR

L-
d) ISOLATION DIFFUSION

a
a) ACTIVE AREA DEFINITION
ilW I
hl METALLIZATIDN

(N CHANNEL-SELF ALIGNED GATE)

Figure 5: MOS-bipolar process comparison.

 Chemical Vapor Deposition 89

active components are fabricated. However, the p+ substrate provides a

backside ground plane which eliminates effects due to substrate noise
generated by the charging and discharging of p-n junction capacitance as
well as processgettering action which enhances the characteristics of the
MOS devices built in the epitaxial film. This structure also reduces the
tendency for latchup in CMOS circuits. In today’s CMOS process, many of
the circuitss are built in epitaxial material, which is deposited by CVD
processing. In this CVD epitaxial process, the interface at the substrate p+
material and the epitaxial p- material is of utmost importance. In order to
obtain a perfect interface HCI vapor etching is normally required. This HCI
step is carried out in-situ immediately prior to the epitaxial deposition at a
temperature in the range of 1200°C using approximately2% HCI in hydrogen.
As can be seen in Figure 6, the HCI etch rate increases rapidly to a
temperature of approximately 1100°C. One should operate in the flat
portion of the curve above 1100°C in order to have well controlled etching.
IfthepercentHCIistoohighwithrespecttotemperaturearoughetchfront
will develop. Figure 7 shows the ideal conditions for the useful polishing
effect and the non-ideal non-useful effect. From Figure 7 one can find an

EMISSIVITY UNCORRECTED
0.048 pm
1 t I I
1000 1050 1100 1150 1200 1250
TEMPERATURE. “C

Figure 6: Etch rate (HCI-5% in Hz) vs temperature.

POLISHING

ii60 1180 1200 1220 1240 1260 1280

TEMPERATURE, ‘C

Figure 7: Useful polishing region vs % HCI temperature.

90 Semiconductor Materials

etchrateasafunctionoftemperatureforanyratiodesired.Forexample2%
HCI at approximately 1220°C is an ideal etching condition in order to
remove the impurities and damaged region of the substrate surface prior
to epitaxial deposition. We are now ready to perform theepitaxial deposition.
Silicon bearing halides, or the hydride, may be used in orderto perform our
epitaxial deposition. These materials are shown in Figure 8 with silicon
tetrachloride being the silicon source requiring the highest temperature
for deposition, trichlorosilane (SiHCIJ requiring a medium deposition
temperature and dichlorosilane (SiH,CI,) or the silicon hydride (SiHJ
requiring the lowest temperature for deposition. In the deposition reaction,
the deposition rate increases as a function of temperature. The cross-
hatched bar zone shown in Figure8 delineates the change-over point from
a kinetically controlled reaction to a diffusion controlled reaction. As in the
case of HCI vapor etching, one should operate in the flat portion of the
curve forwell controlled epitaxial deposition. The importance of hydrogen
and chlorine, in the reaction cannot be overlooked. Silicon tetrachloride
decomposes in the presence of hydrogen and thermal energy from the
heated susceptor. This material (SiClJ does not thermally decompose as
does the other halides(SiHCI,) or(SiH,CI,) orthe hydride(SiH,), without the
presence of hydrogen as a reducing agent. The halides and the hydride all
have a hydrogen atom attached to the molecule, while(SiCIJ does not. The
presence of chlorine in the silicon halide is of importance in preferential
deposition.14-l5 The by-product chlorine and/or HCI gives the silicon atom
a vehicle in which it may be transported from one nucleation site to
another, which may be a more desirable crystallographic site. The by-
product of silicon hydride, does not contain chlorine making this material
somewhat lessdesirablefor preferential deposition unless chlorine is also
added to the reaction.14’16 The effect of silicon atomic mobility ortransport
will be discussed in a later section.

"C
1300 1100 900 900 700 600

Figure 8: Silicon bearing source and deposition rate reduction vs temperature.

 Chemical Vapor Deposition 91

GETTERING

Intheeverincreasingpackingdensityfortoday’stechnologiesofVLSl
and ULSI circuitry, silicon epitaxy plays a very important role.‘O MOS
circuits built in epitaxial material are in general superior in performance to
those built in bulk silicon material. In the past two years considerable
interest has been placed on improving the quality of epitaxial material for
MOS devices. One of the recent developments which has improved the
quality of epitaxial material has been the denuding of defects from the
substrate surface area prior to epitaxial deposition. This denuding is
accomplished byathermal processwhich in mostcases,consistsof ahigh
temperature cycle (approximately 1 1OOC), followed by a lower or inter-
mediate temperature cycle (approximately 650°C) then followed by a
high temperature (approximately 1OOPC) thermal cycle. This denuding
process is highly dependent upon the oxygen and/orcarbon concentration
in the original bulk silicon substrate. The initial high temperature cycle
provides sufficient energy to dissolve the oxygen precipitates that are
present and to cause out diffusion of the oxygen from the surface areas of
the substrate. The intermediate thermal cycle provides energy for renuclea-
tion and growth to stability of oxygen precipitates in the center, non out-
diffused, region of theslice.Thefollowing high temperaturecycle provides
energyforthese precipitates to grow and getter oxygen, heavy metals, and
other defects, during device processing, to these precipitate sites. See
Figures 9 and 10.
Figure 9 shows a cross-sectional view of a denuded substrate after
epitaxial deposition. The high bulk defect density is evident as is the
denuded zone just below the epitaxial silicon interface. In this figure there
are defects at the interface between the epitaxial film and the original
substrate. This indicates that no HCI vapor etching was carried out in this
process. It also shows that the original substrate surface acts as a trap to
hold these defects, which may be bulkstackingfaults, oxygen precipitates,
heavy metals, or carbon atoms. Figure 9 is a photograph of a cleaved
silicon slice. No polishing or potting was required prior to the Wright
Jenkinsetchinordertobringoutthedefectsinthedenudedareaaswellas
the epitaxial film. It is also interesting to note that the defects at the
substrate/epitaxy interface do not cause defects in the epitaxial film at a 1:l
ratio. It appears that only approximately one out of 10 defects at the
interface actually cause stacking faults or defects in the epitaxial film.
Another method of slice/wafer processing that improves device per-
formance is that of backside gettering prior to epitaxial deposition. There
are several methods of backside gettering including sandblasting or
abrading of the back surface of the substrate to produce defects or traps,
and oxide or nitride films on the backside surface to produce strain fields.
However the most successful appears to be that of depositing a thin CVD
film, approximately 1 micron thick, of polycrystalline silicon across the
back surface of the epitaxial substrate prior to final polishing of the front
side. The high density of defects produced by the grain boundaries and
dislocations, due to the polycrystalline film, provide avery effectivegetter-
ing mechanism. During device processing heavy metals may be gettered
92 Semiconductor Materials
u”
,m
E
.-
 Chemical Vapor Deposition 93

Figure 10: (a) 90° cleaved cross section, epitaxy on denuded substrate with back-
side-gettering poly Si layer. 198X P.C. 5 minute W.J. etch. (b) (c) Misfit disloca-
tion extrinsic gettering.
94 Semiconductor Materials

all the way from the front surface to the back surface where they are
trapped at these defect (gettering) sites.
Figure 10a shows a cross-section of a cleaved slice which has a
gettering region at the back surface, a denuded zone just above the
backside gettering media, the high density bulk defect area of the slice,
and then at the top surface a denuded zone just below the epitaxial-
substrate interface. Again, a row of defects is noticable at the epi substrate
interface indicating that this substrate had insufficient or no HCI vapor
etching, in situ, prior to the epitaxial deposition. This also shows that one
could build in intrinsic gettering at desired positions immediately below
theactivedeviceregionofthesemiconductorcircuit.Thistypeofgettering
immediately below the active surface area is very effective18and can also
be designed in discretionarily to provide gettering only at the desired
circuit areas. Figure 1Oa is a cleaved cross-sectional view which required
no polishing or potting prior to the Wright-Jenkins etch to delineate the
defect region, thedenudedzone,andtheepitaxiallayeraswellasthe back
side gettering polycrystalline silicon film.
Asmentionedabove,in-situHCIvaporetchingwillremovethedamage
sites and/or surface traps prior to epitaxy. However, one may wish to leave
or form a new damage layer, for low temperature processing intrinsic
gettering,innearproximitytotheactivedeviceregionofthestructure.Ifso,
a film can be deposited between the substrate and the epitaxial film which
is intentionally doped with, for example germanium, to produce a built-in
misfit dislocation strain field. 10.17,18Figure 10B shows a cleaved cross-
sectional view of a single layer misfit dislocation, extrinsic gettering strain
field, and a single layer epitaxial film. Figure 1Oc shows experimental
multiple layers of strain field/epitaxial silicon films with increasing Ge
doping in the strain fields as they were deposited. This increase in Ge
doping causes a noticeable increase in the density of misfit dislocations
within the strain field layers. Wright-Jenkins etch was used to reveal these
damage sites.

SELECTIVE DEPOSITION

It was previously mentioned that silicon atoms, deposited from vapor

phase, have surface mobility and tend to deposit in single crystal form at
preferred nucleation sites. In Figure 1 1 we show a silicon slice which has
both an oxide and an open silicon area exposed. The oxide covers most of
the photographed area with the exposed singlecrystal area only at the top
of the photograph. As a result of preferential epitaxial deposition, the five
silicon octahedral growths, deposited on the oxide are all crystallographic
ally aligned with the substrate orientation. This indicates that the nucleation
was due to pinholes through the oxide and not at nucleation sites on the
oxide. If silicon is allowed to deposit out in freespace, with noconstraints, it
will always form an octahedral shape bounded by eight (111) faces. In
Figure 11,weseetheoctahedralform of thetopfourofthese(1 1l)facets.
Note the alignment of the (11 1‘s) in each octahedron with each other, thus
indicatingthatepitaxialnucleationpropagatesfromthesubstratethrough
Chemical Vapor Deposition 95
96 Semiconductor Materials

the oxide pinhole. Note also in this figure that the surrounding area is
completely free of polycrystalline silicon deposition or nucleation on the
oxide. This indicates that the silicon atoms, above the oxide area, moved to
a preferred site in the open silicon area. We can take advantage of this
atomic mobility for preferential deposition of silicon at desired sites on an
otherwise oxide or nitride covered masksubstrate. Such a mask is shown
in Figure 12. Shown in this figure are five micron diameter circles, on 25
micron centers, opened up through an oxide or a nitride mask on a silicon
substrate. The goal in this experiment is to preferentially deposit epitaxial
silicon in the five micron diameter circles but have no poly silicon nucleate
on the oxide. An epitaxial diode will be formed at the interface of the
original p substrate with the n epi deposit. After the epitaxial growth has
proceeded up through the mask, in this case oxide, lateral spreading
occurs over the oxide to form a large area “epi top” for electron beam
charging. This process provides a very small area p-n junction diode with
very low parasitic capacitance but with a large “epi top” beam collection
area for the production of Vidicon type detectors. In this process the
preferential deposition must be very complete in that single crystal silicon
is nucleated in the open areas. No spurious nucleation of polycrystalline
silicon can be tolerated on the oxide which would bridge across two diode
“epi tops” thus causing a defect in the array. The diode density in this array
is one million diodes per square inch.
Figure 13 is a top view of such an array after preferential deposition.
The (100) structure is clearly evident in the epitaxial “epi tops”. “Epi tops”
deposited on (111) substrates show an equilateral triangle structure
whereas the (100) substrategives the perfect square‘lepi top”orientation.
Figures 14a and 14b show two SEM photographs with 14a being a low
angle SEM of the cross-sectioned substrate/epi structure and 14b being a
near 90 degree cross-section after the oxide had been etched away. In
14a, the original diode area can be seen as well as the mask oxide which
has been brokenawaywiththecleavageoftheslice. Inthecross-sectionat
14b the original diode structure or size can be seen at the substrate
interface. The lateral spreading, in all directions, over the oxide is approxi-
mately equal to the diameter of the original diode, thus a 3X increase in
diameter and >9X increase in area.
Other examples of preferential deposition making use of the atomic
mobility of the silicon atom are shown in Figures 15 through 7 8. Figure 15
shows the preferential epitaxial deposition of silicon in the vertical lines
across the bottom portion of theslice. In thisgrating there are three micron
wide lines of oxide with two micron wide areas of open silicon between
them. Single crystal silicon is nucleated in the open silicon areas and
grows up through the oxide and then spreads laterally as shown in Figure
18. Also shown in Figure 15 in the top portion of the photograph is an area
with continuous oxide mask with polycrystalline silicon nucleated only on
the top half of this oxide area. The lower half of the oxide area is completely
clean and free of spurious nucleation of polycrystalline silicon. The silicon
atoms have enough mobility, to move to preferred sites in the open silicon
area or to deposit out (at super saturation) as polycrystalline silicon over
the oxide. In this experiment, the deposition temperature was 1 150°C and
 Next Page

Chemical
Vapor Deposition
97
Figure 12: Tivicon mask-5µm open circles on 25 µm centers.
Chemical Etching and Slice
Cleanup of Silicon

Kenneth E. Bean
Texas instruments Incorporated
Dallas, Texas

INTRODUCTION

Slice cleaning and wet chemical etching have been key semiconductor
processing technologiessince the beginning ofsemiconductorfabrication in
the late 1940’s and early 1950’s. The demand for cleanliness, control of
purity: and freedom from defects becomes more stringent with each
advance in device and circuit complexity. This chapter discusses wet
chemical etching of silicon from the standpoint of planar etching, orienta-
tion dependent etching (ODE), concentration dependent etching, and
defect delineation etching. It also discusses the etch composition, the
masking materials used for preferential etching, mask alignment, and
applications for the above etching technologies. We will also discuss
silicon slice cleanup procedures and effects thereof. Table 1 summarizes
the subjects to be discussed, in order of discussion.
Planar etch is a solution that etches silicon in all crystallographic
directions at the same rate. A common formulation is made up by mixing
hydrofluoricacid(HF)=8% byvolume,nitricacid(HNO,)=75%,andacetic
acid (C,H,O,) = 17%. At 25°C this solution etches silicon slices(wafers) at
approximately 5 pm per minute, (see Table 2). Orientation dependent
etches (ODE) have been developed which etch much faster in one crystallo-
graphic direction than in another. For example, a solution of potassium
hydroxideandwater(KOH+H,O) inequalparts(50%-50%weight)at80”C
etchessiliconinthe<l lO>direction=700timesfasterthaninthe<l 1 l>

126
 Chemical Etching and Slice Cleanup 127

Table 1: Chemical Etching and Slice Cleanup of Silicon

*WETCHEMICAL ETCHING *EFFECTS IN (100) SILICON

. PLANAR . FOUR FOLD SYMMETRY

. ORIENTATION DEPENDENT . ETCH SOLUTIONS

. CONCENTRATION DEPENDENT l MASK SYMMETRY
. DEFECTDELINEATION . ALIGNMENT
. SLICE CLEANUP”ETCHES” . APPLICATIONS

*EFFECTS IN (110) SILICON *DEFECT DELINEATION

. (lll)TRACE-FLAT SECCO
. ETCH SOLUTIONS . (100) WRIGHT-JENKINS
. ALIGNMENT
1 SCHIMMEL
. APPLICATIONS

SIRTL

. (111) DASH

LEO’S

‘SILICON SLICE CLEANUP

. STANDARD CLEANUPS

. CHOLINE CLEANUPS

Table 2: Chemical Etches and Characteristics for Silicon

ETCHES CHARACTERISTICS COMPOSITION RATE AN0 REMARKS AEF

PLANAR ETCH ETCH UNIFORMITY HF - HNO] - HAc -5 ,,m,hllN AT 25°C

I
=8Y. ==l% ==,I!4 (IN ALL OIRECTIONSI

l-J-10 ETCHES P+ OR N+ SILICON HF HNO] HAc =d,m,Mlk 11001 25’C

2
“STOPS” AT P- OR N- , 3 10
(lOOI OOE ETCHES (lOOI -100X 11111 KOH -NORMAL =I ,m,MlN AT 8O’C. (1001
OIRECTION PROPANOL-H20 “STOPY AT P++ INTERFACE
KOH - 250 gm ETCHES Si]Nd AT t4XiHR 3-5
N PROP - 200 gm SiO2 AT ZOAIMIN
01 “IO - ml ym

(1101 ODE ETCHES [1101 600 X I1111 KOH - ii20 ~0.8 &MlN AT 80°C
5-I
OIRECTION SO 50 VOL. IN 11101 SILICON

ETHYLENEOIAMINE ORtENTATION OEPENOENT ETHYLENEOIAKINE - =I., pm/MlN AT 100% IN 1100).

ANO CONCENTRATIJN PYROCATECHOL -H20 “STOPY ETCHING AT P++ ,NTER.
OEPENOENT EDA - 25%~ FACE. VERY SLOlY EiCHlNC OF 5-B
H20 - 12ocs SiO2 1*3,t,MlNl “NO” ETCH OF
P.C. - 45 ‘il” Al. Au, Ag, Cu. Ni OR Ta.

direction. SeeTable 2 and Figure 28. If we add normal propanol to the KOH
and H,O etch, we can also etch silicon in the <lOO> direction approxi-
mately 100 times faster than in the <l 1 1 > direction, at 80°C. See Table 2
and Figure 10.
If we mix the same mineral acids used in the planar etch solution in the
ratios of one part HF, three parts HNO,, and 10 parts C,H,O,, we have an
etch commonly known as Dash etch, which etches p+ silicon or n+ silicon,
>7X101g carrier concentration, much faster than p- or n- silicon. In
contrast, the KOH-propanol-water etch “stops”(slows down by- 20X) at a
p+ interface. The ethylenediamine (EDA) etch, made up of EDA, pyrocate-
chol and water (see Table 2) is also both orientation dependent and
128 Semiconductor Materials

concentration dependent in etching silicon and has the advantage of

etching silicon dioxide very slowly (3 A/min) at 100°C.
In today’s high densitycircuittechnologythedetection, ordelineation,
of material defects is of great interest and importance. Wet chemical
etching is commonly used to show these defects. In general, these solvents
preferentially etch the damage site due to the strained or damaged crystal
lattice bonding in the defect area. Sirtl, Dash, and Secco etches are
preferred for(1 11) crystal damage evaluation. Wright-Jenkins, Schimmel,
Yang, and Secco etches are used for (100) crystal defect evaluation. (See
Table 4.)
Silicon belongs to the diamond cubic crystal structure, (perhaps the
most desirable crystal structure to work with). Figure 1 is a model which
shows seven of the low indices planes of the diamond cubic structure we
may choose to use in silicon processing. In general, the (11 l), (100) and
(1 10) planes are the predominant planes used in silicon processing today.
However, other planes are also predominant in etching and deposition.
These planes the (331) and the (113) lie in <310> directions. The (221)
and the (1 12) planes, which lie in the <21 O> direction, are also governing
planes in silicon etching and deposition.
Figure 2 shows the three low indices planes commonly used in silicon
processing in a more vivid display. Figure 3 shows the method of deriving
the Miller indicesforthecrystal planes.The(l 1 1) plane,forinstance, isone
unit length out from the apex of lines A, B, and C in the A direction, in the B
direction, and in theC direction.The plane bounded bythe lines connecting A,
B, and C is the (1 1 l), which is the predominant plane in silicon processing.
The atomic packing in this plane is the tightest, or most closely spaced,
packing density available; therefore this plane dominates the etching and
deposition conditions in silicon. It is the most stable plane in the silicon
crystal structure and is the most difficult on which to etch or epitaxially
deposit.

@ (110)

@ (221)

0 (111)

@ (334)

0 (112)

@ (114)

@ (100)

Figure 1: Low indices planes of the diamond cubic crystal structure.

 Chemical Etching and Slice Cleanup 129

Figure 2: The (100) (110) and (111) planes

Figure 4 is a photograph of a crystallographic model of the diamond

cubic structure. In the <l 1 l> direction we see atoms in a very closely
spaced equilateral triangular arrangement. Thisview shows the extremely
high packing density. If we rotate this same crystallographic model 54” to
the right ortotheleft, wearelooking ina<lOO> directionandseethatthe
atoms are arranged in a square array. The atomic packing density in this
direction is slightly less, making it a more open lattice. Therefore, one
would expect that etching in this direction would proceed more rapidly
than into the more highly packed (111) plane. If we rotate from the (100)
plane 45 or 90 degrees, using this same model then we will be looking in a
<l 1 O> direction. The atoms are in a very open lattice structure, which
exhibits the fastest etching and deposition conditions. This open lattice
structure can also be used to advantage for deep ion implantation. Channel-
ingoftheionstakesplaceveryreadilyin thisopen lattice<1 lO> structure.
This plane in silicon can also be used to advantage for radiation hardened
circuitry. A radiation particle must travel further in this direction before
colliding with a silicon atom, thus producing less radiation damage, than in
the <l OO> or <l 1 l> direction. From this figure we can also see that the
highdensityofthe(1 1 l)planeshouldmakeitaverystrongplane.The(l 10)
plane is 90 degree to the (1 11) plane. The plate-like high packing density
structure of the (1 11) planes are held or bonded together by the structure
ofthemoreopen lattice(1 10) planestructure.Therefore,whenwe breakor
cleave a silicon slice, it will cleave along <l 1 O> directions between (1 1 1)
planes, separating or breaking (1 10) bonds.

ORIENTATION DEPENDENT CLEAVING OF SILICON

Figure5 showsa(l OO)anda(l 11)siliconslicethat havebeencleaved

by pressing the center of each with a hard object, such as tweezers or a
ballpoint pen, when the slice is lying on a pad of paper which allows it to
give, thereforecausing itto break. In thecaseofthe(lOO)siliconslicenote
the fourfold symmetry of the (11 1) cleavage planes. Theirtraces intersect
130 Semiconductor Materials
Chemical Etching and Slice Cleanup 131
132 Semiconductor Materials
 Chemical Etching and Slice Cleanup 133

the (100) surface in the pattern shown. These (111) planes intersect the
(100) surface plane at an angel of 54.74 degrees. If we lookat the cleavage
plane or the edge of the cleaved border of the slice we see a crystallo-
graphic plane that is inclined to the surface at this 54.74 degree angle. In
the case of the (111) slice there are three cleavage planes 120 degrees
apart. When they extend all the way across the slice, they break into pie-
shaped segments with 60 degree angles. The (111) cleavage planes
intersect the (1 11) surface of the slice at 70.53 degrees. If one again
cleaves the sections that have already been cleaved, they will continue to
cleave,inthecaseof(lOO)intosquaresorrectangles,andinthecaseofthe
(1 11) into 60 degree triangular shapes. If we cleave a(1 IO) silicon slice it
will cleave 90 degrees to the (110) surface. If we continue to cleave these
sections we will see that they form rhombic shapes as shown in Figure 6.
However, ifwelookattheedgeorthecleavedsurfacewewillseethat inall
casestheyare90degreestothe(l lO)surface.Thesearethe(lll)planes.
In today’s silicon semiconductor processing there is great interest in
MOS-type structures. For this type of structure the (100) slice orientation
is usually used due to the low surface state density at the (100) silicon
surface-silicon dioxide interface.
Figure 7 is a stereographic projection of the standard (001) or (100)
face centered cubic crystal structure. In this projection we are looking
directly at the (100) surface as we would in a (100) silicon slice. Note that
the four (1 11) planes which intersect the( 100) surface are slightly greater
than half way out to the periphery of the projection (slice) in <l lO>
directions. In otherwords, there isa(l 10) planeperpendiculartothe(l00)
plane and tangent to the periphery at this point. The (111) planes are
actually coming into the (100) surface at angles of 54.74 degrees. The
(1 11) planes are also at 90 degree angles to each other. Those planes
designated by the Miller indices at the periphery of the projection are
known as directions. Starting at the bottom, orthe periphery closest tothe
observer, is a (100) plane, indicating that this is a <l OO> direction. Those
Miller indices indicating planes between this (100) plane and the (100)
plane at the center of the projection are lying in this <lOO> direction.
Moving to the right of the bottom center we have a <310> direction.
Moving up along the periphery we find a <210> direction, a <320>
direction, and then the <l 1 O> direction, in which the (11 1) predominant
plane lies. Further examination of this (100) projection shows a four-fold
symmetry in this (100) plane. All four quadrants are exactly alike, and the
(1 1 1) planes are 90 degrees to each other, as are all other families in this
projection. Note also that in this (100) projection are a <31 O> direction to
the right of the <lOO> direction at the bottom of the projection and a
<310> direction to the left of the <l OO> direction at the bottom of the
projection. These same two (310) planes are also to the right and to the left
of the <lOO> direction at the top of the projection. Likewise, they are
above and below the <l OO> direction at the right and at the left of this
projection. This shows there is double four-fold symmetry of <310>
direction planes in the (100) projection. In this double four-fold symmetry
of <310> directions the predominant planes are the (31 1) and the (331).
These planes etch and deposit rapidly in processing. The effect of these
134 Semiconductor Materials
Chemical Etching and Slice Cleanup 135
136 Semiconductor Materials

(331) planes will be noted in future etching experiments as rapidly under-

cutting planes. In some silicon processing, such as the dielectric isolation
process, which is used for radiation hardened devices and for extremely
high-speed and high-voltage switching circuitry, orientation dependent
etching (ODE) is preferred to form the isolation moatsaround each device
or circuit. To produce these isolation moats, the mask is aligned on the
(100) surface parallel and perpendicular to the (110) flat, a shown at the
lower right of Figure 8. If, the mask is aligned over an oxidized silicon slice
parallel and perpendicular to the (1 10) flat, and if the mask has openings
one micron wide etched down to the silicon, through the oxide the ODE
described in Table 2 will etch to a depth of 0.707 microns and then
completely stop etching. This is the depth at which the two (11 1) traces,
aligned with the edge of the maskopening, intersecting the (100) surface,
meet. Due to the very exact crystallographic 54.74 degree angle, we can
accurately predict the depth of the etch as a function of the width of the
mask opening. See Figure 9.
Figure 9 shows the proper alignment of the mask for ODE etching of
the (100) surface. It also shows a cross-sectional drawing depicting the
54.74 degree angle of the (111) plane intersecting the (100) surface.
Figure 10 is a photograph of an actual ODE etched surface. The top
view shows a portion of a 5 X 7 isolation array as used in the processing of
theelectronicprint-head.Thecross-sectionalviewshowstheexactnessof
the crystallographic structure with the etch stopping on the (111) planes.
Early in the development of this process it was observed that undercutting
occurred at convex (outside) corners of the mask area as shown in Figure
11 a. Figure 11 b is an enlarged SEM view of this exact crystallographic
etching with etch faceting and stopping on the (331) planes, as previously
mentioned. By carefully measuring the angle of intersection of these
facetedplaneswiththe(lOO)surfaceandtheanglethesefacetsmakewith
the(1 lO)flat,theseplaneswereidentifiedas(331). InFigure 12andFigure
14, both (331) and (111) planes are shown. In order to compensate for the
undercutting at the corners and to obtain square or right-angle corners, a
mask corner compensation process was developed. By extending the
oxide out over the area that is being undercut, we can compensate for the
fast etching in the <31 O> direction.
Figure13showsthemaskcornercompensationdesignfor(lOO)ODE.
It should be noted that different orientation dependent etches terminate
their etching on different crystallographic planes. These planes may be in
<31 O> directions or in <21 O> directions, depending on whether the KOH-
propanol-water solution or the ethylenediamine pyrocatechol and water
solution is used. See Figure 14. Figure 15 shows a grossly over etched
ODE structure. The etch time was 70 minutes, or time enough to etch 70
microns deep using a mask designed with corner compensation for a 50
micron, or 50 minute etch.
Figure 16 shows the experimentally derived information for adding
corner compensation to the mask to obtain a 90 degree corner as a
function of etched depth. For example, if one wishes to ODE 30 microns
deep, one must extend the corner out approximately 17 microns in orderto
obtain a 90 degree or right angle corner. It was previously stated that when
Chemical Etching and Slice Cleanup 137
138 Semiconductor Materials

PATTERN OPENED IN OXIDE

0.2 MI1 WIDTH, ETCHED 0.14
MILS DEEP, TERMINATES ON
(111) PLANES

Ii101 FLAT

(110)FLAT

SECTION THROUGH WINDOW

AFTER ETCHING

Figure 9: Alignment of mask with (110) flat on (100) Plane.

the traces of the two (1 1 1) sidewall planes meet at the bottom of the etch
moat the orientation dependent etch stops etching. Toverify this statement,
some (100) silicon slices were etched using a mask designed to etch 50
micronsdeepusingthe(l00)ODE.Thismaskalsohascornercompensation
designed to give square or right-angle corners at a depth of 50 microns.
Figure 17a shows a top-focused view of one of these slices, which was
etched for 38 minutes at 80°C. The etch depth is 38 microns. In the left-
hand picture the focus is at the top of the (100) slice. In the right-side of
Figure 17a the focus is at the bottom of the etch moat. Note that the bottom
is flat at the etch front and is a (100) plane, since we have only etched 38
microns deep. Careful measurement of the etch width at the silicon
surface/oxide mask interface shows that the etch moat is 97.5 microns
wide with no measurable undercutting. Also, note that in Figure 17a, at the
lefttopfocusviewthereisaslighttipofsiliconstickingoutatthecornersin
allfourquadrantsoftheetchmoat.Rememberthecornercompensationis
designed for 50 microns etch depth and we have etched only38 microns
deep.Thesliceswerethenplaced backintheODEsolutionandetchedfor
an additional 30 minutes, for a total etch time of 68 minutes. We have now
over-etched by 18 minutes for the corner compensation design. Careful
measurement of the top of the etch moat again show that the etch moat
width at the oxide is 97.5 microns, indicating that there is no undercutting
oretchingafterthetraceofthe(111) planesreachestheedgeoftheoxide
mask. The oxide corner compensation of the mask is clearly visible in both
the top focus and the bottom focus views of Figure 17b. The bottom focus
shows a completely v’d-out etch front with no (100) remaining. To further
prove this statement, the slices were again placed in the ODE solution for
an additional 30 minutes, making a total of 48 minutes over-etching forthe
 Chemical Etching and Slice Cleanup 139

SEM TOP VIEW (100) DI ETCH

SEM CROSSECTIONAL VIEW (100) DI ETCH

Figure 10: Top view and cross-sectional view of ODE etched (100) silicon.
140 Semiconductor Materials
 Chemical Etching and Slice Cleanup 141

Figure 12: Photograph showing identification of (100) ODE etched planes.

 CORNER COMPENSATION IN OXIDE MASK
ON ODE ETCHED CIRCUIT

Figure 13: Corner compensated mask on (1001 ODE etched silicon.

 Chemical Etching and Slice Cleanup 143

Figure 14: Corner faceting due to (100) ODE etching using different etches.
 Next Page

144 Semiconductor Materials

Figure 15: (1001 ODE etched silicon slice.

5
Plasma Processing:
Mechanisms and Applications

W.C. Dautremont-Smith
Richard A. Gottscho
R. J. Schutz
AT & T Bell Labora tories
Murray Hill, New Jersey

1. INTRODUCTION

In this chapterwe discuss the use of plasmas in the microelectronics

industry. There are basically two reasons why plasmas are used: (1) to
achieveanisotropicheterogeneouschemistry;and(2)togrowmaterialsor
etch materials under conditions far from thermodynamic equilibrium.
Anisotropy is required since feature widths have become comparable to
featuredepths.Non-equilibriumconditionsareadvantageousintwoways:
firstly, new materials or phases can be grown which would not be thermo-
dynamically favored in an equilibrium process; and secondly, the dele-
terious effects of high temperatures on devices can be avoided.
The chapter is divided into three main subsections: fundamental
aspects, etching, and deposition. The origin of anisotropy and the non-
equilibrium nature of the plasma will be discussed in the first section and
the resultant advantages to device processing will be described in the
following two sections. Since there have been several recent review
articles,1-16 particularly on plasma etching, we have not made an exhaustive
effort to include everything that has been published in recent years on this
subject.
In the first section on fundamental aspects the material is initially
tutorial but rapidly progresses to a discussion of the results of recent
diagnostic experiments which illustrate how power is dissipated in rf glow

191
192 Semiconductor Materials

discharges and how the form of power dissipation affectssurface chemistry.

Plasma-surface chemistry is then discussed first in terms of chemical
vapor transport and then in terms of the molecular interactions between
reactive adsorbates, surfaces, and products.
The second section dealing with plasma etching is oriented toward
process design. The steps involved in fabricating a planar MOS silicon
transistor are outlined in order to illustrate the variety of ways in which
plasma etching is used in microscopic pattern transfer. Trade-offs between
different reactors, and opposing design constraints, are discussed along
with processes for etching specific materials.
The final section deals with plasma deposition of materials for micro-
electronic applications. The plasma-enhanced chemical vapor deposition
(PECVD) of silicon nitride and silicon oxide is discussed in detail, with
emphasis on recent advances in techniques and property correlations.
Amorphous and microcrystalline silicon deposition is discussed from the
point of view of the parallels and contrasts with silicon nitride deposition.
Comprehensive coverage of this widely studied field hasnot been attempted,
but adequate reference is made to the large number of existing reviews.
Emerging PECVD applications, in epitaxial semiconductor growth (Si, Ge,
GaAs, GaSb), metal deposition, silicide deposition, and the deposition of
non-silicon-based oxides and nitrides, are also covered. Emphasis through-
out the section is on the influence of plasma parameters on the wide range
of accessible film properties, and in particular in indicating those of
relevance in a variety of semiconductor applications. Plasma film growth,
such as oxidation and nitridation, is not discussed.

2. FUNDAMENTALASPECTS

The idea behind this section is to present properties of plasmas and

plasma reactors which are common to all types of processes, be they
etching or deposition. The emphasis is on unifying concepts. Where
appropriate we have drawn upon the literature for specific examples to
illustrateaconcept; more often than not theexamples havecomefrom the
etching literature since etching processes are generally better understood.
In some instances, the subject matter has not been covered completely
and some references may have been omitted for the sake of covering a
wide range of unifying concepts rather than covering one or two areas in
depth. To our colleagues whose work we have not included, we apologize
in advance.
In Sec. 2.1, we discuss some of the fundamental aspects of plasmas
and sheaths, starting with definitions of their properties as they pertain to
plasma processing. Widely used equivalent circuit models of rf plasmas
are discussed in light of recent diagnostic results. The relationship between
the equivalent circuit parameters and processing variables will be empha-
sized. Next, we discuss the plasma-surface interaction. A useful and
general framework for understanding both etching and deposition, chemi-
cal vapor transport (CVT) theory, is reviewed critically in Sec. 2.1. The
salient features of this theory can be summarized in terms of an equivalent
 Plasma Processing 193

circuit for the heterogeneous chemistry. Current thinking and recent

experiments on the microscopic mechanisms at play in both spontaneous
and ion-enhanced etching reactions are also reviewed in this section. In
Sec. 2.3, we review very briefly recent efforts to model various aspects of
plasma chemistry.

2.1 Plasmas and Sheaths

Plasmas mean different things to different people.” Basically, they
consist of a “soup” of ions, electrons, radicals, and stable neutrals, but, the
relative numbers of these species depend on operating conditions. Typical
numbers for and characteristics of the rf discharges used in microelectronic
processing are given in Table 1. The primary reason for using radio
frequencies is to avoid charging effects when dealing with insulating
substrate material (e.g. SiO,): dc discharges cannot be maintained with
insulating electrodes because there is no direct current conduction path.
In addition, we will see that rf glows have physical propertieswhich depend
on the operating frequency and which can be used to advantage in
heterogeneous chemical processing. Pressures employed are such that
collisions between neutral and charged species are important. Power
densities employed are such that charge densities are relatively low,
typically 1O8-10” cm+, which means that collisions between charged
particles or between charged particles and low density radicals can
usually be neglected.
Two distinct zones are common to all plasmas: the plasma body and
the sheaths (Figure 1). The body is defined as a low field region where the
number densities of positive and negative species are approximately
equal. In most discharges, electrons, are the dominant negative charge
carrienand, becausetheelectronsareunbound,theplasmabodyisagood
conductor. Sheaths correspond to electron deficient, poor conducting
regions which exist wherever the plasma encounters an interface (electrode,
wall, etc.). Sheath formation occurs because of the difference in mobility
between electrons and ions, which stems in turn from the non-equilibrium
nature of partially ionized glow discharges (see Table 1): Electrons easily
gain energy from the field and heat up because they do not exchange
energy efficiently with the more massive neutrals with which they collide;
the neutrals and ions, on the other hand, do exchange energy efficiently so
that energy gained from the field is rapidly dissipated and the ion and
neutral temperatures remain close to the wall temperatures.18
The voltage drop between the conducting plasma and electrodes
occurs in the sheath, resulting in a large sheath electric field. This large
field in turn can lead togradients in concentration, temperature, andfluxof
ions and radicals to and from electrode or device surfaces. Ultimately,
these gradients are responsible for the non-equilibrium, or low temperature,
and anisotropic heterogeneous processing desired.
2.1.1 Response Time and Screening Distance. How does the
difference in mobility between electronsand ions result in sheath formation?
Consider the situation when a potential difference is applied across a
194 Semiconductor Materials

Figure 1: Schematic diagram of parallel plate plasma reactor. Reactant A enters

from left and is removed alongwith product Bat right. Positive ions,denoted by +,
traverse the sheaths along the electric field lines, Es, and impact surface S where
the neutral reactions, etching on the bottom electrode and deposition on the top
electrode, are enhanced (courtesy of C.B. Zarowin).

Table 1: Typical RF Plasma Properties

l+CssWf IO-~ to 10 Torr

FMpWiCY 10 kAr to 30 MHz

Charge Density 10s to 10” cm-3

Electron Plasma Frequency 100 to so00 MHZ

IOU Plasma Frequency I to5Ml1z

Debye Length 0.03 to 1.0 mm

Electron Temperature 1 to 5 eV (Time dependent)

Ion and Neutral Temperature = 0.03 ev

E/N (Sheaths) IO* to 10’ Td*

l I Td = lo-” V cm-z
 Plasma Processing 195

plasma. The electrons rapidly drift toward the positive electrode leaving
behind a net positive restoring force, which prohibits further electron
depletion. Asteadystate is achieved when the plasma potential is sufficiently
positive that electron and ion loss rates become equal. The time it takes
electron plasma frequency,17vlg

we = (ne2/tome)lA, (1)

where n is the total charge density, e is the electronic charge, to is the

permittivity of vacuum, and m, is the electron mass. This frequency is
directly related to the restoring force the electron feels when extracted
from the plasma (hence the dependence on the charge density, n). From
table 1 we see that w, is much larger than typical operating frequencies for
the discharges used in plasma processing. Thus, plasma potential adjust-
ment and sheath formation will be virtually instantaneous as far as we are
concerned.
The maximum distance over which charge imbalance can be main-
tained, in the absence of an externally applied force, is the Debye length,17g19

XD = (q,kT,/ne*)” = Fe/w,, (2)

where k is Boltzmann’s constant, T, is the electron temperature, andFe is

the mean electron speed.The screening length is inversely proportional to
O, just like the displacement of a spring is inversely proportional to the
restoring force constant. The Debye length is also proportional to the
random energy, or speed, since this energy must be overcome to achieve
effective shielding. Although the two are related, the Debye screening
length is not to be confused with the sheath thickness, which is generally
an order of magnitude larger. The ralationship is not an obvious one and
dependsonoperatingparameterssuchaspressure,frequency,andpower
density.20-22
2.1.2 Equivalent Circuits. A simple equivalent circuit which is suit-
ableforbothdcandrf plasmasisshown in Figure2a.1g~23-29Both regionsof
the plasma are represented by resistors in parallel with capacitors; diodes
are used in the sheaths to represent the differences in ion and electron
mobilities which result in rectification of the applied voltage (see below).
Many of the operating characteristics of discharges used in microelectronic
processing can be understood in terms of the relative impedances of each
of these components (Figure 3). Consider dc or low frequency discharges,
where the reactive impedance is so large that only the resistive components
need to be considered. As mentioned above, the plasma body impedance
will be governed primarily by electron conductivity,

6, = ne*/m,v, (34

IP
RP = -
%AP)
196 Semiconductor Materials
ct?
k
P
 Plasma Processing 197

IO' \
\
\\ \\
\ \ \\
106 \ \ \ \
1 1P
\ XP’WCP N WCo
- *P
\ ‘\J

IO"

3 104
N

IO3

IO2
JP meve Pp
RP’(T -( -I--
e P nee2 *P

IO' I I I I
10-3 10-2 10-i 1 10 IO2
w/2-rr (MHz)

Figure 3: Plasma impedances vs. frequency. Resistances, Rs and Rp, are deter-
mined by ion and electron conductivities, Ui = 5.5 X lo1 mhos cm-’ and ue =
lo* mhos cm-’ , sheath and plasma thicknesses, Is = 0.25 cm and Ip = 1 .O cm,
respectively, and the electrode area, AS = Ap = 45.6 cm2. The capacitive impe-
dances, XS and Xp, are determined by the thicknesses, areas, and frequency.

wherev, is the electron momentum transfer collision frequency, A, is the

plasma cross sectional area, I, is the plasma length, and R ,, is the plasma
bodyresistance.Thesheath impedancewill begiven bythe ionconductivity,
defined as in Equation (3) except using the ion massand collision frequency
(see Figure 3). Primarily because of the mass difference, the ion conductivity
is roughly an order of magnitude smaller than the electron conductivity;
thus the sheath resistivity will always be greater than the plasma resistivity.
At higher frequencies, the sheath and plasma capacitive impedances
198 Semiconductor Materials

must be considered. The capacitances of the sheaths and plasma can be

simplyestimatedfromtheareaoftheelectrodeandthesheathandplasma
thicknesses, respectively (Figure 3)

From Figure 3, we see for frequencies below 100 MHz, the plasma body
impedance is predominantly resistive. However, the sheath impedance
changes around the ion plasma frequency (oi = 1 MHz), from being pri-
marily resistive at lower frequencies to being primarily reactive at higher
frequencies. In other words, the sheath capacitor becomes a current
shunt.Abovew, the ionscan no longer respond to the instantaneousvalue
of thefield(see below) and sodisplacement instead of conduction current
dominates.
2.1.2.7. Experimental Verification. Recently, experimental diagnostic
techniques have been developed which allow the concentrations of free
radicals and ions as well as electric field amplitudes to be measured in situ
and non-intrusively.21~22~30-47F or a recent review, see Reference 37. These
techniques allow us to see the extent to which theequivalent circuit model
is appropriate.
2.7.2.7.7 Voltage distribution. How does the electric field vary across
the electrode gap? Acc.ording to the equivalent circuit model, we expect
the field to be largest in the sheaths over the frequency range of interest to
plasma processing (seeTable 1 and Figure 3). In situ electric field measure-
ments are consistent with the model. The local field is plotted as a function
of position for rf discharges through BCI, in Figure 5. For the range of
frequencies studied, 50 kHz to 14 MHz, the field is always greatest in the
sheaths.*’
2.7.2.7.2 Diode behavior. How does the local electric field vary with
time in the electrode sheaths? This has been measured by spectrally
resolving laser-inducedfluorescencefrom parity mixed rotational levels of
the BCI radical formed in rf discharges through BC13,21~46~46 The different
parity levels are mixed by the local electric field; the extent of mixing is
dictated by the field strength as well as the excited state dipole moment
and zero-field energy level splitting. 46.48 Parity mixing is detected by
recording the intensities of transitions which would be “forbidden” in the
absence of an electric field and whose line intensity is a direct measure of
the electric field amplitude. The technique is illustrated in Figure4, where
the field has been sampled at two different times during the rf cycle by
firing the laser synchronously with the applied rf.** Note that the change
signals for the “forbidden” and “allowed” lines in Figure 4 are equal and
opposite insign becausethe”forbidden”component has borrowed intensity
from the“allowed” component asa result of the field-induced mixing. Both
measurementsare made one mm from the powered electrodesheath. The
upper trace is obtained at a time when the powered electrode is the
momentary anode (applied voltage a maximum); the“forbidden” line in the
center is weak compared to the “allowed” lines on either side. Thus, the
field is small during this part of the cycle. However, when the laser is fired
 Plasma Processing 199

Q(5) R(4)

ANODE

CATHODE

1 I I
2721 2720 2719

WAVELENGTH 6,

Figure 4: Spectrally resolved laser-induced fluorescence from BCI radicals formed

in a 13.5 MHz discharge through BCIs at 0.3 Torr and 0.13 W cmm3.The upper
trace was obtained by exciting the P(6) transition 1 mm above the powered elec-
trode at a point in the rf cycle when the voltage was a maximum, making the
powered electrode the momentary anode. The lower trace was obtained in a
similar fashion except during the cathodic part of the cycle. Note that the for-
bidden component, Q(5). is strongest during the cathodic cycle when the electric
field is greatest (from Reference 21).
200 Semiconductor Materials

during the cathodic part of the cycle (lower trace), the “forbidden” line is
comparable in amplitude to the “allowed” lines. During this part of the
cycle, the electric field is strong. Thus, the applied field is rectified in the
sheaths. As a result of the difference in electron and ion mobilities the
plasma potential is”tied” to the anode potential. This behavior is accounted
for in the equivalent circuit (Figure 2) by placing diodes in parallel with the
sheath resistors and capacitors.
2.7.2.7.3 Frequency response. As the frequency is varied an interesting
transition is seen to occur in Figure 5. The local field decreases by roughly
a factor of two above 5 MHz. The peak voltage which must be applied
across the plates in order to maintain constant power also decreases by
this amount (Figure 6a). From the equivalent circuit model we see that this
transition corresponds to a change in the sheath impedance from being
predominantly resistive below wit0 predominantlycapacitive above wr The
total impedance decreases above 5 MHz as the sheath capacitive impe-
dance becomes less than the ion resistive impedance (Fisure _ 3). At
constant power the ratio of voltages at high and low frequency is! gicren by,

2
2 4

POSITION (mm)

Figure 5: Preliminary measurements of electric fields in BCls plasma asa function

of position from the powered electrode to the plasma center for three different
frequencies. The laser was fired at a time such that the powered electrode was
the momentary cathode. The vertical scale is accurate to within + 50 V/cm (from
Reference 21). The counter electrode is at 16 mm.
 Plasma Processing 201

(a)
-

0
E I I IIrlrli I I1111111 I I Ilrllll Illll~

3 . PIE
& 6 0 LIF (b)
2
g 5
S

FREQUENCY(HZ)

Figure 6: (a) Peak voltage for discharge through BC13 as a function of frequency
at a pressure of 0.3 Torr and a power density of 0.13W cm3. (b) BCI radical densi-
ties as a function of frequency. PIE refers to plasma-induced emission, i.e. ex-
cited state radicals, while LIF refers to laser-induced fluorescence, i.e. ground
state radicals (from Reference 21).
202 Semiconductor Materials

(5)

which is in very good agreement with the values in Figures 5 and 6a. This
transition is also apparent when one examines the voltage and current
waveforms in Figure 7.21 Not only does the current increase and the
voltage decrease above 5 MHz but the phase shift between the two
increases toward 90” as the capacitive component becomes an important
sheath current shunt.
2.7.2.7.4 Power dissipation. From the above discussions of voltage
distribution and frequency effects we can see how and where power is
dissipated in rf dischargesasafunction offrequency.At lowfrequency, the
sheaths are primarily resistive and the sheath resistance is much greater
than the plasma resistance. Thus, we expect power dissipation to occur
primarily in the sheaths. Ions accelerated by the sheath field can dissipate
their energy in basically two ways. Collisions with neutrals can result in
ionization, excitation, chemical reactions and/or heating; collisions with
electrodes can result in any combination of surface damage, sputtering,
secondary electron emission and/or heating with either implantation or
reflection of the incident ion.
The response of ions to the sheath field and the consequences of this
response at low frequency can be seen very clearly in Figures 8 and 9.*’ In
Figure 8, the density of Cl,+ measured in the sheath by laser-induced
fluorescence is plotted as a function of time. During the positive part of the
cycle when the local field is very small (Figure 4), the ion concentration
builds as a result of both diffusion of ions from the p.lasma into the sheath
and ionization by electron impact. During the negative part of thecycle, the
ion concentration decreases precipitously as a result of the large cathodic
fields (Figure 4) which sweep the ions out of the sheath toward the
electrode. The extraction of high energy ions at low frequency causes
ionization, excitation, and secondary emission of electrons. This can be
seen in Figure 9 where the uv emission intensity from BCI radicals is
recorded as a function of position across the electrode gap at different
timesduringtherfcycle.*‘Whentheionsareextractedduringthecathodic
cycle the emission is brightest because the ions and secondary electrons
collide with neutrals and produce a cascade of ionization, excitation
(Figure 9), and dissociation as they are accelerated across the sheath.
This periodic build-upand high-energy extraction of ions in thesheath
has no dc or high frequency analog. In dc anode sheaths, ions build up to
some steady-state level but are never extracted with high energy. In dc
cathode sheaths, the ion concentration can never build up to a large value
owing to the large, extracting sheath field. While the time-averaged flux
may be similar in the dc and low frequency rf discharges, the pulsed ion
bombardment in the latter may make a difference in heterogeneous
reaction rates. In high frequency(i.e. above or) discharges, the ions respond
only to the average field, which is less than at lower frequencies owing to
the resistive to capacitive transition discussed above. The net result at
 203

0.2 C-

0.1

-0.4

-0.2

0.4

0.2

9 -0.2
AZ
3 -0.4

2 0.4
5
(3 0.2

-0.2

-0.4

0.4

0.2

- 0.2

-0.4

0. 0.5 1.0 1.5 2.0

T IME (UNITS OF 7)

Figure 7: Current and voltage waveforms for discharges through ECIS at several
different frequencies and a pressure of 0.3 Torr and a power density of 0.13 W
cmm3(from Reference 21). One unit of n corresponds to a 1/2u, where v is the rf
frequency in Hz.
204 Semiconductor Materials

I ” i I”’ I’

0 1 2 3 4
TIME ( UNITS OF 7r 1

Figure 8: Clz+ ion density vs. time in the sheath of a 55 kHz discharge through
Cl? at 0.3 Torr and 0.6 W cm3. One unit of 71corresponds to 18.2 psec.

high frequency is that the ions experience a smaller extraction force and
again build up to some steady state concentration.
The response of ions to the instantaneous field and the change in the
amplitude of this field with frequency at constant power affect the energy
with which ions impact electrode or device surfaces. This is evident in the
ion energy distributions measured by Bruce4g as a function of frequency
(Figure 10). At low frequency, the ions are accelerated to the full sheath
potential, which is approximately the full applied potential (see Figure 5)
on every half cycle as they traverse the sheath. To the extent that there is
ionization and energy loss in the sheath, the ion energy distribution will be
skewed toward lower energies. At 40 Pa(0.30 Torr) of Cl, and 100 kHz, the
Cl+ and Cl,+ ion energies on average are significantly less than the full
sheathpotentialbutthemaximumionenergyisapproximatelyequaltothe
full sheath potential (Figure 10). 4g,50At 13.7 MHz, the ion energy distri-
butions are much narrower and the maximum ion energies are much less
than the peak sheath potential.
Because of the transition from resistive to capacitive sheaths above wi,
power dissipation must shift from the sheaths to the plasma. Since the
current is conducted primarily by electrons in the plasma, the dissipation
mechanisms must involve electron-neutral collisions: ionization, disso-
ciation, and excitation. The shift in power dissipation is evident in Figure
11, where the time-averaged concentrations of excited and ground state
BCI radicals are plotted as a function of position across the gap. Three
different frequencies are displayed; the shifts in emission intensity and
radical density are indicative of the shifts in where power is dissipated.
When these profiles are spatially integrated we can learn not only where
but also how power dissipation changes with frequency. As frequency
increases, the total, spatially-integrated densities of both excited and
 Plasma Processing 205

0 4 0 12 16 20
AXIAL POSITION (MM)

Figure 9: Time-resolved BCI emission obtained from a 50 kHz discharge through

BCIS at 0.13 W cm3 (from Reference 21).

ground state radicals also increases (Figure 6b)21f51because power is no

longer dissipated in the form of ion heating of surfaces and neutrals. Since
total power is kept constant, the power dissipated must be converted to
electron processes resulting in an overall increase in radical, ion, and
excited-state production.
The net effect that operating frequency has on a particular etching or
deposition process depends upon the specific surface chemistry. For
example, Bruce52 has found that the etch rate of Si in a Ccl, plasma
increases by more than an order of magnitude as the operating frequency
increases from below to above wi (Figure 12a). The reaction of chlorine
with Si at room temperature without ion bombardment is negligible; the
206 Semiconductor Materials

104
r
n CP, 0.3 Torr
0.6 W/cm2
SS ELECTRODES
cm SPACING

100 200 300 400 500

ENERGY (VOLTS)
Figure 10: Ion energy distributions, dN/dE, vs. frequency for a discharge through
Cl2 (from Reference 49, reprinted with permission of So/id State Technology,
published by Technical Publishing, a company of Dun and Bradstreet).

reaction is ion induced.4s,53-55 Thus, the plasma etching of Si is enhanced

by lowering the operating frequency because of the increase in the ion
energyat lowerfrequency(Figure lO).Ontheotherhand,undercomparable
conditions the Al etch rate decreases by a factor of 4 as the operating
frequency is tuned from below to above wi( Figure 12 b). Al etchesspontan-
eously in a chlorine environment once the native oxide has been re-
moved.4g,54,55Thus, the Al etch rate increases with frequency because of
the increased production of chlorine atoms and molecules as the degree
of Ccl, dissociation increases (Figures 6b and 11) despite the decrease
in the bombarding ion energies.
2.7.2.2 Bias Effects. It is commonly observed that in high frequency
discharges with unequal electrodeareas that a dc biasvoltage will build up
between the two electrodes. There is a general consensus as to the cause
of dc bias but not as to its scaling with discharge parameters and in
particular its scaling with the electrode area ratio. First of all, unless a
blocking capacitor is placed in series with the rf generator input (Figure l),
there will be a dc path to ground and no bias will be observed. The bias
 Plasma Processing 207

I I I I
--- PIE
4

3 -

I
.
C

4 2.5 M HZ

4 0.25 MHZ
b.
3

._
0 4 8 IZ I6

AXIAL POSITION (r-m-n)

Figure 11: XI radical spatial profiles as a function of frequency for a discharge

through BCIs at 0.13 W crnT3 and 0.3 Torr. The arrows indicate the positions of
the parallel plate electrodes. PIE refers to plasma-induced emission (excited states)
and LIF refers to laser-induced fluorescence (ground states) (from Reference21).
208 Semiconductor Materials

o$p~~; , s’
3 0.01 0.1 I 10 100

EXCITATION
FREUUENCY
(MHz)

3- CC!,:Ar/l:l
0.4Torr
75 w
2-
SS ELECTRODES Al
I cmSPACING

l-

I
0.01 0.1 I IO 100
EXCITATION
FREUUENCY
(MHz)

Figure 12: (a) Sietch rate vs.frequency in a discharge through CC14. (b) Al etch
rate vs. frequency in a discharge through Ccl4 (from Reference 52, reprinted by
permission of the publisher, The Electrochemical Society Inc.).

develops with a blocking capacitor when the electrodes have different

areas because the ion current density to both electrodes is approximately
the same.
It should be noted that an insulating substrate can serve as a blocking
capacitor in the development of a dc bias voltage. However, depending on
the polarizability of such an insulating layer, the sheath field may be
reduced. If the insulator is polarizable it can shield the applied field and a
voltage drop will occur across the substrate.
ZarowiP has shown, using the high frequency equivalent circuit
modelin Figure2b,thattheratioofsheathelectricfieldsshould beequalto
the ratio of areas. For equal sheath thicknesses, this implies that the
voltage ratio should also be equal to the inverse area ratio:

VI A2
‘-= -9 (64
V2 4

where Vi is the potential difference between the plasma and electrode i

whose area is Ar This relationship was derived by assuming conservation
of current density and sheath capacitances which are independent of
current density but proportional to electrode area. One might expect this
approximation to work better at higher pressures, where sheath thicknesses
(and thus capacitances) are not very sensitive to voltage and current.*O
 Plasma Processing 209

The‘classical” workon dc bias effects to which most people refer is by

Koenig and Maissel.24 These authors used the Child-Langmuir Iawl to
relate current and voltage to sheath thickness. The sheath capacitance is
assumed to be proportional to electrodeareaand inversely proportional to
sheath thickness (see Equation 4). Furthermore, the plasma resistive
impedance is neglected compared to the sheath capacitive impedance at
high frequency so that the discharge acts like a capacitive voltage divider.
This leads to the following equation:

Vl
-iE
v2

Thisscaling relationshipshould bevalidonlyat low pressures becausethe

Child-Langmuir law applies to collisionless sheaths.17
Experimental testing of these relationships has not been extensive
but the results obtained so far indicate that Equation 6a is generally more
applicable. Coburn and Kay56 measured sheath voltages as a function of
the area ratio by sampling ions through a pinhole in one of the electrodes.
For an Ar discharge at 0.05 Torr, they found the voltage ratio to scale more
according to Equation (6a) than Equation (6b). More recently, Kohler et
al.2g made similar measurements on a 13.56 MHz Ar discharge operating
at 20 mTorr. For a wide range of applied rf and dc voltages, the capacitive
sheath model was found to be adequate in accounting for the measured
sheath voltages. These experiments were done in an unbalanced (i.e.
unequal electrode area) system and no attempt was made to look at the
electrode area dependence.
Insitumeasurementsofsheathfieldsina13.5MHzdischargethrough
BCI, at 0.3 Torr indicate that both the sheath field and thickness change
with dc bias. The cathode field increases and the sheath contracts with
increasing bias. No changes are observed in the anode sheath.57 The net
result is that the dc biasvoltage appears across the cathode sheath only.
Control of dc bias, by changing electrodeareas, rf power, or by using an
externaldcpowersupply,can beusefulincontrollingetchinganddeposition
processes because the sheath voltages determine the energies of ions
impacting device surfaces(for example, see References 27,28,58-60 and
references therein). This point is discussed in further detail below (Sections
3.2 and 4.2.1).
2.7.2.3 Limitations of equivalent circuit models. From the above dis-
cussion, it should be clear that simple equivalent circuits can be useful for
understanding many qualitative aspects of rf plasmas and developing
intuition which can be applied in process design and trouble shooting.
However, it should be equally clear that the equivalent circuit is really only
a point of departure for complete understanding. The impedances plotted
in Figure 3 are very crude estimates and ignore many aspects of the
discharge physics and chemistry. In particular, the neglect of periodic,
time-dependent variations in concentrations, energies, and fields must limit
the validity of the equivalent circuit model as described above. For example,
oneneedonlylookatthevoltageandcurrentwaveformsforalowfrequency
210 Semiconductor Materials

plasma(Figure 7) to see that the simple circuits of Figure 2 are deficient. A

solution would be to consider the resistors and capacitors to have time-
varyingimpedances.Forexample,theoriginofthetime-dependentsheath
resistance can be seen in Figure 8. Once the ion density has been
extracted by the field, the ion conductivity must necessarily decrease.
2.1.3 Feedstock Composition. Much has been written about the
effects of feedstock composition on both gas-phase and surface plasma
chemistry so we will not discuss the matter in great detail here. The reader
is referred to recent review articles and references therein for more detailed
information.4v5*10*16,61
There are basically two types of effects that feedstock
composition can have on the plasma: physical and chemical. Most of the
literature has dealt with chemical effects.
2.1.3.1 Chemical effects. The effects of feedstock composition on
gas-phase chemistry depend upon the degree of dissociation of the
feedstock constituents so that these effects are not independent of other
plasma parameters such as frequency (Section 2.1.2.1.3) power (Section
2.1.5), and residence time (Section 2.1.4). Given that there is some degree
of radical production, then the reactions proceed much like one would
expect from fundamental chemical principles. For example, the addition of
0, to a CF, discharge results in increased production of F atoms and CO
and reduced production of fluorocarbon radicals and molecules.4~62-64~333
For example, the reaction,

0 + CF, + COF, + F (7)

proceeds rapidly and exothermically.
The net result on surface chemistry can be complicated owing to the
different reactivities and stickinq coefficients of various qas-phase species
on various surfaces. For example, when 0, is added to a CF, discharge
used in the Si etch rateb3 (Figure 13). However, as more 0, is added, the
increaseintheSietchrate63(Figure13). However,asmoreO,isadded,the
etch rate goes through a maximum and then declines because oxygen
begins to compete with fluorine for Si adsorption sites.63 A similar effect
has been seen in the etching of GaAs and InP with CCI,F/O, discharges.65
Another effect of halocarbon oxidation is to reduce the extent of polymer
deposition by oxidizing polymer precursors such as the CF, radical. Poly-
merization is a common problem resulting in slower etch rates and surface
contamination.
Other feedstock recipes and the rationale behind their usage for
specific etching and deposition applications are discussed in greater
detail in Sets. 3.4,3.5,4.2.2, and 4.3.
2.7.3.2 Physical effects. The physical effects associated with feed-
stock composition have to do with changes in the electron energy distri-
bution, electron density, ion energy distribution, ion density, and ion
composition. These changes will, of course, affect homogeneous and
heterogeneous plasma chemistry as well: radical production rates can be
strongly dependent upon the electron density and energy distribution;
surface reaction rates can be strongly dependent upon ion energy.
The effects of feedstock composition on the electron energy distri-
 Plasma Processing 211

PERCENT 02

Figure 13: Si etch rate vs. O2 concentration in a CF4/02 discharge (after Refer-
ence 63).

bution can be seen in Figure 14 where the emission intensities from F and
Arare plotted as a function of the 0, feedstock concentration in a CF,/O,/Ar
discharge. As the oxygen concentration increases, the Ar emission intensity
decreasesindicatingthatthenumberofelectronswithenergiesabovethe
7504A line threshold must also decrease. In other words, the electron
energy distribution appears to cool. Note that the F atom emission lines at
7037Aand 6856A, which have similar excitation thresholds, increase with
0, concentration. The overall increase in F atom production by free radical
reactions (see above and Figure 14) more than compensates for the
decrease in excitation efficiency.
Two explanations for the cooling of the electron energy distribution
with the addition of 0, are plausible: (1) the enhanced production of F
atomsand the introduction of oxygen, both species being electronegative
compared to CF, compounds, results in electron cooling by electron
capture processes; or, (2) the lower ionization potential of 0 and 0, relative
to Fand CF,66 results in electron cooling by inelastic ionization of neutral 0
and 0,. Of these two, the second explanation is more viable because
electronegative gases do not attach high energy electrons very effectively
(see Reference 67 and references therein). On the other hand, the intro-
duction of a lower ionization potential gas necessarily reduces the average
electron energy since a lower energy collision channel has been opened.
212 Semiconductor Materials

4 I I
I I I
(a) ’ CF4 + O2
o Ar (7504%) INTENSITY
3 - EXCITATION EFFICIENCY
FOR F ( 7037% 1

.
2

0 F ATOM DENSITY N

0 I I I I I I
0 20 40 60
OXYGEN PERCENTAGE

Figure 14: F and Ar emission vs. 02concentration in a discharge through CF4/02/Ar

(from References 30 and 63, reprinted with permission of the American Institute
of Physics).
 Plasma Processing 213

Theimportanceoffeedstockionizationpotentialsalsoshowsupinthe
dynamics of ion production and loss. 22 For example, small additions of 0
to an Ar discharge cause dramatic changes in the ion composition. 68
Similarly, when Cl, is added to a low frequency discharge through N,, the
ion composition changes drastically. The concentration of Cl, in the
feedstock need be only 10% forthe N,+concentration to drop by an order
of magnitude. The concentration of Cl*+ is virtually the same in this mixed
plasma as it is in a pure Cl, discharge. 22This effect is illustrated in Figure
15, where the time-dependent concentrations of N2+ and Cl,+ are plotted
for various feedstock compositions. The extent of modulation in the ion
concentration waveforms is a measure of theground-state ion lifetime. For
the N,/CI, mixture, the N,+ lifetime is determined by the rate of charge
exchange with Cl222 (Figure 15d). Since the ionization potentials for N,
(15.58 ev) and Cl, (11.48 ev) are so different, the exchange is essentially
irreversible. The charge exchange reaction must proceed rapidly for the
steady-state ion concentration to be so greatly affected by small changes
in feedstock composition. In this particular case, the reaction rate is
probably enhanced by exchange through the excited state of Cl,+,

N; + Cl,+ N, + Cl;(A*t-t) @a)

followed by,

c~;(A*n,) - Cl$(X?-&j + hv.

The excited state reaction (8a) is exothermic by 1.6 eV as opposed to the

ground state reaction which is exothermic by4.1 eV; thus, reaction (8a) is
expected to lead toa resonant en hancement in the exchange rate.Another
reasonwhytheN,+densitydropswhenCI,isaddedtothefeedstockisthe
electron cooling effect mentioned above. Since the electrons can interact
withchlorineatalowerenergy,fewerelectronswill haveachancetoreach
the higher energies necessary for ionization of nitrogen.
An important point to keep in mind, and one which will be emphasized
in Sets. 3 and 4 below, is that the effects of feedstock composition on
discharge properties and chemistry may be totally out of proportion to the
actual feedstock concentrations. Since ion and radical densities can be a
verysmallfraction of the total gasdensity, small concentrations of feedstock
additives, or impurities, may drastically alter these minority concentrations.
Moreover, the role that these minority constituents play in the discharge
chemistry can be substantially out of proportion to their concentration,
particularly when it comes to surface processes.
2.1.4 Pressure, Flow-Rate, and Residence Time. Variation of
pressure and flow-rate is commonly employed in the tailoring of a particular
plasma process to a particular device application. Again, the effects of
these parameters on the discharge can be roughly divided into physical
and chemical effects with the caveat that the two are, strictly speaking,
interrelated.
2.7.4.7 Chemical effects. The key parameter in affecting discharge
chemistry is neither pressure, P, nor flow-rate, @,but rather the residence
 214 Semiconductor Materials

0.5 1.0 1.5 2.0

TIME (UNITS OF r TT)

Figure 15: Time-resolved Nz+and Clz+concentrations measured by laser-induced

fluorescence (from Reference 22).
 Plasma Processing 215

time, which is simply proportional to P/e. This can be seen very clearly in
themassspectrometricdataofTruesdaleetal.6gwhichisreproduced here
as Figure 16.Theystudied the plasmadecomposition of C,F,asafunction
of both pressure and flow-rate and examined the stable products down-
stream from the dischargewith aquadrupole massspectrometer.Thefinal
concentrations of C,F,, CF,, and C,F,vary both with flow-rate at constant
pressure and with pressure at constant flow-rate. When the ratio of pressure
to flow-rate is held constant, however, the final product concentrations
also remain constant (Figure 16).

(cl
-. F = ZOCCIMIN

P/F = 0.04

c2F6
60-
A A ,
a-”
w - __ A A
d 8 m
z
t I
’ ‘CF 4

20

2 .4 6 8 I.0 2 .4 .6 .8 I.(

FLOW, STD, CUMIN PRESS., TORR

5 IO 15 20 25 FLOW
1 ’ ’ ’ ’ ’ CUMIN

Figure 16: Composition of the effluent from a 50 W CzFb discharge; (a) as a

function of flow-rate at constant pressure; (b) as a function of pressure at con-
stant flow-rate; and (c) as a function of pressure and flow-rate at constant resi-
dence time (from Reference 69, courtesy of G. Smolinsky).

The best way to vary residence time, i.e. with minimal effect on other
plasma parameters, is to vary the flow-rate at constant pressure since
variation of pressure can have pronounced effects on the discharge
physicalproperties(see below). What happenstothegas-phasechemistry
when the residence time is varied? If we considerthe rate of decomposition
216 Semiconductor Materials

and radical production to be fixed for a given power density, then it is easy
to see that the less time the feedstock gas spends in the plasma volume,
the less extensive the degree of dissociation. Thus, at high flow-rates, or
short residence times, the radical density will decrease with increasing
flow-rate. At low flow-rates, or long residence times, the extent of dissociation
may reach a limiting value and a dynamic equilibrium will be established
such that the radical concentrations become flow-independent.
Let us consider the effects of flow-rate on heterogeneous chemistry
when the heterogeneous rates are not rate-limiting: i.e. when the surface
reaction probability is large. If the radical products of feedstock decom-
position are the primary surface reactants, then the low flow-rate radical
concentration may be negliblesince the heterogeneous reaction actsas a
radicalsinkandtheoverallreactionratemaybesmall becauseofthesmall
reactant flux to the surface. At high flow rates, the feedstock may be
insufficiently decomposed to provide radicals for the surface reaction and
again the heterogeneous rate may be small.Theoverall dependence of the
surface reaction rate on residence time, or flow-rate, will exhibit a maximum
(Figure 1 7).lgr70 The effect of flow-rate on heterogeneous chemistry when
the reaction is surface rather than reactant-supply rate-limited will be
discussed in Sec. 2.2.1.
2.7.4.2 Physical effects. The situation is very different when one con-
siders the effects of pressure and flow-rate on the physical properties of
the discharge and, in particular, the energy distributions of ions and
electrons. The effects of flow-rate on ion and electron energy distributions
are primarily an indirect consequence of the compositional changes
discussed above. However, pressure affects these distributions directly

I-____ ETCH RATE LIMIT E,

-__-__ _____ --A-- ______ - ________ --_--_-
I

GENERATION RATE LIMITED ETCHING

OVERALL FLOW RATE

DEPENDENCE

FLOW RATE -

Figure 17: Generalized flow-rate dependence of etching rate for the case where
the surface reaction rate is fast and the reactant is generated in fheplasma. Two
limiting cases are obvious: (1) rate is reactant supply limited and (2) rate is re-
actant generation limited (after Reference 70).
 Plasma Processing 217

by affecting collision rates. For example, the energy with which an ion
impactsasurfaceisnotonlydependentuponthesheathfield,rffrequency,
and ion mass but also the rate at which ions collide with neutrals as they
traverse the sheath.1g,56s71,72If the collision mean free path is greaterthan
the sheath thickness, then ions which enter the sheath from the plasma
boundary will be accelerated by the full sheath potential and will impact
the electrode with a narrow but highly energetic velocity distribution.
Alternatively, if the collision mean free path is much smaller than the
sheaththicknessand if theionsloseall theenergygainedfrom thefieldon
each collision, then

Ei = FX,
where Ei is the ion kinetic energy at the electrode and F is the sheath field,
assumed to be constant with position over one mean free path, X The truth
will generally lie somewhere between these two extremes.
Pressurealso affects the electron energy distribution. Manyelectron-
neutral collisions result in the formation of ion-electron pairs. If the electron-
impact ionization mean free path is small compared to the sheath thickness,
this can lead to substantial ionization in the sheath, which in turn will alter
the ion energy distribution at the electrode surface and the sheath
thickness.‘O In general, the overall charge density and plasma impedance
can be expected to change with pressure in a complex fashion. Since the
ion and electron collision mean free paths can be expected to scale
inversely with pressure, Equation 9 suggests that the natural variable with
which charged particle energy distributions and denities can be expected
to scale is neither pressure nor sheath field but rather the ratio F/P. This
has been long appreciated by scientists studying dc glow discharge
physics. As we will see in Sec. 2.1.7, it is also a useful parameter in
designing and understanding heterogeneous plasma-surface interactions.
2.1.5 Power Density. Many things can happen when the applied
power density is varied. Generally, ething rates, radical densities, charge
densities, and sheath fields increase initially and then saturate with in-
creasing power. One reason why saturation occurs may be that the plasma
volume often increases as the power is increased and electrons and ions
acquire greater energy. This expansion may result in the discharge“finding”
other grounds and discontunities can result in measured plasma para-
meters. If the plasma volume can be maintained at a constant volume, e.g. by
mechanical or magnetic73 confinement, then an increase in power corre-
sponds to an increase in power density. This in turn will result in higher
electron energies, sheath potentials, and ion energies.

2.2 Plasma-Surface Chemistry

In order to understand the overall plasma-surface interaction it is
necessaryto understand thetransport propertiesof the system with which
we are dealing as well as the fundamental interactions between reactive
adsorbate, surface, and product. In this section we first address the
transport problem (Sec. 2.2.1) using recent results derived by
Zarowin.28~58~74,75In Sec. 2.2.2, we deal with the microscopic interactions
218 Semiconductor Materials

between reactive adsorbates and surfaces which lead to etching and

deposition.
2.2.1 Chemical Vapor Transport. Plasma processing takes place
at sufficiently high pressures that back reactions can be important. For
example, in an etching reaction, the volatile product may redeposit either
on the surface from which it desorbed, another part of the same wafer from
which it desorbed (e.g. a side wall), or another surface all together(e.g. the
counterelectrode). Forthisreason it is necessarytoconsiderthetheoryof
chemical vapor transport in order to understand the etching and deposition
of thin films in a plasma environment.
As long ago as 1926, the anomalous sputtering of certain materials
was characterized in terms which we now refer to as chemical vapor
transport58s75-77: involatile cathode materials could be transported via
the formation and subsequent decomposition of intermediate volatile
compounds. For example, in the first experiments by GunterschuIze76 As,
Sb, and Bi were transported in a hydrogen discharge via the formation of
the corresponding hydrides. Veprekand Marecek77 showed that thin films
of Ge and Si could be prepared by chemical vapor transport in a hydrogen
plasma. Transport of the elements occured from the cold zone where the
hydrides are formed to the hot zone where they are decomposed. More
recently, Zarowin has expanded these ideas to include the effects of
geometry, flow-rate, and ion bombardment as well assurface temperature.
We will summarize the salient features of histheory below; first, the nature
of chemical vapor transport in the absence of a plasma or ion bombardment
and at zero flow-rate is discussed in terms of an analogy to an electrical
equivalent circuit.58n75 The circuit is useful only in that there are mathe-
matical correspondences between the electrical circuit elements and
elementsof the heterogeneouschemistry, so that analysisof theelectrical
circuit provides “intuition” for the chemical vapor transport processes. In
the following sections, the effects of flow-rate, loading (or geometry), and
ion bombardment are considered in turn.
2.2.7.7 Equivalent circuit: Zero flow. Consider the generic reaction,

a
A+Sol3 (10)
P

where S is the surface material to be transported, either etched, at rate (Y

per unit area, or deposited, at rate p per unit area, A is the reactant which
combines with S to form volatile compound B. The transport of these
species can be neatly summarized in terms of an equivalent electrical
circuit (Figure 18). Transport impedances, which can all be represented in
terms of resistances, correspond to either heterogeneous reactions or
diffusion. Forsimplicity, weconsideronlytwosurfaces, iand i, with reactive
resistances,

01)
 Plasma Processing 219

i
I Bf
.i n
i

i
Bf

PV Ki-Kj
‘Bd
kT [
(Ki +l)(Kj+l)
1

Figure 18: Equivalent circuit for chemical vapor transport. The transport of
products from one surface to another is driven by an effective chemical potential
difference between the surfaces which may result in turn from differences in sur-
face temperature or ion bombardment. The effects of flow-rate are represented
by current generators so that in the absence of an effective chemical potential
difference, etching but not deposition may occur (after Reference 75). See text
for definitions of circuit elements.

where Ci is the area of the ith surface and ai=cri+Pi is the reaction conduc-
tance. Slow reactions correspond to large resistances. The diffusive resis-
tance between the two surfaces is given by,

where h= Ab/vb is a measure of the separation between surfaces.75 Slow

diffusion corresponds to a large resistance. Theeffective chemical potential
difference between surfaces i and j is given by,

pV (K’-Kj)
(13)
‘= kT(K’+l)(l<i+l)’

where KiJ = c$~‘//~~Jis the equilibrium constant at surface i,j. The term
chemical potential difference is used somewhat loosely here. Afinitevalue
for zeta implies that the equilibrium states for the two surfaces will not be
220 Semiconductor Materials

the same (e.g. if they are maintained at different temperatures). Therefore,

there will be a chemical driving force which produces transport of A and B
between the surfaces. In terms of the product current,

04)

where R = R,‘+R/+R, is the total circuit resistance. The reason for repre-
senting the surface reaction rates and diffusion rate as conductivites
should now be apparent. At zero flow the product current, or etching rate, is
limited by how fast etching occurs on one surface, deposition on the other,
and diffusion of reactants and products in between. If the heterogeneous
reaction rate happens to be limited by reactant generation from a homo-
geneous process, the product current will be limited instead by that
process. This can be seen in a formal fashion by supposing there is a
precursor to reactant A in Equation 10. In terms of the CVT equivalent
circuit (Figure 19), this means that there will be an additional resistance in
series with R,. In terms of the heterogeneous rate constant, ur-’ = uAn-’ +
UP ’
-l where up is the sum of the forward and backward rates for the
precursor reaction P +, A.75
It isimportanttonotethattheaboveequationfortheproductcurrentis
valid, within theframeworkof thesimplegenericequation,foranydeparture
from equilibrium. In equilibrium, Ki = Ki, there is no chemical potential
difference and no net transport of A or B from one surface to another. If a
chemical potential difference is maintained between surfaces i and j, for
example by application of a temperature or electrical potential difference
(see below and Reference 58), there will be net transport of A and B from
one surface to another. Whether B is deposited on surface i and etched
from surface j or vice versa depends on the sign of zeta, which in turn
depends not only on any temperature differences between the surfaces
but also on the reaction energetics. This can be seen most clearly by
expressing the equilibrium rate constants in terms of the surface tempera-
tures and the Gibbs reaction free energy, AG:

K’,i = exp[-AG/kTi~i]. 05)

Thus, when AG is positive(endoergic), zeta is positive forTi-Ti>O and the

transport proceeds from the hot to the cold surface. If AG is negative
(exoergic), zeta is negative for Ti-Ti>O and the transport proceeds from
thecold to hot surface. Regardlessof the reaction energetic& thedirection
of transport and the transport rates can be controlled by control of the
differential surface temperature.
2.2.7.2 Now effects. The effects of finite flow rate on the chemical
vaportransportcan besummarized bysimplyaddingcurrentgeneratorsto
the equivalent circuit as shown in Figure 18. For small flow rates, the
current generators provide an additional driving potential,75
 Plasma Processing 221

where~istheflowrateconstant,i.e.thereciprocalofthereactorresidence
time. Now, even in the absence of a chemical potential difference between
surfaces i and j, net transport of A and B can take place. Flow-rate can be
used as a process control variable in a fashion which is beyond the simple
variation of reactant concentrations by variation of residence time (Sec.
2.1.4).

i
SELECTIVITY = iJPDLy/~P,,,OXIDE

l;,lll I,,, I I,,, II ,,I1

50 250 500 750 1000
FLOW OF WI [seem)
Figure 19: (a) Effect of flow-rate on transport rates showing competition be-
tween flow-rate driven currents and chemical potential driven currents (after
Reference 75). The three curves label a,b,c correspond to chemical potential
differences, <, greater than zero, equal to zero, and less than zero, respectively.
(b) Example of effect of flow-rate on selectivity of polysilicon etching over
photoresist and oxide (after Reference 75).

At higherflow rates, the flow current generator becomes nonlinear. By

using Kirchoff’s law, which says that the sum of the currents into any node
must be zero(i.e. conservation of flux), Zarowin derived the complete flow
dependence for the product current:
222 Semiconductor Materials

Iii = s+As
(17)
RT+ ART ’

,,v (ui,j~[Rd+Ri,j(~Rd+2)]
where As = k~
oL1

R’R j
and AR = ~R,(R’+R’+&R’R’+~~)
d

Both the driving potential difference and the reactive impedance are
modified by finite flow. At very large flow rates, the product current becomes
independent of both the chemical potential difference and the flow rate
and is limited only by the reactive resistance,

IB(co) - f&I&. (18)

Providing reactant production is fast, the rate is surface reaction limited.

The complete dependence of I, on flow rate is shown in Figure 19a,
wheretheproduct current normalized toitsvalueat infiniteflow rate, I,,” is
plotted against the reduced flow rate, f = c$R,. It is the flow-rate relative to
the diffusive resistance which determines the overall transport rate. It the
diffusion rate of products and reactants between surfaces is slow, &large,
then the two surfaces behave somewhat independently and smallerflow-
rates are required to reach the high flow-rate limiting transport rate.
As shown in Figure 19a, three situations arise because of the compe-
tition between theflow-ratecurrentgeneratorsandthechemicalpotential
difference between surfaces i and j(Figure 18 and Equation 17). SinceAc2
0 in Equation 17, the flow-rate current generators can either work in
concertwith or in opposition to the chemical potential differencedepending
on the sign of <and which surface is considered. The three curves, a, b, c, in
Figure 19a correspond to chemical potential differences greater than
zero, zero, and less than zero, respectively. Note that for the case when [<
0, the product current at surface i crosses zero at some finite flow rate, f,
This means that below f, deposition occurs while abovef,etching occurs.
At f,, no net transport occurs. If the chemical potential differences for
different substrate materials have different signs, this competition can be
used to great advantage in achieving large etching selectivities. For
example, when etching polysilicon in the presence of photoresist and SiO,,
Zarowin75 reports selectivities of >300:1 (with respect to SiO,) and>50:1
(with respect to photoresist) at f,(Figure 19).This behaviorcan be explained
if the chemical potential difference, with respect to the counter conducting
electrode, is greater than zero for polysilicon but less than zero for
photresist and SiO,. At flow-rates below f,, deposition of Si occurs on the
photoresistandoxide. Since we have already concluded that &si-~resist,oxide>O
this means that the deposition of Si onto resist and oxide must be endoergic
(see discussion after Equation 14 above). This example illustrates how we
must consider chemical vapor transport between not only the two electrode
surfaces but also the different parts of nominally the same surface.
 Plasma Processing 223

2.2.7.3 Loading. A commonly observed phenomenon in plasma pro-

cessing is that of reactor loading orthe dependence of substrate transport
rates on substrate area (for example see Reference 79). Under conditions
where reactant generation is rate-limiting, transport between surfaces is
unimportant, and flow-rate effects are negligible, Mogab*O showed that
loading can result from competition between reactant generation, homo-
geneous (i.e. gas-phase) reactant loss processes, and reactant loss by
surface reaction. He showed that the reciprocal etching rate should be
linearly related to the substrate surface area:

N,pC'I,
Z-B

M (194

where dz’/dt is the film thickness rate of change (i.e. the etching or
deposition rate), r is the gas-phase reactant lifetime, G is the gas-phase
reactantgeneration rate,pisthesubstratedensity,M isthesubstrategram
molecular weight, and N, is Avogadro’s number. The linear relationship ot
Equation 19 has been observed under a wide range of conditions. This
suggests that the assumptions inherent in Mogab’s theory may be too
restrictive.Thechemicalvaportransporttheorydescribedaboveallowsus
to examine loading effects when flow-rate effects cannot be ignored and
when reactant generation is not rate limiting.
Under conditions where the substrate transport rate is not limited by
reactant supply, the relationship between flow-rate, substrate surface
area and the transport rate is contained in Equation 17. At zero flow,

Note that Equation 19b also exhibits a linear relationship between the
reciprocal transport rate and substrate surface area. There is a direct
correspondence between the parameters in Equations 19a and 1 gb:

u.I *--). ,i
(20a)

r .-. y(R; + Rd) (2Oc)

The correspondence between a and u (Equation 20a) arises because

Mogab only considers etching at surface i and assumes deposition on i or
anyothersurface is negligible. When this is not so, Q must be replaced byu,
the sum of the forward and backward reaction rate constants. In Equation
20b, we see that the volume generation rate in Mogab’s theory, G, corre-
sponds to generation by etching of “reactant” at surface j or product
224 Semiconductor Materials

transport current. In the case of zero flow, reactant A and product B are
transported in opposite directions from one surface to the other when the
chemical potential difference, <, is finite so that one surface acts as a
reactant generator for the other surface. Similarly, the reactant loss time
constant, r, corresponds to the sum of the reactive resistance at surface j
and the diffusive resistance (Equation 20~) both of which correspond to
reactant loss mechanisms.The important point is that despite the radically
different assumptions in the two theories, there is a correspondence of
sources and sinks such that the overall functionality remains the same.
Thus, observation of a linear loading effect is not sufficient to determine
the rate-limiting process.
At higher flow-rates, the relationship between reciprocal transport
rate and substrate area is no longer linear (see Equation 17). The loading
effect is predicted to go through a maximum as the flow-rate is varied.75
Thesensitivityofaprocesstothenumberofwaferswilldependontheflow-
rate in a non-linear fashion. Although some of the aspects of this theory
have been verified(e.g. that there isan effect of flow-rate on loading), more
experimental data are needed to assess the range of validity of Equation
17. One difficulty in obtaining such data is the change in discharge
composition which usually occurs when the residence time is changed.
(see Sec. 2.1.4). This could result in a change in the rate-limiting step from
heterogeneous to homogeneous. Another complication may arise when
more than one reactant is important, This effect alone can give rise toa non-
linear loading curve.81 If changes in flow-rate change the relative concen-
trations of these reactants further deviations from the simple theory above
can be expected. To test the range of validity for the CVT equivalent cir-
cuit model, studies of spontaneous reactions, i.e. without a plasma, would
be most appropriate.
2.2.2 Plasma Modified Chemical Vapor Transport. Until now we
have considered chemical vapor transport without considering the effects
of the plasma except to the extent that it modifies reactant concentrations
and diffusion coefficients. The major influence of the plasma, however, is to
modify the heterogeneous reaction rates by ion bombardment of the
surfaces. Although electron enhancement of heterogeneous rates has
been demonstrated82*83, the sheath fields ordinarily are such as to repel
electrons and negative ions from device surfaces (see Sec. 2.1.2). In this
section we will see how this effect can be treated in a formal fashion within
the framework of chemical vapor transport theory.28,58z74,75The following
section (2.2.3) will discuss the kinetic and microscopic origins of the
heterogeneous chemistry and plasma modifications.
In addition to the neutral reaction, Equation 10, we consider a parallel
ion-driven reaction:74t75

S + A+ f e- ++ B+ + e- ++ B
(21)
P+

This reaction is written in a formal fashion for simplicity. The ion need not
correspond to the neutral moiety nor must the product be an ion initially.
Electrons are included in Equation 21 merely to account for surface
 Plasma Processing 225

neutralization of the incident ion as well as production of a neutral product.

In fact, the following discussion is equally valid for energetic neutrals as
well as ions. The key concept in Equation 21 is that there areparallelpaths
forproduction ofthe finalproducts. Each path hasadifferent rateconstant
and activation energy. In terms of the CVT equivalent circuit, the energetic
ion (or atom) components correspond to resistors in parallel with the
neutral (or chemical) reaction resistors (Figure 18). However, this analogy
is of limited utility because the neutral component resistances in the
presence of ion bombardment are generally different from the case where
ion bombardment is absent. It is this change in the neutral component
resistance which is formally responsible for synergistic effects.
From Equation 11, thetotal reaction ratewill begiven bythesum of the
neutral and ionic components. If each rate is of the form74

cx = N*Zexp(-EA/kT) (22a)

,b = NBZexp(-EB/kT) (22b)

cr+ = N*+Zexp(-EA+/kT) (22c)

/3+ = NB+Zexp(--&+/kT) (22d)

the total rates are given by

a, = a[1 + f,exp(U,/kT)] (23a)

Pt = PI1 + fBexp(U&T)]. (23b)

whereZisapreexponentialratefactor,fheisthedegreeofionizationofA,B
and “I@ = EAB - E*+ f3+is the difference between the neutral and ionic
activation energies. ’
Expressing the rate constants in this form allows us to explain a large
number of temperature studies where Arrhenius behavior has been ob-
served (Figure 20). For the case where the back reactions are negligible
and reactant supply is constant,74

+ In [A] + In [1 + fAexp(U&I’)j. (24)

For neutral dominated reactions, f, exp(U,/kT)< < 1 and the slope of 1,~s.
l/T gives the neutral activation energy, E,. For ion-dominated reactions,
f,exp(U,/kT)>>l and the slope gives -E,,. The fact that ion-dominated
reactions give smaller slopes (see Figure 20) indicates that the ionic
activation energy is smaller than the neutral activation energy. This is not
surprising considering that the ions have been accelerated to relatively
high energies by the sheath field. Another way to think of this activation
energy difference is to think in terms of effective temperatures. Because
the ion energy is superthermal, the effective temperature for the ion-
surface interaction is much larger than forthe neutral-surface interaction.
226 Semiconductor Materials

Thus, thesamechange in absolutesurface temperature will correspond to

a much smaller relative change for the ion-surface reaction than for the
neutral surface reaction.
In general, the effect of ion bombardment is to change the surface
reaction energetics.74*75. To see this, it is more convenient to view the

T('C)
300 280 260 240 220
I I I I I I I I

lOO(

g 100
1
Y

2
QL
3
t

10

P(W/cmV E(kcal/mole)
v 0.89 28.4 0
0 0.40 30.6 0
a 0.15 38.8
. 0.62 34.5 ,\ 0
1 0 -
0
I , ,
1.8 1.9 2.0
1ooorT

Figure 20: Arrhenius plots showing effects of temperature and power density
on etch rates of InP and relative In atom emission intensity in an 0.3 Torr dis-
charge through Clz. The emission intensities are proportional to etch rate. Note
the smaller slopes for the higher power densities suggesting that ion-bombard-
ment is reducing the overall activation energy (from Reference 181, courtesy of
V.M. Donnelly).
 Plasma Processing 227

parallel reaction (2 1) as modifying thechemical potential difference, orthe

degree to which the two surfaces differ from the same equilibrium state,
ratherthan simply a parallel reactive resistance. Consider the equilibrium
constants in Equation 13; the difference between Ki and Kj effectively
determines the chemical potential differences which drive the transport
processes. In the presence of parallel ionic reactions,

1+ fAexp(U&T)
IC, = I<
I + f,yxp(U,/kT) I’

When the reaction is in dominated.

- [AG-AU- kTln(fA/fB)
I<, -+ exp w
kT

where K, is the total (i.e. ionic and neutral) equilibrium rate constant, AU =
U, - U,. Thus, the effect of ion bombardment is a modification of the
effective free energy. Alternatively, we can think of the surface temperature
as being modified, T’ = T/(1-(kTInfJf,+AU)/AG]. If AlJ/kT>ln(f,/f& the
effectivetemperaturewill be hotterthantheactualsurface temperature. In
termsof the effective temperature, transport still goesfrom“hot” to”cold”
for endoergic neutral reactions and from “cold” to “hot” for exoergic
reactions. The difference is that “hot” and “cold” depend upon not only
surface temperature but also ion energies,which can be controlled by
frequency, dc bias, and pressure. Thus, we see the complementary nature
of ion-enhanced chemistry and thermally enhanced chemistry. Of course,
they are not the same thing. The product distributions are likely to be very
different since the thermal energy deposition will be statistically distributed
tothevariousdegreesoffreedom buttheionictranslationalenergymaybe
disposed in very specific ways.
2.2.2.7 Anisotropy. Now that weformallyunderstand theeffectsof ion
bombardment on heterogeneous reaction rates we can understand how
anisotropic patterning (see Sec. 3.4.2) is possible. In general we need to
consider transport between not only the two electrode surfaces but
among all surfaces. Specifically, when considering anisotropy, these
surfaces reside on the same electrode but are mutually orthogonal. The
surface which is perpendicular to the electric field lines will experience
more energetic ion bombardment than the surface which is parallel to the
electric field lines as long as the ion transport across the sheath is
anisotropic. This will occur at higher values of F/P (see Sec. 2.1.4 and
Figure 21).
The specific value of F/P which gives a particular anisotropy in the ion
transport directionality will depend upon the gas composition and operating
frequency(see Sec. 2.1). For example, the value of F/P, estimated from the
square root of the rf power density,** required for a given degree of
anisotropy is shown in Figure 21. Fora pure Cl, discharge, where resonant
charge exchange can be very effective in reducing the ion energy aniso-
 Next Page

228 Semiconductor Materials

r;f =200 w p=2T

.A;, /p ,‘(’

f',f :50 w p=o 57

. ,‘
I,.
,
.) ,, , 1,’

Figure 21: Anisotropy as a function of the ratio of the square root of rf power
density to pressure (approximately equal to F/P) for three discharges illustrating
the effect of gas composition on the degreeof anisotropy in the ion energy distribu-
tion (from Reference 28, reprinted by permission of the publisher, The Electro-
chemical Society Inc.) and the value of F/P required for a given anisotropy.
6
Physical Vapor Deposition

John A. Thornton
Department of Materials Science and Coordinated Science Laboratory
University of Illinois
Urbana, Illinois

1. INTRODUCTION

The term physical vapor deposition is used to denote those vacuum

deposition processes such as evaporation and sputtering where the
coating material is passed into avaportransport phase by physical mecha-
nism-i.e., evaporation, sublimation, or ion bombardment. Physical vapor
deposition methods are the most universal of the available means for
depositing thin films and coatings. Metallic, dielectric, and semiconducting
coatings, in some cases with unique properties, can be deposited. Sputtering
is particularly effective for providing controlled deposition of materials
with complex composition. No attempt is made in this chapter to give a
complete discussion of these technologies. The objective is instead to
simply highlight those aspects that are of particular importance in semi-
conductor device fabrication and processing.
The metallization of semiconductor devices constitutes one of the
primary applications of physical vapor deposition. Originally most device
metallization was done using evaporation. The current trend is toward
increased use of sputtering. The reasons are (1) the effectiveness of
sputtering for depositing refractory metals and materials of complex
composition, such as silicides, which are coming into increased use in
device design, and (2) the recent development of sputtering technologies
(magnetron sputtering) that minimize substrate radiation damage and
offer greatly increased production capabilities. In fact, it has been estimated
that about 70% of the 1983 wafer metallization activity involves the use of
magnetron sputtering.

329
330 Semiconductor Materials

Other applications where sputtering plays a prominent role include

magnetic thin films for recording applications, thin film resistors and
capacitors for hybrid interconnect circuits, as well as microcircuit photo-
lithographic mask blanks and transparent conducting electrodes. Sputtering
may also be used todeposit microcircuit insulation layers, although chem-
ical vapor deposition (CVD) or plasma-assisted CVD is a more common
method for these particular coatings.
Physical vapor deposition is also used to deposit thin films for piezo-
electric transducers, photoconductors, waveguides for integrated optics
devices, and luminescent films for display devices. A potentially very large
application is the fabrication of thin film photovoltaic devices for direct
energy conversion.
A rapidly developing new method called molecular beam epitaxy
(MBE) uses evaporation from multiple sources to deposit device quality
semiconductors such as GaAs with precisely controlled doping profiles.
MBE is finding increasing application for microwave and optoelectronic
devices, with the promise of novel future devices which will incorporate
specially synthesized superlattice structures having properties not found
in homogeneous materials.
This chapter is divided into seven sections. Section two reviews some
ofthe importantaspectsofthevacuumenvironmentwhich relatetovacuum
deposition. Section three discusses vacuum evaporation, and Section
four discusses the application of vacuum evaporation to molecular beam
epitaxy. Section five discusses deposition by sputtering. Section six dis-
cusses and the growth and properties of thin films and coatings, with
particular attention to the influence of deposition parameters, such as
concurrent ion bombardment, on coating properties. Considerable atten-
tion is also given to internal stresses because of the importance of these
stresses in the performance and adhesion of device metallization layers.
Finally, Section seven reviews some of the major considerations in the
important application of device metallization.

2. THE VACUUM ENVIRONMENT

The unit of measure for pressure in vacuum systems is the Torr or

Pascal. The Torr (1 Torr= 1 mm Hg) is a carryover from the time when
pressure measurements were made primarily with manometers. Starting
about 1975, most technical publications began changing to the Inter-
national System of Units(SI), where the unit of pressure is the Pascal (Pa).
The Pascal is the MKS unit of pressure: 1 Pa= 1 N/m2=7.5 mTorr (1
mTorr = 0.133 Pa). Most pressure gauges are still calibrated in Torr or
microns ( 1 micron = 1 mTorr). Therefore Torr will be used in this text,
although both Torr and Pa are given in many cases.
Vacuum systems can be classified as high vacuum (1 Om3 to 1Oq6Torr),
veryhighvacuum(10~6to10~QTorr),andultrahighvacuum(below10-QTorr).
Figure 1 shows schematic drawings of several typical pumping configura-
tions.The highvacuum pumpsmay beoftheoildiffusionorturbomolecular
(Figure 1 a), getter(Figure 1 b), orcryogenic(1 c)type. Pumpingsystemsare
 PRESSURE
, INSTRUMENTATION
GAS
INJEC .TION
? CARBON
P

T-t
Ic, VANE PUMP -
VACUUM VACUUM 0
CHAMBER CHAMBER
1
SORPTION
ROUGHING
-29 GATE VALVE GATE VALVE GATE VALVE

tf3b
TRAP

/ I”I “I
DIFFUSION OR
TURBOMOLECULAR
PUrviP

TITANIUM
\ LN2 CRYOPUMP
CRYOPUMP MECHANICAL
PUMP
3!
SUBLIMATION 5-.
SPUTTER
PUMP c)
ION PUMP ”
MECHANICAL
PUMP c <

b CRYOGENIC PUMPED SYSTEM !

;
GETTER PUMPED SYSTEM
fi
DIFFUSION OR TURBOMOLECULAR 02
PUMPED SYSTEM 5
-,
P

Figure 1: Schematic drawings showing vacuum pumping systems of the various types used in deposition technology: (a) dif- w
0
fusion or turbomolecular pump configuration, (b) getter pump configuration, and (c) cryogenic pump configuration.
332 Semiconductor Materials

discussed in References l-4. Our concern here is with the “vacuum state”
that is achieved and its implications on the deposition process.
Consider a cubic vacuum system with sides 1 m in length. The volume
is 1 m3. The internal surface area is 6 m2. An ideal metal surface contains
about 2~10’~ adsorption sites per cm2. When the chamber is exposed to
the atmosphere, an even largerdensityof molecules will become attached
onto the walls because of surface irregularities and multilayer adsorption.
The number of molecules per cubic centimeter in a room temperature gas
is about

n = 3.3x1 016 p particles/cm3 (1)

where p is the pressure in Torr. Thus when pumping is initiated we have the
taskof removing(760 Torr)(3.3xl 016 molecules/cm3-Torr)(l 06cm3) = 2.5x
1025 moleculesfrom thevolumeandat least(2xl 0i5 molecules/cm2)(6xl O4
cm2) = 1.2x1 020 molecules from the walls.
Nowconsiderachamberfiiledtoan initial pressure P,with an idealgas,
which has no interactions with the walls other than reflections. When such
a chamber is evacuated by a pump of constant volumetric efficiency, the
pressure will decrease with time according to the equation.

p(t) = P, exp (-t/r) (2)

wherethetimeconstant,r=V/S,isafunctionofthechambervolume(V)and
pumping speed(S). Suppose that the pumping system for our 1 m3 cham ber
has a speed of 1000 liters/set. Then z = 1 sec. Typical values are in the
range from 0.1 set to a few seconds.5 Thus Equation (2) predicts that the
pressure in our chamber will decrease exponentially once pumping has
commenced, dropping almost an order of magnitude during each 2 set
interval.
Now consider the removal of atmospheric gases from a chamber. The
relationship given by Equation (2) is obeyed, after a few seconds from the
start of evacuation and until a pressure of about 10 Torr is reached, as gas
is removed from thevolume of thechamber. Subsequently, theevacuation
will become rate-limited by outgassing from the chamber walls. Under
these conditions, the pressure will decrease much more slowly, obeying
an equation of the form

p(t) = QWS (3)

where Q(t) is the total outgassing rate from the surfaceswithin the chamber
atthetimet.Theoutgassingrate,Q(t),andthereforethechamberpressure,
decrease as a function of time, because internal diffusion and surface
desorption deplete the reservoirs of stored gas entrapped on thechamber
internal surfaces.
The dwell time of an atom or molecule on a surface under vacuum will
depend on the binding energy between the molecule and the surface, and
on the surface temperature. See Equation 13 in Section 6.1. Physisorbed
gases with binding energies of the order of 0.1 to 0.5 eV desorb quickly
 Physical Vapor Deposition 333

during the initial pump-down and do not contribute to Equation 3. At the

other extreme, chemisorbed gases with binding energies of 1.5 to3 eV are
released at very small rates, which are persistent but do not contribute
significantly to the gas load. The troublesome gases are those which
produce significant outgassing on the same time scale that is used in
executing the deposition processes. These gases have desorption energies
of about 1 eV. The most notable example is water. In some cases water may
condense on vacuum surfaces to thicknessesof hundreds of monolayers.
Figure 2 shows the specific outgassing rates (primarily water vapor)
for several engineering materials6 The specific outgassing rates typically
obey an equation of the form q = q&/t)“, where n varies from about 0.5 for
elastimers and plastics to about 0.3 to 1 for metals.’ Thus the total
outgassing rate can be expressed as

Q(t) = A q,, (tdt)” , (4)

whereAisthechambersurfacearea.Thetimet,isareferencepointwhere
q = q,. For approximate calculations t, can be taken as the point at which
the high vacuum valve is opened.
Consider the case of our 1 m3 chamber after three hours of pumping.
Assume that the chamber is constructed of stainless steel and that the
high vacuum pump has a speed of 600 liters/set. The specific outgassing
rate for stainless steel after 180 min. of pumping is seen in Figure 2 to be
about 4x1 O-*Torr-liters/set-cm”. From Equation 3 we estimate the chamber
pressure to be (4 X 10W8Torr-liters/set-cm2)(6 X 1O4 cm2)(600/liters/sec)
or 4 X 1 0e6Torr.
In practical deposition systems unwanted gases are a result of desorp-
tion from the deposition sources, substrates, and hot filaments as well as
the chamberwalls. Back-streaming gases from the pumps alsocontribute
contamination species. After prolonged pumping, the residual gases are
typically H,O, CO, CO,, 0, and N,.’ For a residual gas pressure p (given in
Torr), the impingement rate on a substrate surface is

R = 3.51 X 1022 p(mT)-112 molecules/cm2-set (5)

where M is the molecularweight in grams and T is the temperature in OK.It

is useful to keep in mind that at a residual gas pressure of 10.6Torrtheflux
of gas incident on a(substrate) surface within the chambercorrespondsto
the flux associated with a deposition rate of about 1 A/set for a material of
typical density.
The achievement of vacuums less than about 10.’ Torr in room tem-
perature systems generally requires prohibitively long pumping times.
Therefore, baking of the walls is used for ultra high vacuum systems.
Because of the temperature dependence of the adsorbed atom binding
(see Equation 13) this procedure is extremely effective. Thus the number
of molecules pumped from a system at 200°C in one second can equal the
number that would be pumped in a whole day at 20”C5 It is important to
note that the entire system must be heated at one time, because many of
the liberated molecules in a partially heatedsystem will recondenseon the
334 Semiconductor Materials

\
\
\
\\
\
\
1o-9 7 \
\

Figure 2: Specific outgassing rate as function of time for various materials. From
Reference 6.

cooler surfaces, from which they can provide a continued source of

impurity gases.
The required pumping timewill depend on the application. Deposition
processes are often started when the chamber pressure has reached an
empirically determined value. High pumping speeds are often equated
with cleanliness becauseof the relationshipexpressed byEquation3.This
is not necessarily correct4 Two extremes are illustrated in Figure 3. In the
caseshown in Figure3a, the“coatingapparatus”fills muchofthechamber
and the deposition area is large. The gettering capacity of the coating flux,
 OUTGASSING SoURCE OUTGASSING
I COATING
FLUX FLUX
I FLUX
!

SUBSTRATES SUBSTRATES
/

COATING
FLUX

Pe
RESIDUAL

r-1
I _ \ GAS PRESSURE
SOURCE
1
VACUUM PUMPS PUMPS
CHAMBER ?
VACUUM Y
cn.
CHAMBER
c
5
B
TOTAL OUTGASSING FLUX Kp/ m
IMPURITY LEVEL - IMPURITY LEVEL - ;;
TOTAL COATING FLUX TOTAL COATING FLUX
8
8.
Z
a b 2
Figure 3: Schematic illustration showing influence of apparatus geometry on the way in which wall outgassing affects the coating
impurity level.
336 Semiconductor Materials

Q,, is large compared to the capacity of the physical pumping system. In

such systems the purity of the deposit will be roughly proportional toQ(t)/Q,.
Therefore, the deposit purity depends on the pumping time, t, and the
deposition rate, but is independent of the pumping speed of the vacuum
system. In thecaseshown in Figure3b, thedeposition processisconfined
locally and represents a small perturbation to the vacuum system: i.e., the
gettered flux is small compared to the physically pumped flux. In this case
the flux of residual gas which enters the deposition region is given by
Equation 5 and is therefore dependent on the residual gas pressure in the
chamber. For a given pumping time, a larger pump will therefore decrease
this pressure and improve the purity of the deposits. Actual situations will
generally lie between the two extremes shown in Figures 3a and 3b.
However, most production deposition systems will tend toward the case
shown in Figure 3a.

3. EVAPORATION

3.1 Introduction
In the evaporation process, vapors of the coating material are released
from a source because of heating. The source material may be in the liquid
or solid state, depending on its vapor pressure relative to its melting point.
Almost any conceivable method can be used to heat thesource. One of the
most common methods is resistive heating, either of the source material
itself or of a support containing the material. Other common heating
methods involve the use of an electron beam, a laser beam, or an arc
discharge to produce local surface heating of the source material.
The evaporation process is usually carried out at a sufficiently low
pressure(typically 1O-5to 1 0e6Torr) so that the evaporated atoms undergo
an essentially collisionless “line-of-sight” transport to the substrates. In
this connection it is useful to remember that the mean free path of gas
particles is about equal to

X= 5/p,, cm (6)

where p, is thepressurein mTorr.Thusatapressureof 10-4Torr,Xisofthe

order of 50 cm and about equal to the size of a typical vacuum chamber. A
second reason for using a low pressure is to avoid oxidation of the hot
source material and the condensing coating. The substrates are generally
unbiased, i.e., electrically isolated or at ground potential.
The advantages of evaporation include the possibilities of high deposi-
tion rates and the fact that the source material can be in a relatively simple
form. Evaporation is most effectivefordepositing low melting point materials.
Althoughevaporationcan beusedforrefractorymaterials,the hightempera-
tures make the process more difficult to execute. Accordingly, it is estimated
that about 90% of the commercial applications of evaporation involve the
deposition of aluminum. Difficulties of stoichiometry control are encoun-
tered in evaporating many alloys and compounds. It is forthis reason that
sputtering is replacing evaporation for many microcircuit metallization
 Physical Vapor Deposition 337

applications (see Section 1). A host of special techniques have been

developed for evaporating multi-component materials. These include flash
evaporation, hot-walled evaporation, co-evaporation from multiple sources,
and reactive evaporation. Several of these methods have proven very
effective for depositing semiconducting coatings of high quality.
References8 to 10 contain detailed discussions of coating deposition
by evaporation.

3.2 Evaporation Rate

The rate at which atoms pass into vacuum from a heated source is
given by the Hertz-Knudsen equation

W = 35x1 O** (Yp*/(MT)-l/* atoms/cm*-set , (7)

where p* is the vapor pressure in Torr, T is the temperature in OK,and M is

the molecularweight ingrams. The parameter cuistheevaporation coeffici-
ent. It is dependent on the cleanliness of the evaporation surface and
can range from unity for clean surfaces to very low values (1 0e3)for dirty
surfaces.g The evaporation coefficient can also be less than unity in the
case of materials that evaporate as moleculesforwhich the liquid-to-solid
phase change involves a change in degree of freedom.g
Thevaporpressure,p*, isaverysensitivefunctionoftemperature.This
is shown in Figure 4 for several materials. Thus maintenance of a constant
evaporation rate requires extreme control over the temperature. This is
often a difficult task This problem is frequently avoided by using an in situ
thickness monitor to simply indicate when the desired coating thickness
has been achieved (see Section 3.7) or by evaporating a fixed charge of
source material to completion.
Rough estimates of required source operating temperatures are com-
monlybasedontheassumptionthatvaporpressuresof~lO-*Torrmustbe
established to produce useful condensation rates. Temperatures, T,, that
give p*=l O-* Torr are given in Tables 1 and 2 respectively for typical ele-
ments and inorganiccompoundsof interest in electronics relatedapplica-
tions. More detailed tables are given in References 8-l 0.
The average energy of the evaporated molecules is 3/2 kT where T is
the source temperature. Thus for the case of gold, where the source
temperature is 1400°C at p* = 1O.*Torr, the kinetic energy of the evaporated
Au atoms will be about 0.20 eV.
The emission of vapor from a liquid or solid surface obeys the cosine
emission law for the case of clean metal surfaces where (Y= 1, and to first
order for other cases9 Thus the evaporated flux from a small source, of
area A, and,evaporation rate W, which is incident on an elemental substrate
area located at an angle @Joff the perpendicular axis of the source as
shown in Figure 5, yields a deposition flux per unit area of the substrate
that is given by

w,= WAe co&$ case

7rr2
338 Semiconductor Materials

0 MELTING POINT

300 400 500 600 800 1000 1600 2000

TEMPERATURE (‘C)

Figure4: Equilibrium vapor pressures of several elements and inorganic com-

pounds of interest in electronics related applications.

where r is the distance from the source to the substrate. The Co@ term
accounts for the fact that the substrate may not be perpendicular to the
lineofcentersconnectingthesourceandsubstrate.Thethicknessgrowth
rate of the film is given by

DC MW, (9)
PNA
where N, is Avogadro’s number, and M is the molecular weight and p is the
mass density of the deposit.
Depositionratesfortheevaporationprocessareclearlydependenton
the material being evaporated, the type of evaporation source, and the
position and orientation of the substrate surface. Consider the case of
aluminum evaporation from a 1 cm diameter source onto a substrate
located 15 cm directly above the source (COSQ = 1) and oriented to face
the source (Cosf3 = 1). Thus we have r = 15 cm (this is a typical distance),
and Equation 8 yields W, = W/707. From Table 1 we see that a source
temperature of 1220°C is required to provide p* = 1O-2Torr. We assume
that this temperature is used. Therefore, from Equation 7 with p* = lo-*
 Physical Vapor Deposition 339

Table 1: Temperatures and Support Materials for Evaporating Elements

Commonly Used in Electronics Related Processing

Melting Temp. (%) at

Predominant Temp. (‘C) 1O-2 Torr Support
T’TI.1
Element Vapor Species T (OK) Materials**
TM..-..-

Aluminum Al 659 1220 1.61 W,C,BN

Antimony Sb4,Sb2 630 530 0.89” Mo,Ta,BN,Oxides
Arsenic As4,As2 820 300 0.52* Oxides ,C
Beryllium Be 1283 1230 0.97* Mo,Ta,W,Oxides
Cadmium Cd 321 265 0.91* Mo,To,W,Oxides
Chromium CK - 1900 1400 IO.77” Ta ,W
Copper Cu 1084 1260 1.13 Mo,Ta,W,C,A1203
Ga 11 ium G:! 30 1130 4.63 Be0,A1203
Germanium Ge 940 1400 1.38 Mo,Ta,W,C,Al203
Gold AU 1063 1400 1.25 Mo,W,C
Indium In 156 950 2.85 M0,W.C
Lead Pb 328 715 1.64 Mo,W
Molybdenum MO 2620 2530 0.97*
Nickel Ni 1450 1530 1.05 W ,Oxides
Palladium Pd 1550 1460 0.95* W,A1203
Platinuw Pt 1770 2100 1.16 W ,Oxides
Silicon Si 1410 1350 0.96* Br0,%r02,C
Silver Ag 961 1030 1.06 Mo,Ta,C
Tantalum To 3000 3060 1.02
Tellurium Tti 450 375 0.90* Mo,Ta,W,C,A1203
Tin Sn 232 1250 3.02 Ta,W,C,A1203
Titanium Ti 1700 1750 1.03 Ta,W,C,ThO?
Tungsten W 3380 3230 0.96*
Zinc Zn 420 345 o.t19* Mo,Ta,W,C,A1$3
Zirconiuts Zr 1050 2400 1.26 Id

“Materials that can bc evaporated effectively from solid state.

**See References 8 and 9 for more detailed specifications.

Torr, T= 1493” K, an aluminum molecular weight of 27 gm, and (Y= 1, we

obtain W = 1.75~10’~ atoms/cm-sec. From Equation 8 we obtain W, =
2.5~10’~atoms/cm~-sec. Ifweassumeabulkdensityof2.7gm/cm3forthe
aluminum deposit, we obtain D = 4.1 A/set or0.41 nm/sec using Equation 9.
Rates of 1 to 10 nm/sec are typical for many materials. In practice, for a
low melting point material such as aluminum, a p* of about 10-l Torr and a
deposition rate of 4 nm/sec would be more typical for many applications.
Finallywecanconsidertheimpuritylevelwhichwemightexpect inour
aluminumcoating. Weassumeap*of 10-l Torrsothatthedepositionfluxis
2.5~10~~atoms/cm~-sec.Weassumethattheresidualgaspressureduring
deposition is 1 0e6Torr. Thus, using Equation 5 and the molecularweight of
oxygen, we estimate a residual gas flux of 3.6~10’~ molecules/cm*-set
reaching the substrate. Since each oxygen molecule contains two atoms,
the implied impurity level is about 3%. High purity starting material, high
deposition rates, and/or low residual gas pressures are required to assure
high purity deposits.
340 Semiconductor Materials

Table 2: Direct Evaporation of Inorganic Compounds Commonly Used

in Electronics Related Processing

Melting Temp. (‘C) at

Predominant Temp. (OC) 10-2 ‘rorr T/TM Support
Vapor Species* TM T a Materials**

Al,O,AlO 2030 - 1800 0.90 Mo,W

Al203
*120,02(*10)2

In,In20,02 Vapor species Pt

I”203
observed at
1 loo- 1450°C g

SiO SiO 1025 Mo,Ta

S i02 Si0,02 1730 - 1250 0.76 Mo,Ta,W

Ti02 Ti0,Ti,Ti02 1840 Low vapor

02 pressure dt
2000% 9

IJO3 (WO3)3,WO3 1473 1140 0.81 Pt

ZrO* Zr0,02 2700

ZnS 1830 1000 0.61 MO

(150 atm)

znsr 1520 820 0.61

(2 ntm)

CdS 175p 670 0.47 C,Mo,Ta,W

(100 atm) Al203

CdSe Sc2,Cd 1250 6GO 0.61

Al.203

PbS PbS,Pb,S2(PbSj2 1112 675 0.68 MO

MgP2 >@W2)2
MgF2 1263 1130 0.91 MO

0W2)3
CaF2 CaF2,CnF 1418 1300 0.93 M0

*Given in order of decreasing prominence.

**See References 8 and 9 for more detailed specifications.

3.3 Evaporation Sources

Several common types of evaporation sources are shown schematically
in Figure 6.
3.3.1 Wire and Metal Foil Sources. The simplest evaporation sources
are resistance-heated wires and metal foils of various types. A wire source
isshown in Figure6aandametalfoilsourceisshownin Figure6b.Theyare
commerciallyavailableinavarietyof materialsandsizes,atsufficientlylow
 Physical Vapor Deposition 341

EMISSION FLUX FFlOM SMALL SOURCE OF AREA A,

W,=VJA,Cosd

DEPOSITION RATE PER UNIT AREA

Wd=~CosQCorcl
II J

Figure 5: Flux passing from small area source to elemental substrate area dAS
which inscribes solid angle dw.

prices to be discarded after one use if necessary. The wire or foil supports
must be fabricated from materials which have negligible vaporordissocia-
tion pressures at the operating temperatures. These temperatures are
typically in the range from 1000 to 2000°C. Wetting of the wire or foil
surface bytheevaporant isalsodesirableinordertoachievegood thermal
contact. Detailed recommendations pertaining to wire or foil support
materials for various evaporants are given in References 8 and 9. These
recommendations for a few evaporants are summarized in Tables 1 and 2.
The most commonly used support materials are tungsten, molybdenum,
and tantalum. Suitable wire or foil sources are available to evaporate small
charges of nearly all the elements except the refractory metals themselves.
Themaximumcapacityofwireandfoilsourcesistypicallyafewgrams.
The usual approach is to calculate the charge of source material that will
provide a given deposit thickness, using a relationship of the form of
Equation 8 for the apparatus geometry in question, and then to evaporate
the entire charge. The wire/foil approach is in general too time-consuming
for most production applications, but it is an effective method, for example,
for depositing test electrodes in laboratory studies.
3.3.2 Crucible Sources. Crucible sources are required to support
molten metals in quantities of a few grams or more. Since the melt is in
contact with the container for prolonged periods of time, the selection of a
noncontaminating and thermallystablecruciblematerial isveryimportant.
Detailed recommendations for crucible materials are given in References
8 and 9. The non-metallic support materials summerized in Tables 1 and 2
apply strictly to crucibles. Thus it is seen that graphite and the refractory
 METAL FOIL SOURCE RESISTANCE HEATED CRUCIBLE
RESISTANCE HEATED WIRE

==I!@&\-

a
b
SUBLIMATION SOURCE

RF HEATED CRUCIBLE

RADIATION
SHIELDS
MOLTEN METAL

d e
Figure 6: Schematic illustrations showing several types of evaporation sources.
 Physical Vapor Deposition 343

oxides are commonly used in addition to the refractory metals as crucible

materials.
A wide variety of methods are used to heat the crucibles. The most
common methods are radiation heating from asurrounding oven, conduc-
tion and radiation heating from a surrounding coil as shown in Figure 6c,
and rf induction heating as shown in Figure 6e. The latter method has the
advantage that energy is coupled directly into the evaporant metal, so that
it is not necessary to produce crucible temperatures in excess of the
vaporization temperature in order to produce heat flow.
3.3.3 Sublimation Sources. Figure 4 shows that the vapor pressures
of materials increase continuously with temperature and do not show an
abrupt change at the melting point. Tables 1 and 2 show, in fact, that many
elements and compounds reach a pressure of about 1O-2 Torr before
melting (i.e., TJT, <l in Tables 1 and 2) and hence can be sublimated at
rates which are practical for coating applications. Direct wire and foil
evaporation is particularly effective for metalswith significant sublimation
rates. Figure 6d shows a rod type sublimation source that has been used
for chromium.g Sublimation sources remove the problem of contact with
foreign support materials.
3.3.4 Baffle Type Sources. In the evaporation of many materials the
spontaneous release of absorbed or occluded gases can cause theviolent
ejection of droplets or, in the case of sublimation, particulates of the
evaporation material. These particles can become incorporated into the
growing film. To avoid this problem, baffled sources are often used which
inhibit direct line-of-sight transmission from the evaporation charge to the
substrates. These baffles are typically constructed of Ta and are maintained
at sufficiently high temperature to prohibit condensation (see Figure 11 in
Section 3.5). Atoms or molecules incident onto such baffles are generally
re-emitted in a cosine distribution.*
3.3.5 Knudsen Cell Sources. A Knudsen cell is an evaporation
crucible with a small exit orifice. The orifice is made small enough so that
the evaporation flux passes through it via free molecular flow. The flux is
emitted in a near cosine distribution if the thickness of the orifice is
negligible.* Formation of a molecular beam occurs under conditions of
free molecular flow when the aperture is in the form of a tube. Although the
flux is not baffled, the small size of the orifice makes Knudsen cells
relatively immune to the spitting described above. A principal advantageof
the Knudsen cell is that, when the surface area of the evaporant isan order
of magnitude larger than the aperture, control of the evaporant temperature
establishes the pressure, p*, which exists inside the cavity in front of the
orifice. Since there is no phase change as material passes through the
orifice, Equation 7 with (Y= 1 iscloselyobeyed.sThis removal of uncertainty
over CI allows effective control of the deposition rate by controlling the
source temperature. (Holland draws the analogy between the use of a
Knudsencellandtheuseofacavityforobtaining blackbodyradiationfrom
a substrate whose emissivity is less than unity.8) Therefore, Knudsen cells
are particularly important when film stoichiometry is to be controlled byco-
evaporation (see Section 3.5).
The general term “effusion cells” is used to identify the class of cells
344 Semiconductor Materials

with flow orifices that are restricted but not necessarily small enough to
satisfy the free molecular flow conditions that are implicit in the particular
case of the Knudsen cell. The flow from effusion cells can be theoretically
predicted if the fluid dynamics of the flow through the orifice is properly
taken into account. However, as a general rule the emission characteristics
as a function of temperature from effusion cells, including Knudsen cells,
are determined experimentally. Figure 7 shows an array of effusion cell
sources used for multi-source deposition of semiconducting coatings of
CulnSe,. ” Effusion cells play a very important role in the process of
molecular beam epitaxy, which is discussed in Section 4.
3.3.6 Electron Beam Sources. Figure 8 showsaschematicdiagram
of an electron beam evaporation system. Since the beam is concentrated
on the evaporating surface, while other portions of the evaporant are
maintained at lower temperatures, the evaporant can form its own crucible.
Hence, interactions between evaporant and support materials are greatly
reduced. Electron energies are typically in the 3 to 10 KW range, with
power levels in the range2 to50 KW.Therefore, relatively highevaporation
rates can be achieved, even for the refractory metals. Rod-fed sources can
provide a large inventory of coating material. Therefore, electron beam
sources are the most commonly used evaporation sources for large scale
production applications. However, two difficulties that must be dealt with
are, first, that electron beam sources are vulnerable to spitting because of

, WART2 CRYSTAL
MONITOR

SUBSTRATE

VACUUM -
CHAMBER

/
SHIELD

SOURCE ’
HEATER
ASSEMBLY

/ PUMPING
THERMOCOUPLES

L-J PORT

Figure 7: Knudsen cell evaporation sources arranged for co-evaporation to form

coatings of CulnSe2. See Reference 11.
 Physical Vapor Deposition 345

SUBSTRATES

VAPOR FLUX

MAGNETICALLY FOCUSED
MOLTEN ELECTRON BEAM
POOL

EVAPORANT
SUPPORT
BEAM SOURCE

SOURCE MATERIAL
TO VACUUM
(MAY BE ROD WITH
PUMPS
AUTOMATIC FEED)

Figure 8: Schematic diagram of electron beam evaporation source.

the high power densities at the point of beam impact, and second, that the
deposition flux is nonuniform as discussed in Section 3.4.
3.3.7 Other Types of Evaporation Sources. Several othertypes of
evaporation sources have been developed to deal with the particular
problems associated with forming stoichiometric coatings of alloys and
compounds. These are discussed in Section 3.5.

3.4 Deposit Thickness Uniformity

It is difficult to maintain a uniform evaporation temperature over large
surface areas because of radiation losses9 Consequently, relatively small
area sources are nearly always used. Deposition fluxes in the substrate
plane are therefore non-uniform, and some type of substrate movement is
generally required.
A small source emitting from its surface according to the cosine law
will provide uniform deposition overthe inside of a spherical surface if the
source is placed on the circumference.8This is easilyseenfrom Equation 8
by noting that Cos@ = Co& and r = 2R Costi, for all deposition points on
the circumference of a sphere of radius R. Therefore, planetary substrate
holders of the type shown in Figure 9, which continuously move the
substrates over a hemispherical surface with its center placed about one
radius above the source, are commonly used.
Theoreticaldeposition profilescalculatedfrom Equation8aregiven in
References 8 and 9 for evaporation from point sources, small area sources,
extended strip sources, cylindrical rod or wire sources, and ring and
circular disk sources, all depositing onto plane receivers. The calculations
show that the thickness uniformity of coatings deposited from flat filament
or crucible sources cannot be improved significantly by enlarging the size
of the sources, but that ring sources are particularly effective in providing
346 Semiconductor Materials

SUBSTRATES

SOURCE /’ -

Figure 9: Schematic illustration of planetary type substrate tooling for small

area vacuum coating source.

near-uniform deposits over relatively large areas. In particular, the deposit

thickness is uniform over an area about equal to the area inside the ring
when the substrate is placed above the ring at a distance equal to its
radius. This is also an important consideration when using ring type planar
magnetron sputtering sources. See Section 5.6.
Theoretical and experimental deposition profile data are also given in
References 8 and 9 for several practical evaporation sources. The degree
to which wire baskets of the type shown in Figure 6a duplicate a point
source depends on the density of the wire winding. A dense winding
promotes directional emission from the open ends.6 Flat metal strips or
shallow dimpled boats of the type shown in Figure 6b have been found to
yield near cosine-law emission. The emission patterns from practical
effusion cells of the type shown in Figure7 tend to be more directional, and
to have a more pointed maximum in the center than the cosine emission
pattern, because the requirement of negligible aperture thickness is
usually not satisfied. The emission patterns from crucibles with relatively
wide openings, and cylindrical cone shaped side walls which can act as
extended emitting surfaces, tend to follow the cosine emission law, although
the deposition profiles are slightly more directional than those predicted
forcosineemissionfrom aflatsurfacesource. Electron beamsourcestend
tobehaveassmallareasources,butoftendepartfromthecosineemission
law becausethe high evaporation rates, which aretypicallyachieved, yield
high enough vapor densities in the immediate vicinity of the source to
cause collisional scattering of the evaporated molecules.

3.5 Evaporation of Alloys, Compounds and Mixtures

3.5.1 Introduction. The constituents which are present in most inor-
ganic compounds, alloys, or mixtures differ in their vapor pressures. Conse-
quently, during evaporation the composition of their vapors, and hence of
their condensates, is not the same as that of the source material. This
behavior is known as incongruent evaporation.
The available thermochemical data are seldom sufficient for predicting
the conditions necessary to achieve coatings of the desired composition.
Accordingly, the approach is usually empirical. Often, because of incon-
gruent behavior, coatings of the desired composition cannot be reached
 Physical Vapor Deposition 347

by direct evaporation. This has led to the use of special methods such as
flash, two-source, and reactive evaporation. These processes are discussed
in Section 3.6.
3.5.2 Evaporation of Alloys. The constituents in alloys evaporate
independentlyof oneanother, mostlyassingleatoms. However, thevapor
pressures of the individual constituents are not equal to their pure metal
values at the temperature in question, because there is a contribution to
the chemical potential when one metal is dissolved in another. Most
metals evaporate incongruently, and this has led to the use of sputtering
where extreme composition control is necessary. An example is the
deposition of Nichrome (80%Ni - 2O%Cr) to form thin film resistors. How-
ever, in the important case of Permalloy(85%Ni - 15%Fe), the evaporation
issufficientlycongruent topermittheuseofsimplesinglesourceevapora-
tion for many applications8
Electron beam evaporation can significantly expand the range of
materials which can be evaporated with reasonable composition control.1°
This is possible because the electron beam source creates a small molten
region, as shown in Figure 10. During an incubation period the molten
region becomes deficient in the volatile species. The composition is then
rate-limited by the passage of material by diffusion from the solid into the
melt, across interface “A” in the figure. If the vapor pressure difference is
not too large for the constituent diffusion rates, a steady state is developed,
where the composition of the melt is just such as to produce a vapor
composition equal to that of the solid. It is reported that reproducible
compositions of Ni-20Cr, Ti-GAI, Ag-SCu, Ag-1 OCu, Ag-20Cu, Ag-30Cu,
and Ni-xCr-yAl-zY have been successfully achieved by electron beam
evaporation.1°
3.5.3 Evaporation of Compounds. In the evaporation of compounds
the transition to the vapor phase rarely occurs without changes to the
molecularspecies.Thusevaporation isusuallyaccompanied bymolecular
dissociation, association, or a combination of both processes. Dissociation
represents thermal decomposition and generally makes simple direct
evaporation impractical. The species formed in the direct evaporation of a
number of compounds are summarized in Table 2.

EVAPORATED
FLUX

RATE LIMITING
FLtiX

SOURCE -
MATERIAL

Figure 10: Schematic drawing showing equilibration of molten region during

electron beam evaporation.
348 Semiconductor Materials

There are, however, some important compounds that do evaporate as

constituent molecules and thereby maintain their composition. Most not-
able are SiO, MgF, and CaF,, a fact which explains the successful use of
thin evaporated coatings of these materials in theoptics industry.12 Similar
behavior is found for B,O,, GaF,, and most of the divalent group IV oxides
such as GeO and SnO (SiO-like species).g
Generally, the tendency to produce a dissociated vapor flux increases
with increasing evaporation temperature and decreasing pressure. The
evaporation of most oxides requires temperatures in excess of 1500°C.
The binary oxides of Be, Mg, Ca, Sr, Ba, and Ni evaporate predominantly by
dissociation into metal atoms and oxygen molecules, although their vapors
may contain molecular species and in some cases lower oxides. The
tendencytoform suboxides isstrongeramong group three metalssuch as
Al and In (see Table 2). Generally, congruent evaporation is more likely to
be attained with binary oxides than with sesqui- or dioxides, because the
higheroxidestendtoloseoxygenattemperatureswhicharetoolowforthe
volatilization of the resulting suboxides.g However, it is reported thatAl,O,,
SiO,, and ThO,, as well as MgO and BeO, films have been successfully
deposited by direct evaporation using electron beam heating.gThe oxides
of Ti, Zr, Nb, Ta, Fe, and Cr are examples of materials which do not
evaporatecongruentlyandforwhich difficulties have beenencountered in
obtaining stoichiometric films by direct evaporation.
The II-VI compound semiconductors are important examples of com-
pounds that undergo complete dissociation on evaporation. However,
both the group II and the group VI elements in these compounds are
relatively volatile, with the consequence that they are amenable to direct
evaporation,13 with the coating stoichiometry being controlled by the
substrate sticking coefficient.
The Ill-V compound semiconductors are an example of materials that
undergo severely incongruent evaporation. The vapor pressures of the
group V constituents, such as P, As, and Sb, are orders of magnitude
greater than those of the group III elements, such as Al, Ga, and In.
Accordingly, these compounds are difficult to deposit by direct
evaporation.6~13~14
Bi, C, Si, Te, P, As, and Sb are examples of materials that undergo
associationtoformpolyatomicspecies.Forexample,AsyieldsAs,andAs,
Other examples are the oxides of molybdenum and tungsten, which can
yield (MO,), and (WO,), species with n typically equal to two or three.

3.6 Special Evaporation Methods

Several special evaporation techniques have been developed for
depositing materials whose constituents have different vapor pressures.
3.6.1 Flash Evaporation. In this technique small quantities of the
constituents in the desired ratio are evaporated to completion from a
common source using a temperature sufficiently high to evaporate the
less volatile component. Often the evaporant is dispensed as a steady
trickle onto a hot filament. A wide range of apparatus configurations have
been devised for dispensing the source material. See Reference 9. The
method is applicable to the evaporation of alloys, metal-dielectric mixtures,
 Physical Vapor Deposition 349

and compounds. In most cases, the vapors impinging on the substrate are
highly supersaturated, so that the film composition is not affected by the
condensation coefficients. (Condensation coefficients are discussed in
Section 6.1.) The most common problem is incomplete evaporation due to
particle ejection and deflection. Ni-Cr alloys, Cr/SiO cermets, GaAs, InP,
CL@, and BaTiO, are examples of materials that have been deposited by
flash evaporation.
3.6.2 Hot-WallEvaporation. Inthistechniquefilmsaregrownunder
conditions that areclose to thermodynamicequilibrium.15-16aAschematic
drawing of a hot wall evaporation apparatus is shown in Figure 11. The
evaporated flux is passed into an enclosure with walls held at a sufficiently
high temperature so that condensation is precluded. Accordingly, stoichio-
metric coatings can be deposited, even on substrates maintained at such
high temperatures that one or more of theconstituents has a lowcondensa-
tion coefficient. Since wall condensation is prohibited, the vapor pressures
of the volatile constituents simply build up until they deposit onto the
substrates at steady state rates that are equal to the rates at which they
enter the enclosure from the evaporation sources. For example, near-
stoichiometric CdTe films have been evaporated from a single CdTe
source maintained at 600°C with a hot-wall temperature of 5Oo”C, and a

SUBSTRATE
TEMPERATURE -T,

HOT WAL
T > T,
VACUUM
CHAMBER

\ EVAPORATION
SOURCES

PUMP

Figure 11: Schematic illustration of hot-wall evaporation system. Baffle of type

discussed in Section 3.3 is shown on one of sources. Arrows show coating flux
directions and are not meant to imply individual atom trajectories, since atoms
are generally re-emitted from walls and baffles in a cosine distribution.
350 Semiconductor Materials

substrate temperature 465”C.16 If two sources are used, as shown in

Figure 11, then the stoichiometry of the coating can be controlled. Thus
non-stoichiometric n-type CdTe coatings were deposited using Cd and
CdTe sources at the following temperatures: Cd-330°C CdTe-600°C hot-
wall-550”C, substrate-51 5”C.16
The key advantage of the hot-wall method is that coatings of materials
with volatile constituents can be grown with controlled composition at
elevated temperatures. Elevated substrate temperatures are often desi-
rable,sincecoatingpropertiestendtoapproach bulkvaluesasthesubstrate
temperature is increased. See Section 6.2.
3.6.3 Close-spaced Sublimation. This is anothertechnique in which a
net thermal transport of coating material occurs under conditions close to
thermodyunamic equilibrium. Figure 12 shows a schematic drawing of a
close-spaced sublimation apparatus. A flat plate source of coating material
and the substrates are maintained in close proximity to one another, being
separated by only a few mm. The temperatures of the source and substrates
are both maintained at values such that the sublimation rates are signifi-
cant, but with a temperature difference so that a net transport of coating
material occurs from the source to the substrates. The space between the
source and substrates is so small compared to the lateral dimensions that
little escape of the vapors occurs. Hot walls, such as those shown in Figure
12, may be used to further hinder this escape. Relatively high deposition
rates can be achieved. For example, CdTe films have been deposited at 67
nm/sec using a CdTe source temperature of 660°C and a substrate
temperature of 600” C, and CdS films at 1000 nm/min using a CdS source
temperature of 720°C and a substrate temperature of 550”C.17
As with the hot-walled method, the advantage of close-spaced subli-
mation is that near-stoichiometric coatings containing volatile constituents

GAS
INLET

VACUUM -
CHAMBER I
HEATER

- SUBSTRATES
WALLT>T, -
NO CONDENSATION
- SUBLIMATION

PUMPING
PORT

Figure 12: Schematic illustration of close-spaced sublimation type deposition

apparatus.
 Physical Vapor Deposition 351

can be deposited at relatively high substrate temperatures. The films can

bedoped byintroducingagaseousimpurity. Inasomewhatsimilartechnique
called close-spaced vapor transport, a reactive gas is introduced which
promotes the formation of volatile species and thereby permits the trans-
port to take place at lower temperatures.18
3.6.4 Multi-source Evaporation. In this method two or more inde-
pendent sources are operated simultaneously, thereby permitting the
deposition of multiconstituent materials which are not amenable to direct
evaporation. The types of sources employed are the same as in single-
source evaporation. An apparatus using effusion ceils was shown in Figure
7 and one using open crucibles is shown schematically in Figure 13. By
controlling the power delivered to the sources it is possible, in principle, to
circumventtheproblemsoffractionationanddecompositionencountered
in the direct evaporation of most alloys and certain compounds.
There are two central problems in this technique. The first iscontrol of
deposition rates in the exact constituent ratiodesired. Control isgenerally
achieved through direct measurement of the particle fluxes in the vapor
streams. (See Section 3.7.) This feedback method is used for the open
crucible Cu-In-Se evaporation shown in Figure 13. The emission rate from
effusion cell type sources is generally a reproducible function of the
source temperature. Therefore, the effusion rates in multi-sourcesystems
usingeffusioncellscan becontrolled byfeed-forwardsystemsthatcontrol
the temperatures within the cells, as indicated in Figure 7. The second

“LI.““II
SELENIUM
(In & Cul I I CRUCIBLES

- HEATER
CONTROL

CONTROL

INDI IUM
BOA T

WATER COOLED
SHIELD PLATE
COPPER
BOAT
L
Figure 13: Multi-source evaporation system using open crucibles to deposit
CulnSe* semiconducting coatings. See Reference 19.
352 Semiconductor Materials

problem encountered in the multi-source evaporation method is the limited

deposition area overwhich coatings have a uniform composition. It is also
important that the sources be arranged to minimize deposition flux angle-
of-incidence effects. See Section 6.2.
Multi-source evaporation permits the co-deposition of materials that
do not form compounds or solid solutions. An example is the co-evaporation
of ceramic oxides and metals such as SiO and Cr or Au to form cermet thin
film resistors. Other examples are metals such as Nb-Sn and compound
semiconductors such as ZnS, CdS, CdSe, BiSe, BiTe, GaAs, InAs, InSb,
AISb, and CulnSe,, as shown in Figures 7 and 13.
In the case of many compounds the condensation rate is not solely a
function of the ratio of the arriving constituent fluxes, but is also determined
by surface reactions on the substrates. For some compounds involving
constituents of widely differing volatility, a substrate temperature can be
selected such that only the stoichiometric compound can survive and
grow. In such cases less stringent control of the individual impingement
fluxes is required. In fact, one of the important advantages of multi-source
evaporation is its applicability to this so-called “three temperature method’.
See Section 6.2. Multi-source evaporation with extreme control over
substrate reactions forms the basis of a special method called”Molecular
Beam Epitaxy” which is discussed in Section 4.
3.6.5 Reactive Evaporation. In this techniquea metal isevaporated
in the presence of a reactive gas in order to form a compound of the metal
and the reactive gas. The technique is most commonly used to form
coatings of metal oxides that cannot be evaporated directly because of
complete or partial decomposition. Table 3 lists deposition conditions for
reactive evaporation of some metal oxides9
Deposition conditions are selected so that the reactions occur at the
substrate surface. Consequently, the growth process is controlled by the
impingement rates of the metal and reactive gas atoms, the condensation
coefficients of the two species, and thesubstrate temperature. The central
problem in reactive evaporation is that while the condensation coefficient
of the metal constituent is usually near unity, the condensation coefficients
of the reactive species become very low as full stoichiometry is approached
in the deposit. This is shown for the Si+O, case in Figure 14, where an OJSi
impingement ratio of between lo* and lo3 is required to form coatings
having a composition approaching SiO,
It is generally found that the use of high reactive gas pressures, to
provide high impingement ratios, has detrimental effects on film properties:
for example, reduced hardness and refractive index. See Section 6.2.
Accordingly, as can be seen in Table 3, deposition rates are usually kept
low, in the few angstrom per second range, to provide the required high
reactive-gas-molecule to metal-atom impingement ratios without requiring
gas partial pressures above 1Om4Torr. Elevated substrate temperatures
arealsogenerallyusedinordertopromotethesurfacereactions,tolessen
the detrimental effects of high reactive gas pressures, and to provide
significant improvements in structure. Coatings deposited at elevated
substrate temperature exhibit improved crystallinity, density, hardness,
optical constants, and dielectric properties. By contrast, films deposited at
 Physical Vapor Deposition 353

2
10-l 100 10’ 102 103

Og/Si IMPINGEMENT RATIO

Figule 14: Film stoichiometry versus oxygen-to-silicon impingement ratio for

react,vely evaporated films. Data from Reference 20.

Table 3: Reactive Evaporation of Metal Oxides

EvaporaVd Des ired Oxygen Deposition Substrate

Metal Metal Oxide Pressure (Ton) Rate &Is1 Temperature (‘C)

Al A1203 10-5 - 10-4 -1 400-500

Cr Cr203 2x10-5 -2 300-400

Ta Ta205 10-4 - 10-3 -2 700-900

Ti Ti02 10-4 300

BafTi BaTiC3 10-2 2-0 770-1025

Data fro!, Ref. 9.

low substrat ? temperatures tend to have amorphous or poorly crystallized

structures (s?e Section 6).
The low .eactive gas condensation coefficient occurs because the
reactive gas tnolecules must undergo dissociative chemisorption on the
surface of the growing film, with the resulting reactive atoms being incorp-
orated into tht coating. The reaction process can be stimulated, and high
deposition ratIts can be achieved, by using a plasma to dissociate the
reactive gas molecules and/or to produce other species that promote the
surface reactior’s involved in compound formation. The process is generally
referred to as pl;\sma assistedoractivated reactive evaporation(ARE). The
reactive gas ma,/ be passed through a hollow cathode discharge,*’ or an
354 Semiconductor Materials

external electrode may be used to create a plasma discharge in the

deposition chamberasshown bythe AREapparatus in Figure 15TheARE
process has been successfully used, for example, to produce oxide,
carbide, nitride and sulfide films of various metals.10~23

3.7 Deposition Rate and Flux Monitors

One of the disadvantages of evaporation, as compared, forexample, to
sputtering, is that the rate of passage of material into the vapor phase is a
very nonlinear function of the power delivered to the source. Thus as a
general rule, the evaporation flux must be monitored tocontrolthedeposit
thickness. Deposition rate and species flux monitors also play a very
important role in the multi-source evaporation process. Several types of
rate monitors are available. They are discussed in detail in Reference 9.

1) ionization Gauge Rate Monitors. These devices are similar to

hot cathode ionization gauges. They monitor the atom density
inthevaporphasebyionizingthevaporsandmeasuringtheion
current. The obvious difficulty is residual gas contributions to
the current.

2) Mass Spectrometers. Quadrupole mass spectrometers are

small enough so that they often can be conveniently arranged

CLECTRON BEAM

Figure 15: Schematic drawing of apparatus configuration for activated reactive

evaporation.From Reference 22. See Reference 23.
 Physical Vapor Deposition 355

to intercept the vapor flux. This method is frequently used in

molecular beam epitaxy (see Section 4).
3) Nectron impact Spectroscopy. The vapor flux is passed through
an electron beam which produces an atomic line emission that
is monitored, usually with a narrow band filter and photomulti-
plier. An electron impact spectroscopy type sensor is used to
monitor the Cu and In fluxes in the apparatus shown in Figure
13.
4) Microbalances. The balance is used to measure the accumu-
lated coating mass on a thin vane.
5) Crystal Oscillators. This method utilizes the piezoelectric prop-
erties of quartz and the fact that the resonant frequency is
influenced by the accumulation of a mass of coating material on
the surface of the crystal. A quartz crystal monitor for controlling
the Se evaporation rate is shown in Figure 13.

3.8 Evaporation Source Material

An advantage of the evaporation process as compared, for example, to
sputtering, is thesimpleform of thestarting material; i.e., the material does
not have to be in the form of a sputtering target. However, the need for
purity cannot be overemphasized. Impure source material not only results
in impurecoatings, but alsocan lead to the difficuItiesof“spitting”discussed
in Section 3.3. These problems are particularly severe for electron beam
evaporation because of the high power levels involved. Therefore, vacuum
melted, rather than power metallurgy, metal rod sources should be used in
electron beam evaporation.

4. MOLECULAR BEAM EPITAXY

4.1 Introduction
Molecularbeamepitxy(MBE)isamulti-sourceevaporationprocess,of
the type discussed in Section 3.6, which is done with extreme control over
the deposition parameters in order to exploit the kinetic processes of film
growth that are discussed in Section 6.1. MBE has been applied primarily
tothegrowthofsinglecrystalfilmsofcompoundsemiconductors.Thermal
molecular beams of each constituent of the film are directed to converge
onasinglecrystalsubstrateunderconditionssuitableforepitaxialgrowth.
Deposition rates are low (typically about 0.1 rim/see). The low deposition
rates reduce the temperature required to achieve epitaxialgrowth(Figure
47 in Section 6.2). The low growth rates are made feasible by the use of
ultra-high vacuum systems which have base pressures in the 1 O‘lOto lo-l1
Torr range and thereby reduce the residual gas contamination flux incident
on the substrates, as discussed in Section 2.
The slow growth rates permit very precise control of layerthicknesses
in the nm range. Shields are used to provide abrupt initiation or cessation
of the molecular beam fluxes and thereby to create sharp interfaces or
356 Semiconductor Materials

precisely controlled doping profiles. The reduced growth temperatures

minimize the disturbance of these built-in composition profiles because of
bulk diffusion.
An important advantage of MBE over most otherforms of epitaxy is the
ability to include in situ facilities for process monitoring and control and for
surface analysis. These diagnostic tools include (1) quadrupole mass
spectrometers to monitor the composition of the incident beam and the
residual background gases; (2) high energy electron diffraction (HEED)
systems to monitor the surface structure of the substrate and coating; and
(3)Augerelectronspectroscopy(AES)systemstomonitorthecomposition
at the substrate surface before and during coating.
Excellent reviews of MBE are given in References 24 to 31.

4.2 Apparatus Configuration

Figure 16 shows a schematic diagram of a typical MBE deposition
chamber. The systems generally have three to eight evaporation sources.
Resistance or electron beam heated sources are usually used. However,
gas phase sources may be used.32 This arrangement is sometimes referred
to as chemical beam epitaxy. Crucibles are typically made from pyrolytic
boron nitride because of its inertness to metals such as Ga and Al. Source
temperaturesaregenerallycontrolledtowithinabout0.2”C,usingthermo-
couples inserted within thecrucibles. 26Precise temperature control of the
individual cells is essential because of the strong temperature dependence
of the evaporation rate(see Section 3.2). Thus, temperature fluctuationsof
fl”Ccan result in molecularbeamfluxvariations ranging from+2 to4%.28
Shuttersare provided, as noted previously, toabruptlycontrol thefluxfrom

AUGER
ANALYZER

QUADRUPOLE MASS
SPECTROMETER ,, -) ION SPUTTER GUN

TvL VIEW PORT

‘--*I-L
*_ FLUORESCENT

_.-_.-
3 NITROGEN
Ll.>nn, I_

EFFUSION CELLS

Figure 16: Schematic illustration of MBE deposition chamber with sources con-
figuredfor depositing GaAs type films.
 Physical Vapor Deposition 357

a source which in turn is controlled to provide a given steady state

emission.
MBE pumping systems typically use carbon vane, turbomolecular, or
sorption pumps for the initial chamber evacuation. Titanium sublimation,
ion pumps, and liquid nitrogen cryopanels are generally used for high
vacuum pumping, although oil diffusion pumps have been used. Most MBE
apparatuses have load locks for introducing the substrates. This is an
important consideration, since long pumpdown times and chamber heating
are generally required to reach ultra-high vacuums in an apparatus that
has been exposed to the atmosphere.
An important aspect of MBE systems is that liquid nitrogen cooled
shrouds are usually designed to cover as much of the wall surface as
possible in the deposition chamber. See Figure 16. In addition to impurity
species such as water vapor and CO, these cryogenic surfaces tend to trap
any coating atoms that are re-emitted from thesubstrate(sticking coeffici-
ent lessthanunity).Thusthefluxofagivenspeciesarrivingatthesubstrate
can beaccuratelycontrolled bythe powerdelivered to itssource.Thegoal
is generally to keep the partial pressures of residual gases with a high
sticking coefficient below 1 O-l4 Torr in the vicinity of the substrate.28 A
general guideline is to provide sufficient liquid-nitrogen-cooled surface
area in the deposition chamber to yield a pumping speed for water that
exceeds 20,000 liters/sec.27 In addition, liquid-nitrogen-cooled shrouds
are usually provided in the vicinity of the evaporation sources to prevent
intercontamination and thermal cross talk.
The schematic drawing in Figure 16 shows a number of characteriza-
tion tools, including an Auger spectrometer and an ion sputter gun. A
common practice is toconfigure MBEapparatuseswithseparatechambers
for sample analysis and deposition. A diagram of a typical commercial
system of this design is shown in Figure 17. A photograph of the apparatus
is shown in Figure 18. Such systems consist typically of (1) a sample entry
or load-lock chamber with a turbomolecular pump, (2) a sample analysis
chamber with an ion pump, Ti sublimation pump and cryopump, and (3) a
depositionchamberwithsimilarpumping.Thedepositionchambershown
in Figure 17 is equipped with a quadrupole mass spectrometer and a
HEED system. The test chamber is configured to incorporate an ion
sputter gun with provisions also for a range of surface analysis tools such
as Auger electron spectroscopy, X-ray photoelectron spectroscopy, or
secondary ion mass spectroscopy.
The quadrupole mass spectrometer is probably the single most import-
ant analytical tool in an MBE system.27 The second most widely used
technique is HEED.These instrumentsare placed in thedeposition chamber,
as shown in Figure 16, and are also recommended for production systems.28
Ion gauges are often used for neutral beam monitoring. Auger electron
spectroscopy is the most commonly used method of composition analysis.
Load lock systems introduce substrates in short time periods (%15
min) while the growth chamber is maintained in the lo-lo Torr range. In a
typical machine designed for small production runs, a batch of five two-
inch wafers is introduced into a preparation and analysis chamber, where
they are stored and sequentially cycled through thegrowth process, while
Physical Vapor Deposition 359
360 Semiconductor Materials

istypicallycoveredwithacontaminationlayerconsistingofcarbonaceous
compounds and oxides which must be removed. The most detailed MBE
workhasinvolvedthedepositionofGaAsontosinglecrystaIGaAssubstrates.
The (100) plane is chosen for the technologically important reason that it
has orthogonal (1 10) type cleavage planes.27 A typical preparation pro-
cedure involves polishing with a diamond paste followed by etch-polishing
on an abrasive-free lens paper soaked with a sodium hypochlorite or
bromine/methanol solution.** The substrate is then rinsed in trichloro-
ethylene, methanol, and distilled water, following which it is boiled in
hydrochloric acid, free etched in sulfuric acid, again rinsed in distilled
water, and finally soldered with In to a MO backing plate. At this point the
substrates, which are generally contaminated with both oxygen and a
small amount of carbon, are introduced into the MBE chamber.
A typical in situ process within the MBE chamber involves the use of
ion bombardment toremoveforeign materialsfrom thesurface,andAuger
spectroscopy to verify that the surface is clean. The sample is then passed
into the deposition chamber and annealed to remove the surface damage
created by the sputter cleaning. In many cases thermal desorption rather
than ion bombardment may be used to avoid composition changes due to
preferential sputtering. It is well established that temperatures in the 525
535°C range evaporate the passivating oxide film on GaAs without causing
surface composition changes because of incongruent evaporation of the
GaAs.28 In any event, the HEED system is used to verify the crystalline
quality of the substrate surface prior to deposition.
The sources are then adjusted to tempeatures that provide the desired
deposition rates. The shutters are closed during this operation to prevent
depositionon thesubstrates.Thesubstratetemperatureisadjustedtothe
desired value and the appropriate shutters are opened to commence
deposition.The HEED system can be used to provide periodic verifications
that epitaxy is proceeding. The quadrupole mass spectrometer is used to
monitor the beam fluxes and the residual gas partial pressures. Finally the
coated substrates are withdrawn through the load-lock system.

4.4 Coating Growth

The general principles that govern the growth of evaporated and
sputtered coatings are discussed in Section 6. MBE creates an environ-
ment in which remarkable control can be exerted over these growth
processes. Table 4, from Reference 26, lists some representative semi-
conductors which have grown by MBE. Most of the detailed studies of
growth kinetics have been done on GaAs. However, sufficient work has
been carried out on other binary compounds such as InAs, InP, and AlAs to
show that similar behavior is observed for most combinations of Al, Ga, and
In with P, As and Sb.35 The essential feature is that at the substrate
temperatures used, the column III elements (Al, Ga, In) have near unity
sticking coefficients on the growing coating surfaces, while the sticking
coefficients of the column V elements (P, As, Sb) are dependent on the
density of column III atoms which are available on the surface to react.
Typicalsubstratetemperaturesare~600”C.TheexcesscolumnVspecies
 Physical Vapor Deposition 361

Table 4: Representative Semiconductors Grown by MBE

(From Reference 26)

Group IV III-V IV-VI II-VI

Silicon Binary Binary Binary

Germanium GaAS PbTe ZnTe
GaP PbS ZnSe
GaSb PbSe CdTe
1IlA.S SnTe CdS
InP
InSb
AlAS
Ternary Ternary Ternary
GaAlAs PbSnTe ZnSeTe
GaAsP PbSnSe CUI&!~
GaAsSb PbSSe
GaInAs
GaInP
GaSbAs

are lost by re-evaporation. Thus, near-stoichiometric coatings can be

grown under a range of deposition conditions, provided that there is an
excess flux of the column V element arriving at the substrate. This type of
growth is described in Section 6.3.
It should be noted that even at the UHV pressures of 1O-lo to 10-l l Torr
used during MBE deposition, doping levels of 10” to 1018 cme3 would
result if all the impurities which are incident on the substrate were incorp-
orated into the film and were electrically active.36 (See Section 2.) Fortun-
ately, the sticking coefficients for residual gases on III-V compounds are
sufficientlylowsothattheelectricallyactiveimpurityconcentrationsarein
the 1014 to 1015 cmT3 range. The main residual impurity in MBE GaAs is
carbon, which appears to be a shallow acceptor with an energy of around
26 meV.27v26Therefore, undoped GaAs films are generally found to be p-
type. The question of residual impurities and their effects is one that
should be considered in evaluating any new MBE materials and/or appli-
cations.
The incorporation of dopants is a key consideration in MBE. Dopant
incorporation is governed largely by reaction kinetics rather than by
equilibrium thermodynamics. 26 Doping levels are typically less than 1Oig
cme3.Many of the dopants which are useful in otherforms of epitaxy do not
behave well with MBE. The actual behavior is strongly dependent on the
substrate temperature and the surface reconstruction which occurs during
growth.26 It is difficult to dope with an element having a high vapor
pressure, since such materials are desorbed prior to incorporation. There-
fore, dopant incorporation is a contemporary research area in MBE. Con-
siderable attention is being given to the use of ion beams.26~30~37‘40 In this
case, the dopant flux is directed at the substrate in the form of an ion beam
with energies in the 0.2 to 1.5 keV range. The kinetic energy of the incident
362 Semiconductor Materials

ions appears to permit them to penetrate into the lattice of the growing
coating to a sufficient degree so that the incorporation probability is
increased.
The complexity of the doping problem is illustrated by the GaAs
technology. Commonly used dopants are Sn, Si, and Ge for n-type and Be
for p-type GaAs.27~*8Tin, which is the most commonly used n-type dopant,
illustrates the complexities that can occur. Surface segregation causes
the Sn to accumulate on the surface in a concentration which is several
ordersof magnitude largerthan that in the bulk.The rateof incorporation is
controlled bythe Sn surfaceconcentration and theGavacancyconcentra-
tion within the GaAs.27 The Sn segregated on the surface precludes the
formation of abrupt changes in doping concentration, since itsconcentra-
tion cannot be reduced to zero by simply closing the shutter at the Sn
source. Anothersource of complexity occurs because many of the dopants
are amphoteric. For example, under As-rich conditions Ge tends to be
incorporated as a donor, while under Ga-stabilized conditions (see Section
6.3) Ge is incorporated predominantly as an acceptor.27 These examples
illustrate how the dopant incorporation is dependent on relative substrate
arrival rates of As and Ge atoms as well as the doping flux itself.
The difficulties in forming p-type GaAs are even more severe. The
conventional acceptor dopants for GaAs such as Zn and Cd have high
vapor pressures and therefore low incorporation coefficients. Beryllium
has shown the most promising p-type doping properties, but isan extreme
toxicity hazard.27 The ion beam technique has been successfully used to
incorporate Zn+and provide carrier concentrations in the 101gcm-3 range.28”7
Manganese has been used but causesadverse surface degradation.27 Ion
beam deposition has also been proven effective in Si MBE.40,41

4.5 Applications
MBE is particularly effective when control overthickness, composition,
and doping profiles are critical to device performance. Such requirements
are often encountered in microwave and optoelectronics devices. These
needs have stimulated the development of MBE technology in general
and GaAs technology in particular. MBE has been used not only to produce
state-of-the-art performance in conventional structures, but also to produce
totally new types of thin film devices. Table 5 lists some devices which
contain epitaxial structures grown by MBE.
GaAsfield effect transistorsare typically used as low-noise microwave
signal detectors and microwave signal generators. Both low noise and
high-powerfield-effect transistors require n-type layers less than 1000 nm
thick Low-noise FET’s have been reported using 100 nm thick, heavily
doped, MBE GaAs layers.27 The linearity of power FETs can be improved
bytailoringthedopingprofile,arequirementthatcan beachievedbyMBE.
Microwavevaractors,mixerdiodes,andIMPATTdiodesareotherexamples
of devices in which controlled doping profiles are required and therefore
where MBE is useful.27
The formation of low-resistance contacts to n- and p-type GaAs, as well
as Schottky barrier diodes on GaAs, is also of great technological importance
 Physical Vapor Deposition 363

Table 5: Devices Whose Epitaxial Structures Have Been Grown by MBE

(From Reference 34)

Discrete microwave devices

LOW noise FETS

Power FETS
Novel FET structures
IMPATT diodes
Mixer diodes
Varactor diodes
Gun diodes

Discrete optoelectronic devices

Laser diodes
Waveguides
Integrated optics
Tnper couplers
Light-emitting diodes
Photodetectors

Other devices

Diodes
MIS capacitors
Superlattices
Tunnel triodes
Solar cells

in microwave and optoelectronic device fabrication. The unique capabili-

ties of MBE are well suited to first growing the epitaxial layer structure
neededfordeviceoperation,andthengrowingtherequiredmetalfilmonto
the freshly deposited semiconductor surface in the same growth cycle
without breaking vacuum. The semiconductorsurface is neverexposed to
the atmosphere or solvents. MBE in situ metallization makes the repro-
ducible production of ideal metal-semiconductor interfaces feasible.2g
This is a particularly important consideration asverysmall circuit dimensions
are contemplated.
The high electron mobility transistor (HEMT) and the multiquantum
well (MQW) laser are examples of novel thin film devices which have been
producedbyMBE.InthecaseoftheHEMTdevice,athinGa,.,AI,Aslayeris
grown in the middle of a GaAs active channel. As a result of the greater
electron affinity of the lower bandgap GaAs, the donor electrons from the
Ga,.,AI,As layer thermalize in the GaAs active layers, where they are no
longer scattered by the ionized parent donors. Such devices can have very
fast switching times (in the 10 ps range).34
The double heterojunction injection lasersconsist essentially of a thin
active layer at the interface of a p-n junction. 34The higher refractive index
of the active layer with respect to the confinement layers forms an optical
waveguide that, with cleaved mirror faces, can define a resonant optical
364 Semiconductor Materials

cavity. The band energies of the active layers are such that the charge
carriers injected under forward bias are trapped in the active region. In
recent work, lasers with unique performance have been fabricated by
making the active layers have the form of quantum well superlattices
consisting of alternate layers of materials with different bandgapsand with
layerthicknesseslessthantheDebyelength.Thus, inoneexample,fourteen
GaAs quantum-well active layers, only -14 nm thick, were sandwiched
between AI,,,Ga,,,,As confinement layers ~13 nm thick.34j36 Injection
MQW laser diodes are of great importance in fiber optics communication
systems, because laser operation can be tailored to emit at frequencies
well above the standard lasing frequencies of the host material, and
therebytocontrol the losses in thefiberoptics. The deposition ofsuperlattice
structures with properties not found in homogeneous materials is an
active area of current research which can be expected to yield a host of
applications in the future.42t43

5. SPUTTERING

5.1 Introduction
Sputtering is a process whereby material is dislodged and ejected
from the surface of a solid or a liquid due to the momentum exchange
associated with surface bombardment by energetic particles. Asource of
coating material called the target is placed into a vacuum chamber along
with thesubstrates, and thechamberisevacuated toapressure typically in
therange5x10-4t05x10-7Torr.The bombardingspeciesaregenerallyions
of a heavy inert gas. Argon is most commonly used. The sputtered material
is ejected primarily in atomic form. The substrates are positioned in front of
the target so that they intercept the flux of sputtered atoms.
The most common method of providing the ion bombardment is to
backfill the evacuated chamber with a working gas in the 1 to 100 mTorr
pressure range and to ignite an electric discharge with the target serving
as the cathode or negative electrode. Such an apparatus configuration is
shown schematically in Figure 19. Applied potentials are typically between
500 and 5OOOV. Direct currents are generally used when the target
material is a good electrical conductor. Radio frequencies are used when
the target material is poorly conducting or an insulator. Deposits of poorly
conducting metallic compounds can also be formed by dc sputtering the
metallic component while injecting other constituents in the gas phase.
This is known as reactive sputtering. A voltage bias may be applied to the
substrates so that they are at a negative potential relative to the plasma
and therefore subject to an ion bombardment that can influence coating
properties. This is known as bias sputtering.
The most striking characteristic of the sputtering process is its uni-
versality. Since the coating material is passed into the vapor phase by a
mechanical (momentum exchange) rather than a chemical or thermal
process, virtually any material is a candidate coating. Films containing
almost every element in the periodic table have been prepared bysputter-
 Next Page

Physical Vapor Deposition 365

CATHODE
WORKING
GAS FEED

TARGET ---t+ GROUND 1

ION FLUX

TO VACUUM
PUMPS

Figure 19: Schematic drawing showing glow discharge sputtering apparatus of

the planar diode type.

ing. Alloys and compounds can generally be sputter-deposited while

preserving their composition. For example, organic bone has been sput-
tered, with the deposits having an amorphous microstructure ratherthan
the crystalline structure of the target material, but an identical composition.44
PTFE (Teflon) has been sputtered to produce films having many of the
properties of the starting material. 45,46However, most applications involve
metalsandmorecommoncompoundssuchasaluminumoxide.Oneofthe
primary applications of sputtering is for interconnect metallization in
integratedcircuits.Otherareasattractingincreasingattentionarefilmsfor
magnetic4’ and optical data storage.48
Aseries of review papers in References49-59 trace the recent develop-
ment of the physics and technology of sputtering.

5.2 Basic Sputtering Mechanisms

In sputterdeposition we are concerned primarily with what is termed
physical, as opposed to chemical, sputtering. In physical sputtering, the
bombarding particle transfers kinetic energy to the target atoms and
incurs the subsequent ejection through the target surface of those atoms
which acquire sufficient kinetic energy to overcome the local binding
forces. In chemical sputtering, chemical reactions induced bythe impinging
particles produce an unstable compound at the target surface, which
subsequently passes into the gas phase. 6oChemical sputtering is particu-
larly important in plasma etching applications. See chapter on plasma
etching.
Diffusion and Ion Implantation in Silicon

Richard B. Fair
Microelectronics Center of North Carolina
Research Triangle Park, NC

INTRODUCTION

As it becomes necessary to achieve higher levels of integration in IC

manufacturing, so too does it become necessary to better understand the
interrelationships among processing steps. Knowledge of the mechanisms
involved in ion implantation and diffusion are basic to obtaining this
understanding.
The focus of this chapter is on impurity diffusion and ion implantation
in silicon. Because of the large solid solubility of Group III and V doping
impurities in silicon, diffusion proceeds by interactions with point defects
in the silicon-vacancies and silicon self-interstitials. Each high temperature
processing step has the potential for changing the number of vacancies
andself-interstitials, and therefore, the properties of impurity diffusion. We
can understand these effects at two levels-the atomic level and the
continuum level. Thus, discussion of diffusion from both points of reference
is provided.
The process of introducing impurities into silicon is called predeposition.
Chemical predeosition is described in terms of a solution to the diffusion
equation and also in terms of ion penetration into silicon, distributions of
implanted impurities, lattice damage, etc. Finally, useful curves for designing
implanted junctions with a single annealing step are provided to assist in
the selection of implant dose, energy and dopant.

455
456 Semiconductor Materials

CONTINUUM THEORY

According to the Continuum Theory of diffusion, matter will flow in a

mannerwhich will decrease all concentration gradients in an inhomogenous
single phase alloy undergoing annealing. The physics governing diffusion
are described in two equations. The first is Fick’s First Law which states
that there will be a flux of atoms whenever a concentration gradient exists,
and that flux is related to a constant that is a fundamental material
property. In one dimension Fick’s First Law becomes’

J, = -D dC (1)
dx

As an example, Figure 1 shows a plot of the concentration of an impurity

distributed in a host lattice as a function of x-the depth into the material.
From Equation 1 the flux of this impurity during diffusion is related to the
concentrationgradient. Figure 1 bshowsthefluxcalculatedat2 points-x,
and xP From Figure 1 c, if Ax is small,

= -*r a-l
JI-J, (2)
ax

The net increase in matter in the volume is

J,-J, = Ax-3c = -Ax-

aJ
(3)
at ax
Differentiating Equation 1 and substituting into Equation 3 gives Fick’s
Second Law:

s
-=- a D-ac
at ax I axI (4)
For the special case where D is constant and the surface concentration of
the impurity that is diffusing is fixed, then Equation 5 results:

a’c
D -=- i)c
(5)
ax2 6r
Fick’sSecondLawisacontinuityequationwhichdescribesthetimerateof
change of the impurity concentration. The diffusion constant D is in units of
cm2/sec. and the concentration C is usually in units of atoms/cm3.

Special Cases
Predeposition. UnderthespecialcasewhereDisconstant,thesurface
concentration of the diffusing impurity is fixed, the concentration of the
impurity at x=m is C( - ,t)=O for all time, and the concentration at any point
inthecrystalatt=OisC(x,O)=O, thenundertheseconditionsthesolutionto
Equation 5 is given as:*
 Diffusion and Ion Implantation 457

Jl

J2

i i
I
I
I I
-I I- (cl
JI I I J2
Ax -t I
Ic

Figure 1: (a) Plot of an assumed concentration as a function of depth, (b) the

flux J(x) for this plot and (c) the element of volume with the flux J1 entering
and J2 leaving.
458 Semiconductor Materials

c (xJ.t)= coerfc -
I =I2JEJ’ (6)

If C( m ,t) = C, and C(x,O) = C,, then

I I
I
c Cx,t)= coelfc - * CR
z&it (7)

where C, is the background doping concentration in the semiconductor.

Thus, for the boundary conditions described above the impurity concen-
tration as a function of space and time is given by a complementary error
function whose argument is x/,/&t The complementary error function is a
tabulated function and is described in Equations 8 and 9. A plot of the
complementary error function if given in Figure 2. If we form the inverse
complementary error function of Equation 6 and set the concentration
equal to the background concentration in the host lattice we can solve for
the depth of a junction with that background concentration. This isgiven by
Equation 10.

10-l

Figure 2: Normalized Gaussian and complementary error function curves.

 Diffusion and Ion Implantation 459

erfc y = l-ClfY (8)

(9)

cB
I:] = 24% erfc-’
II
-
CCI (10)

Example: forC,=5xl 018cm-3 and diffusion of arsenic in silicon at 12Oo”C,

what diffusion time is necessary for the arsenic concentration to decrease
by a factor of 1000 in 5x1 OT5 cm (0.5 microns)?

a) c W = c, erfc (x/a& 1

c (I,&
b) -y-- = lo-’ ; xp& = 2.32 (from Fig. 2)
0

xj3
c) t=- : D = 22x10-” cm2/sec; t = 528.4 UC.
215D

Figure 3 shows the complementary error functions plotted as a function of

time on linear and semilogarithmicscales. It can be seen that the junction
depth increases as the Jr- when the surface concentration is equal to a
constant value.
Diffusion processes that are performed with a constant surface concen-
tration are normally referred to as predeposition steps. Predepositionsare
usually done in N,furnace ambients with a small percentage of O,, and the
doping species is introduced into the furnace in gaseous form. The dopant
concentration in thegas N,stream isvaried tochangethesurfaceconcen-
tration in the silicon. Typical predeposition temperatures are in the 900-
1000°C range, and times are usually 30-60 minutes. There are a wide
variety of sources of dopants including liquids, solids and gases.
Forthe predeposition of boron the most prevalent species in thegas
phase in the furnace is B,O,. Once the B,O, is deposited on the silicon
surface there is a reaction of this oxide with the silicon to produce doping.
This is shown as Equation 11.

w3+ 12 Si z 2B + (11)

The production of B,O, may come from either one of the reactions described
in Equations 12 or 13,

2H3% & BzO3 + 3W

(12)

2BN + 302 - 2B203 + 2N2 (13)

The source of the boron nitride in Equation 13 may be in the form of disks
460 Semiconductor Materials

Figure 3: The complementary error function (erfc): normalized concentration

vs. distance for successivetimes.

about the size of a silicon wafer which are placed next to the wafers in the
diffusion furnace.
By varying the partial pressure of the gas phase of the dopant in the
furnace, it is possible to change the concentration of impurities in the
silicon. Henry’s Law relates the concentration of dopants that are introduced
in the furnace to the surface concentration:

CO= HP, (14)

CO- dopant surface concentration

H - Henry’s cOnstint
pr - partial pressure of dopant gas

Figure 4 shows Henry’s Law plotted. It can be seen that once the solid
solubility of boron in silicon is reached, Henry’s Law no longer applies.
Thus, most predeposition steps operate with a high enough partial pressure
in thedopantgasphasethatsolidsolubilityofthedopantisachievedinthe
silicon. This provides a natural control for reproducible diffusion results.
 Diffusion and Ion Implantation 461

Solid rolubility of
2X1020 ----c-------_--_--
B in Si at 1100%
0’
/
/
I

/
1 /
/
0’
1 -/- Line correspondsto Henry’s law,
with H 12 X ld5 #m/cm3

.V 0 0.5 1
Pt (Torr)
1.5 2XlQ2

Figure 4: Surface concentrations of boron in silicon as a function of the partial

pressure of BzOJ in the ambient at 1100°C.

For the predeposition of phosphorus the predominate species in the

gas phase is P,O,. The doping reaction with P,O, is shown in Equation 15:

Ws + SiO, + 2P . (15)

Sources of P,O, vapor are solid P,O,, red phosphorus, POCI,, PBr,,
NH,H,PO, or PN.
For the predeposition step the goal is to deposit some number of
atoms/cm2 in the silicon substrate, Q(t). The way in which that number is
calculated is to integrate the totalconcentration percubiccentimeterfrom
0 to - as shown in Equation 16.

Q (t) = 1-c (x,t) dx

0

=C, Jo etfc (s/ZJIi;) dx

0

= co
Ipi.I 7r
(16)

Once the predeposition is completed with Q atoms/cm* the next step is to

redistribute the atoms to give the desired junction depth.
Redistribution or Drive-in. If Q atoms/cm* are deposited on the
semiconductor surface with the following boundary conditions:*
462 Semiconductor Materials

c (x,t=o-l = Qs,,,

c (ms) = 0
then the distribution of impurities after diffusion for a time t is given by a
Gaussian function solution to Equation 5:

2
Q
c (x,t) = -jE$ “P
II
$ * (17)

This distribution is shown plotted in Figure 2 on normalized axes. The

Gaussian distribution can be used to describe the impurity profile that
results from a drive-in with no dopant gas in the furnace. The drive-in
step is performed in several typesof ambients: dry oxygen, steam, nitrogen
or argon. The drive-in temperatures range from 900-l 200°C.
Example: arsenic was predeCosited and the resulting Q equals 1 xl 014
cm*. How long would it take to drive-in the arsenic to a junction depth of
1 xl 0m4 cm (one micron) in a background doping of 1 xl 015 cmm3? T =
1200°C.

lXIO1’ 410-4>2
c (1.t) = lxlols = - -
GE erp I 4Dt I

The solution to the equation above must be graphed and is shown where
the left-hand-side of the equation intersects the righthand side of the
equation in Figure 5. Note that if x = 0, the surface concentration C,
decreases as 1/A as shown in Equation 18. The junction depth can be
found by taking the log of both sides of Equation 17:

Q
co
(t)=J;rij; (18)

(19)

Normalized Gaussian concentration profiles versus distance areshown in

Figure 6 for successive times both on linear and semilogarithmic scales.
Under certain conditions the Gaussian solution to the Second Law
can be used in conjunction with short predeposition steps provided that
the following condition applies:

Otherwise, a more complex solution is necessary, and under these condi-

tions the solution is

(20)
 Diffusion and Ion Implantation 463

10-3
3

s
N.-

x
2
u
ii

I,oQ
10-4

lCF6 I I I1111 I I I111111 I I I IlII(

l( 103 104
t (sac)
Figure 5: Graphed solution to the equation cited in the example in the text.

where

The decision as to when the Gaussian solution is appropriate can be

determined by plotting Equation 20 for various ratios of the ,/6i product
for the predeposition and diffusion. These results are shown in Figure 7.

Diffusion Coefficients
Diffusion coefficients are based upon the atomic behavior of the atom
in a host lattice. Diffusion coefficients obey an analytical form as described
in Equation 21.

D = Do CXp (-EAflrT), (21)

464 Semiconductor Materials

1x 105 n

0.6 .-

0.6 -.

0.4 _ Zdiii=O.lr

Figure 6: The Gaussian function: normalized concentration vs. distance for suc-
cessive times.

where D, is the prefactor(cm*/sec), E, is the activation energy in (ev), k is

the Boltzmann constant and T is the temperature (“K). Typical diffusion
coefficients of Group III and V elements in silicon are shown in Table 1.
There is remarkable similarity between the diffusion coefficients of these
elements in silicon. The activation energies for Group III and Group V
elements are in the 3.5 to 4 eV range. A discussion of the origin of these
energies and prefactors is provided in the next section.

Table 1: Diffusion Coefficients of Dopants in Silicon

Impurity P As Sb B Al Ga In

%I 10.5 0.32 5.6 10.5 8 3.6 165

E, 3.69 356 3.95 3.69 3.47 3.5 3.9

 Diffusion and Ion Implantation 465

0.6
~Dt)p,&(Dt)d,ive = 1.0
0.4

Exact

Uncoupled
10-3
3

Figure 7: Comparisons between exact and uncoupled solutions to the drive-in

diffusion equation for several values of Dt (drive-in)/Dt (predep).

ATOMIC THEORY OF DIFFUSION

Diffusion Mechanisms
The atomistic theory of diffusion is concerned with describing how an
atom gets from one part of a crystal to another. The lattice sites in a crystal
aregenerallytakenasthefixedlocationoftheatomsmakingupthecrystal.
It is known that the atoms oscillate around these lattice sites which are
their equilibrium positions. These oscillations lead to finite chances that
an atom will move from its lattice site to another position in the crystal.
There are several ways by which atoms can move from one site in the
crystal to another. These mechanisms are

l the vacancy mechanism

466 Semiconductor Materials

0 the interstitial mechanism

0 the interstitialcy mechanism

These mechanisms are illustrated in Figure 8.

00000 0000
00000 00&O
oo+ 00 0000
00000 (b) Thr interstitial diffusion mechanism.
(a) The vacancydiffusion mechanism.

0000
o@do 0
0000
(c) The interstitialcy mechanism.

Figure 8: illustration of the dominant diffusion mechanisms in silicon.

Thermodynamic considerations require that some of the lattice sites

in the crystal are vacant and that the number of vacant lattice sites
generally is a function of temperature. When a lattice atom moves into an
adjacent vacant site, this process is called thevacancydiffusion mechanism.
In addition to occupying lattice sites, atoms can reside in the space
between the lattice sites. These interstitial atoms can readily move to
adjacent interstitial sites without displacing the lattice atoms. The interstitial
atoms may be impurity atoms oratoms of the host lattice, but in eithercase
they are generally present only in very dilute amounts. These atoms,
however, can be highly mobile and are the dominant diffusion species in
certain cases. A mechanism related to interstitial diffusion is the interstitialcy
mechanism. In this process an interstitial atom moves intoa lattice site by
displacing the atom on that site onto an adjacent interstitial site. Although
several other diffusion mechanisms may exist in semiconductors, in silicon
the three dominant mechanisms are those just described.

The Flux Equation in Diffusivity

The number of atoms which cross a unit area in unit time is known as
theflux.Inonedimensiontheatomsonlymovetotherightorleftwhenthey
 Diffusion and ton implantation 467

change position along the x axis indicated in Figure 9. The atoms in this
simple case are taken to be located in planes at x, and x, + a, as shown in
the figure. The flux J is simply the concentration C times the velocity v:

Jx =cv (22)

The net flux is the difference between the flux to the right and from the left:

where CxOand C,O+a are the concentrations at x= X, and x0 + a, respective-

ly. A factor of l/2 occirs in Equation 23 because at any one plane, half of the
atomsmoveinthe+xdirectionandtheotherhalfmovesinthe-xdirection.
When a, approaches 0,

(24)

and Equation 24 becomes:

(29

x, %+a,
Figure 9: Flux in the x direction through the unit area in unit time. The planes
of the unit area are located at x = x0 and x = x0 + a,.
468 Semiconductor Materials

For motion by discrete jumps between planes a,, apart, the velocity is the
number of jumps per second, lY, times the distance a,, of each jump.
Equation 25 may now be written as

1 dC
J, = --&-,
2 dx (26)

and the quantity (t 2 r) is called the diffusivity or diffusion coefficient D:

1 *2
D=-aa,r
2 (27)

Equation 27 shows that for diffusion by a particular mechanism, calculation

of the diffusivity is reduced to the calculation of the jumpfrequencyl’? The
jump frequency by the vacancy mechanism is

r = X,W

where w is the frequency at which an atom and an adjacent neighboring

vacancyexchange, andX,is theprobabilitythat theadjacentsiteisvacant.
From statistical thermodynamics the vacancy atom fraction is given by
Equation 29, where AS, is the entropy of formation of the vacancy and AH,
is the enthalpy of vacancy formation.

X, = CXP (Asf/k) CXp (--d&/kT) (29)

These terms are related to the Gibbs free energy change for vacancy
formation through the equation

AG, = AH, - TAS, = -kT in Xv_ (30)

It is far more difficult to derive the frequency, w, from fundamental

principles. Nevertheless a discussion of the physics involved in evaluation
w provides useful insights into the quantities that affect diffusion.
In self-diffusion by the vacancy mechanism a lattice atom moves from
a normal lattice site to a vacancy. As shown in Figure 10, the atom must
move from the normal lattice site in 1 Oa to thesaddle point position in 1Ob
to reach the vacancy at 1 Oc. The energy at the saddle point is greater than
at the equilibrium lattice sites, and atoms must be sufficiently activated in
order to move to band then c. The fraction of the lattice atoms activated to
the saddle point is related to the Gibbs free energy change between
positions 1Oa and lob. In the same manner as for the atom fraction of
vacancies, the atom fraction of activated atoms is

%l = CXP (AS,+) CXP (-AH,/LT) (31)

where AS,,, and AH,,, are called the entropy and enthalpy of motion
respectively.
Now, the frequency, w, at which an atom and an adjacent neighboring
vacancy exchange can be written
 Diffusion and Ion Implantation 469

Activated atom

0 0 0
88 0 0 0 88
(a) (c)

Figure 10: The sequence of (a), (b), and (cl show the movement of the atom
from a normal lattice site to an adjacent vacancy. Part (d) shows the variation of
free-energy as the atom moves from (a) to (c).

w=x,y (32)

where the frequency, y, is generally net known and is usually taken as the
lattice vibrational frequency of an atom about its equilibrium site, which is
of the order of 1013/sec-1. Now, from Equations 28,29 and 31 and 32 the
jump frequency for vacancy self-diffusion is

r =y e~p kASf + AS,h] CXp [-(AH, + AH,,,)/LrT]. (33)

Experimentally it is found that diffusivity isgiven by the Arrhenius expression

D = D,, exp (-E&T) (34)

where E, is the activation energy. Thus, the diffusivity is

1
r)=- 2 a: y exp [(AS, + AS,)lk] exp [-fAHf t AH,)/kT] .
(35)

Comparisons of Equations 34 and 35 gives the prefactor D, as

Do = f 4 y exp [(AS, + AS&c] (36)

and

E* = AH, t AH,,, . (37)

470 Semiconductor Materials

From the above discussion it can be seen that diffusivity is basically

the product of the lattice vibration frequency, vacancy concentration and
activated lattice concentration:

D = X, X, y (38)

Also the activation energy for vacancy diffusion depends upon the energy
necessary to form the vacancy and to move the lattice atom into an
adjacent vacancy.

Multiple Charge State Vacancy Model

From the previous discussion it can be seen that the process of
diffusion depends upon the concentration of point defects in the crystal
such as vacancies or self-interstitials. Therefore, if one can find ways of
raising or lowering the point defect concentrations then one can effect
diffusion coefficients.
Forthe vacancy mechanism, the single vacancy in silicon is known to
exist in four charge states: V+, Vx, V-and V=, where+ refers toadonor level,
x a neutral species and - an acceptor leveL3r4 The creation of a vacancy
introduces a new lattice site, and thus four new valence band states in the
crystal. These states are available as acceptors but are not shallow. The
lattice distortion associated with the vacancy will split states from the
valence and conduction. bands of the surrounding atoms a few tenths of an
electron volt into the forbidden gap. States split from the valence band will
becomedonorsandthosefromtheconduction bandwillbecomeacceptors.
At Iowtemperaturesthereshould beonedeepdonorlevel,V+,afewtenths
of an eV above the valence band edge, a single acceptor level, V- near
midgap, and a double donor level V= very near the conduction band edge
(see Figure 1 1).5 The levels depicted in Figure 11 represent a best guess
based on experiment.6-6

1.2- + Si AT 0°K
CB
O.lleV “=
l.O- -f- t
0.44eV

E 0.8-
2 V-
g 0.6-
5
0.4 r

Figure 11: Estimated vacancy energy levels in the silicon band-gap at 0°K.
 Diffusion and Ion Implantation 471

It has been experimentally verified that both silicon self-diffusion and

the diffusion of Groups III and V impurities in silicon depend upon the
Fermi- level position. The initial assumption in the vacancy diffusion model
ofself-diffusion isthatanobserveddiffusivityarisesfrom thesimultaneous
movement of neutral and ionized vacancies. Each charge type vacancy
has a diffusivity whose value depends upon the charge state, and the
relativeconcentrationsofvacanciesdepend upon the Fermi- level.gCalcu-
lated changes in relative concentrations of charge species versus Fermi-
level, E,, are shown in Figure 12a at T=300”K and in Figure 12b at
T=1400”K.5WhereasatlowtemperatureVXwillbethedominantspeciesin
intrinsic silicon, at high temperatures both V+ and V- would be more
numerous. There is no value of Erforwhich V”dominates. Another important
concept is that every time an ionized vacancy is formed the crystal must
return the neutral vacancy population back to equilibrium by generating
an additional vacancy. In this way, as the doping becomes more n-type or
morep-type, thetotalvacancyconcentrationwillincreasewiththeincreasing
population of ionized vacancies. Since impurity and self-diffusion coeffi-
cientsdependupontheconcentrationofvacancies,thediffusioncoefficients
will also increase with doping. Such concentration-dependent diffusion
can occur when the doping level exceeds the intrinsic electron concen-
tration, ni at the diffusion temperature. An illustration of concentration
dependent diffusion is shown in Figure 13.

I- T=14003K
6- 6
I-
4-

0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6

EFW) EY ET(eV) EC

(a) (b)
Figure 12: Calculated changes in the ratios of ionized to neutral vacancies at (a)
300°K and (b) 1400°K.
472 Semiconductor Materials

I l111111
n.I

LOG(n) LLECTRONS/cm3

Figure 13: Donor impurity diffusion coefficient vs.electronconcentration show-

ing regions of intrinsic and extrinsic diffusion.

THE ROLE OF POINT DEFECTS IN SILICON PROCESSING

The Silicon Processing Balancing Act

Silicon oxidation and diffusion of impurities are quite related since
they both occur at high temperatures and they both involve point defects
such as vacancies or self-interstitials. The first level of process design
involves the concept of doping and junction formation, threshold voltage
control, or the gain control of the transistor. Another goal of doping is to
achieve low sheet-resistance. For oxidation the primary goal is to grow
controlledlayersofSiO,.Thingsofconcerninoxidationincludethegrowth
of stable oxideswith electrical integrity, etc. If one iscreating a non-planar
structure it is necessary to worry about the viscous flow characteristics of
the oxide and whether the viscosity is low enough to release stress. The
process engineer in general spends a lot of time dealing with these first
order requirements. However, the rest of the time is spent in trying to
balance things that are generally not well understood. The point defect
balancing act diagram is shown in Figure1 4. All of the arrows in the figure
indicate the directions of interactions. For example diffusion may change
the concentration of point defects, and point defects themselves can
affect diffusion. Oxidation produces point defects and point defects can
affect oxidation. The balancing act involves point defect generation and
the effect of this generation on these major processes. Diffusion may
introduce strain into the lattice which can affect surface quality. Oxidation
 Diffusion and Ion Implantation 473

Figure 14: The point defect balancing act in silicon processing.

can influence surface bonding which also affects surface quality. As these
processes produce point defects it is possible that extended structural
defects can grow in the silicon. Point defects can also influence the
precipitation of oxygen. Oxygen is incorporated into the crystal during
crystal growth, and precipitates during subsequent heat treatments. It is
known that these precipitates create good internal gettering sites for
metal impurities with subsequent impact on junction quality.

Point Defects
Point defects are defined as atomic defects. There are atomic defects
such as metal ions which can diffuse through the lattice as shown without
involving themselves with lattice atoms or vacancies. Another type of
atomic defect is the self-interstitial which in silicon is a silicon atom that is
bonded in a tetrahedral interstitial site. Examples of point defects are
shown in Figure 15.
One of the major controversies in solid state science currently is: what
is the dominant native point defect in silicon - the monovacancy or the
silicon self-intersitial? A brief review of the arguments for each species is
given below

The Monovacancy
From statistical thermodynamics, it is known that if avacancyisformed
by removing an atom from the crystal and depositing it on the surface, the
freeenergyofthecrystalwilldecreaseasthenumberofvacanciescreated
increases until a minimum in this free energy occurs. Because a minimum
inthefreeenergyoccursforacertainvacancyconcentrationinthecrystal,
the vacancy is a stable point defect. Other experimental observations
involving vacancies are listed below:‘O

1. Electron paramagnetic resonance measurements only iden-

tify the existence of vacancies or vacancy complexes in Si
irradiated by electrons. The absense of Si self-interstitials
has been ascribed to rapid athermal migration even at
2°K.”
474 Semiconductor Materials

2. Diffusion phenomena as well as calculations of diffusion

entropy and enthalpy have been successfully explained by
ascribing multiple ionization levels to vacancies which are
the same as those observed for the vacancy in a low-
temperature irradiation experiment.12-l4
3. Theoretical estimates of the heats of formation and entropies
of formation of vacanciescorrespond well with those of the
native defects observed in diffusion and quenching experi-
ments.l3,15-17

4. Channeling studies of impurity-defect interactions in Si

show that under helium ion bombardment the trapping
efficiency of impurities for radiation-produced defects is
very low near 30”K.j7 Vacancies are not mobile in Si below
this temperature while interstitialsstill are.This implies that
the impurity-defect interactions involve vacancies.
5. Positron annihilation lifetime measurements which have
been performed on float-zone Si at high temperatures,
show that vacancy-like defects are formed.la

Foreign interstitial etomf

Ce, Ni, Fe, Li, H

Self-interstitial I

I
Substitution81 dopents

B,Al, 08 ; P, As, Sb

P-

Figure 15: Examples of point defects in the silicon lattice.

 Diffusion and Ion Implantation 475

The Silicon Self-Interstitial Atom

It is possible to perform a similarconsistent statistical thermodynamic
analysis on the existence of self-interstitials and show that they are stable
point defects. Other arguments in support of thesilicon self-interstitialare:

1. The great majority of dislocation loops and stacking faults

in Si observed by transmission electron microscopy are
judged to be of extrinsic or “interstitial” character. Though
there exist four proposed mechanisms by which extrinsic
type dislocations may be formed without any self-interstitials
being present,‘O most workers feel that self-interstitial pre-
cipitation is the dominant mechanism.
2. The picture of self-interstitials in Si developed by Seeger
and FranklQ is consistent with observations indicating self-
interstitial migration at low and high temperatures.
3. Evidence for the liquid drop character of B-swirl defects in
Si comes from the observation that upon melting, droplets
of liquid Si are formed in the interior of the solid phase.20
4. In n-pstructuresformed bysequentialdiffusionsof Band P,
dislocation climb was observed to have occurred at the
same time that the emitter-push effect was seen in the B
layer.*’ This result implies that the same point defect is
responsible for both phenomena.
5. Stacking fault growth P diffusions and enhanced buried
layer diffusion have been observed to occur simultaneously.**
6. Total energy calculations show that self-interstitials form
and migrate in Si with a total activation energy roughly the
same as that of self-diffusion.23

After reviewing the balance sheet of pros and cons surrounding the
question of the native defect in Si, one isstill left with the question: what is
the native defect responsible for impurity diffusion and defect growth in
Si? So far we only have clues. However, the majority opinion currently is
that both types of point defects are important. Thermal equilibrium concen-
trations of point defects at the melting point are ordersof magnitude lower
in Si than in metals. Therefore, a direct determination of their nature by
Simmons-Balluffi type experiments24 has not been possible.The accuracy
of calculated formation and migration enthalpies appears to be within +
1 eV but do not help to distinguish whether vacancies or interstitials are
dominant in diffusion. The interpretation of low temperature experiments
on the migration of irradiation-induced point defects is complicated by the
occurrence of radiation-induced migration of self-interstitials.25*26 In addition,
thereareindicationsthatthestructureandpropertiesof pointdefectsmay
change from low to high temperatures. 27The observation of extrinsic type
dislocation loops in dislocation-free, float zcne Si showed that self-inter-
stitials must have been present in appreciable concentrations at high
temperature during or after crystal growth.28~2Q However, it is unclear
476 Semiconductor Materials

whether these self-interstitials were present in thermal equilibrium or

were introduced during crystal growth by non-equilibrium processes.
In view of the uncertainties regarding the native point defect in Si, it is
necessary in discussions of self and dopant diffusion to take account of
both types of defects.

Point Defect Models of Diffusion in Silicon

Underthermalequilibriumconditions,aSicrystalwillcontainacertain
equilibrium concentration of vacancies, C.,,, and a certain equilibrium
concentration of Si self-interstitials, C,. In dtffusion models based on the
vacancy, CvG, and dopant as well as self diffusion can be explained as13

D, = Df + D; C D,= + D; (39)

where Di is the measured diffusivity and DiX, D!-, Di= and Di+
are the intrinsic diffusivities of the species through Interactions with
vacancies in the neutral, single acceptor, double acceptor ordonorcharge
states respectively. These individual contributions to the total measured
diffusivity were described in a previous section.
Analogous to the vacancy model, Si self-interstitials can be assumed
to be dominant such that C,>>C,. For such a model, dopant and self-diffusion
are assumed to occurviaan interstitialcy mechanism.30 Mobile complexes
consisting of self-interstitials in various charge states and impurities are
assumed to exist.
In principle, both vacancies and self-interstitials may occur simulta-
neously, and somewhat independently. Indeed, any relationship that may
exist between Cvand C, may be dominated by the Si surface which can act
asasourceorsinkforeitherspecies. If alocaldynamicalequilibriumexists
between recombination and spontaneous bulkgeneration, vacancies and
self-interstitials would react according to

V+IZ 0, (40)

where 0 denotes the undisturbed lattice. The law of mass action under
equilibrium for this reaction is

c, cv = cp cc. (41)

For sufficiently long times and high temperatures Equation 41 turnsout to

befulfilled.31~32 However, it has been reported that asubstantial amount of
time may be required for dynamical equilibrium to occur.32 This would
make vacancy/self-interstitial recombination an activated process. In
addition, under point-defect injection conditions, Equation 41 may no
longer be valid.
If both types of point defects are important, diffusion processes may
involve both types:

Di = D/ + Dt”e (42)
 Diffusion and ton Implantation 477

where Di’ is the interstitialcy contribution and D; is the vacancy contribution

to the total measured diffusivity, Dr One way in which vacancies and self-
interstitials could cooperate in affecting impurity diffusion is the Watkins
replacement mechanism34 shown in Figure 16. Interstitial dopant impurities
can be created by the exchange between a self-interstitial and a substitu-
tional dopant atom. The newly created interstitial impurity would migrate
until it finds a vacancy. Then, it is free to diffuse again as a substitutional
impurity.
It is evident now that both vacancies and self-interstitials can exist in
equilibrium with each other in the silicon lattice. Each species can be
decribed by equilibrium equations of the type:

c = cup [s;n] cxp [-AH;~T] (43a)

cp = e~p [s$k] ~XP [-AH$~T) (43b)

For silicon self-diffusion, the total diffusion coefficient could be expressed

as

Dsl = f, D, c + f, D, C; (44)

where.f:, and fi are the fractional contributions of vacancies and self-

interstmals to self-diffusion. There currently is substantial debate as to
what the values of these fractional coefficients are. A diagram of the
spectrum of the debate currently underway in the literature is shown in
Figure 17. The concept that impurity diffusion was dominated by vacancies
onlywas helduntil 1968whenSeegerandChi~k~~proposedthatbothself-
interstitials and vacancies could contribute to diffusion in silicon. However,
the concept of vacancies and interstitials coexisting in silicon leads to
several unresolved questions such as-is there dynamic equilibrium between
self-interstitials and vacancies and what is the time required to establish
this dynamic equilibrium?

Experimental Observations
In order to understand whether vacancies or self-interstitials are

000000
op3 0
000000
Figure 16: A schematic diagram of the Watkin’s Replacement Mechanism.
478 Semiconductor Materials

Questions:
0 I+v~o
0 c,cv = cpc;
l Time to equilibrium?
In D

Figure 17: A diagram of the spectrum of the vacancy vs. self-interstitial debate.

involved in diffusion, there are numerous indirect observations that we

must rely upon. A partial list of these types of experiments isshown in Table
2.
For example, during oxidation, enhanced diffusion of phosphorus, boron
and arsenic are observed as well as retarded diffusion of antimony. However,
if direct nitridization of the silicon surface occurs, the inverse effects are
observed, i.e. enhanced antimony diffusion and retarded phosphorus
diffusion. There also is a doping dependence associated with oxidation-
enhanced diffusion. As either p or n-type doping concentration increases
above n, the effect of oxidation-enhanced diffusion diminishes. If chlorine
is introduced into the oxidizing ambient oxidation enhanced diffusion is
likewise diminished.
Not only is enhanced impurity diffusion observed during oxidation but
also increased stacking fault growth. A stacking fault is a plane of dislocated
material that may intersect the silicon surface but which also has a
bounding partial dislocation. These faults grow if sufficient numbers of
self-interstitials aregenerated such that theconcentration of self-interstitials
in the lattice is higher than the concentration of self-interstitials on the
bounding partial dislocation core. This process is illustrated in Figure 18.
Since oxidation is a process that generates excess self-interstitials, stacking
faults grow during oxidation.
 Diffusion and Ion Implantation 479

Table 2

Which Model is Ooeratinn in Silicon?

For insight we need indirect observations from numerous
di5erent experiments
. Oxidation - enhanced/retarded diffusion
- backside oxidation
- role of Si3N, surface films
- retarded diffusion of Sb
- doping dependence of OEIYORD
- effect of chlorine
- CL versus FL Si

a Doping effect on OSF shrinkage

l E5ect of diffusion on 0 precipitation

l &diffusion studics
.e TEhI rtudies of precipitates/defects
l C, vs. n in doped layer
. Profile !&deling
l Role of stress
. Doping dependence of oxidation

Other experiments that have been performed include irradiating uni-

formly doped silcion wafers with protons and observing the diffusion of the
dopant after irradiation has occurred. Additional discussion of these effects
will follow.

DIFFUSION IN THE PRESENCE OF EXCESS POINT DEFECTS

Oxidation-Enhanced Diffusion
As it was mentioned in the above discussion, oxidation generally
enhances the diffusion of Group III and Group V elements except for
antimony. These results are summarized in the Figure 19. In this figure
oxidation- enhanced diffusion is generally observed by depositing a silicon
nitride mask on the silicon surface which will prohibit oxidation in the
regions that it covers. Then oxidation is performed in a window opened to
the silicon surface, so that differential changes in junction depth can be
observed. In orderto explain these results, HUESproposed a model whose
essential points are:

1. Oxidation of Si at theSi/SiO, interface is usually incomplete

to the extent that approximately 1 Si atom in 1000 is
unreacted.
480 Semiconductor Materials

PARTIAL
/+ DISLOCATION

Figure 18: A model of self-interstitial diffusion from the bulk to the partial dis-
location bounding a stacking fault. Under non-oxidizing conditions the concen-
tration of self-interstitials at the fault line, Cr L, is greater than the equilibrium
bulk interstitial concentration, Cr 0. Under oxidizing conditions, Cr is greater
than CrL until the retrogrowth temperature is reached.

Figure 19: Experiments that illustrate oxidation-enhanced and oxidation-re-

tarded diffusion of dopants in silicon. The supersaturation of self-interstitials
associated with the oxidation process drives both effects.
 Diffusion and Ion Implantation 481

2. The unreacted Si becomes mobile, severed from the lattice

by the advancing Si/SiO, interface. These atoms enter the
Si lattice interstices, causing a flux of self-interstitials away
from the interface.
3. Growth of oxidation-inducedstackingfaultswill proceed by
the absorption of the generated self-interstitials. Oxidation-
enhanced diffusion can occur as a result of the presence of
the excess interstitials via the Watkins34 replacement
mechanism or by an interstitialcy process.

If the Watkins replacement mechanism is ignored, the diffusivity of an

impurityatom underconditionsof non-equilibrium point defectconcentra-
tions is
D = D$C,/@ t D;tC,/C;), (6)

where C, and Cv are the non-equilibrium self-interstitial and vacancy

concentrations. Defining the fractional interstitialcy factor as32

fi _ D!/DY
I 1 (46)

we can write

DIDi = fitCI/CD + cl-f&K;,, (47)

Calculations of the fractional interstitialcy components for B, P, As and Sb

are shown in Table 3.31937,38-40 A significant spread in the values of fi is
obtained. The value off! has been correlated with the amount of energy
required to make asubstltutional dopant atom become interstitial. Interstitial
formation energies in Si areshown in Table 4. Thus, the larger the interstitial
formation energy the smaller is the fractional interstitialcy component of
diffusion.
It is observed that the diffusion of Sb is retarded during oxidation of the
Sisurface.31 Thiscan be explained byassuming Sbdiffusespredominantly
by a vacancy mechanism, and the self-interstitials generated at the oxidizing
surface combina .vith vacancies to reduce their concentration. Recent
data from nitridation experimentssuggest that fifor P isgreaterthan0.7.41

Table 3: Fractional lnterstitialcy Components of Diffusion Via

Self-lnterstitials in Silicon at lOOO’-1100°C

<-_---------___ fi I D!/D: ---__ >

1 1
Element Fair [37] Antoniadis [32] Matsumoto [39] Gceelc [38] Mathiot [40]

B 0.17 0.32 0.41 0.8-1.0 0.18

Al 0.2 0.6-0.7

P 0.12 0.40 0.35-0.5 0.5-1.0 0.19

AI 0.09 0.43 0.45-0.7s 0.2-0.5 0.16

Sb 0.13 0.15 0.02

482 Semiconductor Materials

Table 4: Estimated Interstitial Formation Energies in Silicon

Element Interstitial Formation Energy

s 2.2tv
A?+ 2.21
B 2.26
P 2.4
As 25

Experiments that use the backside of the silicon wafer to inject self-
interstitials and thus observe diffusion on the frontside of the wafer are
illustrated in Figure 20.42j43On the wafersurface, films of Si,N, orSi,N, on
SiO, are deposited over previously diffused layers. On the backside a
windowisopenedwhosedistancefromthefrontsidesurfacecan bevaried
by etching. It can be seen in the figure that the backside oxidation can, in
fact, influence the diffusion of dopantson thefrontsidesurface.Theratioof
the junction depth under the oxidized portion to the non-oxidized portion
versus distance from the backside oxidizing surface is shown in Figure 21
for boron-phospohorus and antimony. These results were obtained in float
zone (FZ) silicon with no oxygen incorporated in the silicon. It can be seen
that self-interstitial diffusion lengths of the order of 200-300 microns were
obtained. These backside oxidation experiments show:

1. Oxidation-enhanced diffusion of B and P and oxidation-

retarded duffusion of Sb involve the same point defects
generated by an oxidizing Si surface.
2. The diffusion length of these point defects increases with
diffusion time in FZ Si.
3. Long-range(>lOO pm) oxidation enhanced/retarded diffu-
sion does not occur in Czochralski Si (CZ Si).
4. A S&N, layer on the Si surface is not asinkfor point defects.

Doping Dependence of Oxidation-Enhanced Diffusion

Tanaguchi et al44 found that oxidation-enhanced diffusion decreases
as the concentration of the diffusing impurity increases beyond the point
where concentration-dependent diffusion occurs. This effect was explained
in terms of the reduction of oxidation produced self-interstitials by recom-
bination with the increasing supply of vacancies. Fair45 assumed that the
equilibrium vacancy concentration is unaffected initially by the self-inter-
stitials generated at the oxidizing surface. But, the quasi steady-state
value of interstitial supersaturation is inversely proportional to the vacancy
concentration which increases with doping above nr The oxidation enhanced
dopant diffusivity, D, is then

De = D,, +AD, (48)

-DiCC,/C~) + Di fi (C,/Cp>i(C~/C~),
 Diffusion and Ion Implantation 483

BN-arra BOsrea

‘JBN ‘JBO

Figure 20: Experiments illustrating the use of the backside of the silicon wafer
to inject self-interstitials in order to observe diffusion on the frontside of the
wafer (after Mizuo).

where(C,/C,“)i is theself-interstitialsupersaturation underintrinsicdoping

conditions, and Cv/Cvo is the vacancy enhancement that occurs when
doping exceeds nr This equation is divided into the contributions to
substitutional impurity diffusion under non-oxidizing conditions, D,,, and
theenhancedcontributionduetooxidation,AD,.ThedataofTanaguchiet
al44 are shown in Figure 22 for oxidation-enhanced diffusion of P and B
versus the total number of dopant impurities per cm2, Q, The calculated
values of D,, and AD, are shown in comparison with the data. Reasonable
agreement is obtained. Thus Tanaguchi’s model of self-interstitial recom-
bination with vacancies is consistent with the high concentration diffusion
models of B and P used by Fair in his calculations.

Effect of Chlorine on Oxidation-Enhanced Diffusion

If chlorine is added to oxygen in the furnace in sufficient concentrations
such that stacking fault retrogrowth occurs,46 oxidation-enhanced diffusion
will become negligible.47This result is believed to bedue tothegeneration
484 Semiconductor Materials

Figure 21: The ratio of the junction depth under the oxidized portion to the
non-oxidized portion of the wafer vs. distance from the backside oxidizing
surface.

TOlL IMPURITV OOPING, QT(tm-9

’ +--A 00 CALCULAlEO
. .
DATA FROM TANIGUCHI tlal
hl-_

Figure 22: Measured and calculated values of boron and phosphorus diffusivity
as a function of total impurity doping. Data are divided into contributions to
substitutional impurity diffusion under non-oxidizing conditions, Dsl and the
enhanced contribution due to oxidation ADO.
 Diffusion and Ion Implantation 485

of vacancies at this SVSiO, interface when Cl reacts with Si atoms on lattice

sites to produce SiCl by the reaction

Si + W3~-6iCl tV. (49)

The vacancy generated is then available to recombine with a Si self-

interstitial produced by oxidation:

1 +v -0. (50)

As a result, the supersaturation of self-interstitials in the silicon surface

and the bulk is reduced or eliminated, inhibiting stacking fault growth and
enhanced diffusion. This effect is diagrammed in Figure 23. The effect of
adding HCI to 0, on stacking fault length after oxidation of silicon isshown
in Figure 24.

CHARACTERISTICS OF SILICON SELF-DIFFUSION

In order to satisfactorily explain the self-diffusion of silicon, one must

reconcile the experimental results obtained by three techniques in three
temperature ranges:

1. high temperature radio-tracer measurements

2. precipitation in quenchedcrystalsat temperatures less than
850°C

(HCIoxidation)

-
A {- OSF shrink

Figure 23: Diagram of SiCl formation during oxidation with the subsequent in-
jection of vacancies. The vacancy injection reduces the concentration of self-
interstitials in the bulk and causes oxidation stacking faults to shrink.
486 Semiconductor Materials

1 I I I I lllll I I I IllIll
10-l 100 10
PERCENT HCI IN 02

Figure 24: The effect of adding HCI to O2 on stacking fault length after oxida-
tion of silicon.

3. electron paramagnetic resonance measurements during

the low temperature annealing (100°K) of radiation-induced
defects.

Silicon self-diffusion data over the range 850 to 1380°C are shown in
Figure 25.35,48,4gThe high temperature data show an activation energy of
5.02 eV while the lower temperature show a 4.25 eV energy. Watkins and
Corbett50reportedanactivationenergyforselfdiffusioninSiof3.9eV.This
result was obtained from low temperature annealing of E-centers, impurity-
vacancy pairs at 100” K. The cause for the continual decrease in activation
energy with decreasing temperture has been ascribed to different charge
state vacancies dominating self-diffusion in the various temperature
ranges.13~51~52ThusatverylowtemperaturesneutraIvacanciesmaydominate
self-diffusion. At high temperatures, both donor and acceptor vacancy
diffusion was considered important. An alternate view was expressed by
Seeger and Chik35 who suggested that in Si at low temperatures, self-
diffusion mainly occurs via vacancies, whereas at high temperatures it is
dominated by the interstitialcy mechanism. Their observations indicate a
change in theself diffusion mechanism and/or in theentropyand enthalpy
of self diffusion as a function of temperature. The change in entropy with
temperature can be accounted for by assuming that the form of the self-
interstitial changes with temperature. For example, the entropy would
increase due to a spreading out of the self-interstitial over several atomic
volumes.
 Diffusion and Ion Implantation 487

TEMPERATURE
(‘C)
10-12 1300 1200 1100 1000 900

10-13

CALCULATED
(As-DOPED
TO8~1O~~,nr-~)
10-l’

10-15

2 1o-16 CALCULATED
(B-DOPEDTO
Z 2.5~10~~~11t’~
)-QSi=4.78CV
cy‘
E 10’17
.-
k?
10-18 . INTRINSICSi (HETTICH,

Ni IN INTRINSIC Si(SEEGER
6 CHIK)
B-DOPED Si (HETTICH, etaI)
10-20 A As-DOPED Si(FAIRFIELD 8 MASTERS)
. P-DOPED Si(SANDERS 8 DOBSON)

INTRINSIC Si (KALINOWSKI, etal)

1o-21 q

6 7 8 9 10 11

lO’/T (‘K-l)

Figure 25: Selfdiffusion data in intrinsic and heavily doped n and p-typesilicon.

The self-diffusion data in Figure 25 shows that Si diffusion is different

in heavily doped n-typeorp-typesilicon. In ordertosee howthecontributions
from vacancies in various ionization states can describe this effect, we will
write the intrinsic self-diffusion coefficient as

Di, _ WI Do + 5 D- + [v7, Do + Iv’], D+

St
2nH ” 2q3 ” 2nH ” 2nH ”’ (51)

where D, is the vacancy diffusivity, nH is the number of sites in the crystal,

and [yi is the intrinsicvacancyconcentration. In extrinsicsilicon wherethe
488 Semiconductor Materials

doping concentrations exceed the intrinsic electron concentration, nil

mass action effects cause changes in ionized vacancy concentrations as
shown in Figure 12. These curves obey the relations

[V-l n iv+&
-=-=-
[v-lj ni IV+] * (52)

Using the relation Dsi = 1/(2n,)D,[V), where the one-half term is the
correlation factor for the diamond lattice and nH is the number of lattice
sites, the Si self diffusion coefficient becomes

(53)

Thecalculatedcurvesshown in Figure25 use Equation 53 with thefol-

lowing intrinsic diffusion coefficients

D; = 0.015 exp (-3.89eV/kT), (S4a)

D, = 16 cxp (-rtJ?eV/kT). (S4b)

D; = 1180 exp (-S.O9eV/kT). WC)

The expression for Dsi= cannot be obtained by analyzing the data in Figure
25. The values of the activation energies for each term are consistent with
theformationenthalpies, migration enthalpiesandaveragefreeionization
energies associated with each vacancy.53 Thus, at temperatures below
600°C Equation 53 predicts that C?siapproaches 3.89eV as the neutral
vacancy dominates self-diffusion. This agrees with the low temperature
value observed by Watkins and Corbett.50

DOPANT DIFFUSION IN SILICON

Group III and V elements as solutes in Si are unique in their ability to

formstrongcovalentbondswiththelatticeatoms.Theresultistheyexhibit
very high substitutional solubilities in Si. An important consequence of this
is that it has led people to believe that these elements diffuse predominatntly
via vacancies of self-interstitials. Thus, one would expect similar activation
energies and pre-exponential factors for Group III or V elements in Si and
for Si self-diffusion. In fact, both the pre-exponential factors and the
activation energies of impurity diffusion are lower by a significant amount.
Toexplain this phenomenon usingthevacancymechanism asan example,
HIJ~~ has proposed that there must exist a long-range vacancy-impurity
interaction potential which would cause impurity-point defect pairing to
occur. Thus, the vacancy and the impurity atom would diffuse as a pair and
the additional energy requiredforcomplete dissociation would not have to
be supplied. If no pairing occurred, the vacancy would have to disappear
 Diffusion and Ion implantation 489

into the lattice, and thiswould be the rate controlling mechanism as it is for
self-diffusion. Therefore, the difference between the activation energy for
self-diffusion and Group III or V impurity diffusion is less than the impurity-
vacancy pair binding energy, E,. This is illustrated in Figure 28 where a
particular long-range interaction potential is assumed. The potential energy
between a vacancy at a third coordination site and one infinitely removed
from the impurity atom is AQ. Thus the activation energy for impurity
diffusion, Q,, is proposed to be

QI - Qsi - AQ. (55)

Equation 55 is based upon an impurity displacement cyclewhich sees

thevacancyfirst partiallydissociatefrom the impurityatom,andgoat least
as far as the third coordination site to close a path around the impurity
atom. If the long-range interaction potential is assumed to be Coulombic,
this complements the multiple charge state vacancy model where the
diffusion of donor atoms is dominated by acceptor type vacancies, etc.
Experimental evidence exists in support of coupled point defect-
impurity diffusion in Si. For such a model, chemical pumping effects
involving vacancies or self-interstitials would be negligibly small. Thus, for
a system such as Si where the diffusivity of the solute differs considerably
from that of the solvent, avacacnyor self-interstitial flux will be induced by
the solute fluxes.55 According to the chemical pump model, the influx of a
fast diffusing impurity such as P or B in Si will cause an eflux of lattice
vacancies or a flux of self-interstitials in the same direction as the solute
atoms. However, it is observed that buriedclumpsof Bor Papproximately
microns from the Si surface will undergo isotropic enhanced diffusion
(uniform broadening towards the surface and into the bulk) during the

\
1
012345678
VACANCY SITE ON COORDINATION
SHELL ABOUT THE IMPURITY
Figure 26: A schematic diagram showing a long range vacancy-impurity interac-
tion potential which could account for the lower activation energy of impurity
diffusion compared with selfdiffusion in silicon.
490 Semiconductor Materials

diffusion of a high P concentration at the surface. If a chemical pumping

effect were important, one would expect a buried clump of impurities to be
skewed in one direction or the other depending upon whether vacancies
or self-interstitials were dominant. This is not observed. This experiment is
diagrammed in Figure 27.
Other types of experiments such as proton-enhanced diffusion have
been used to support the notion of coupled impurity- point defects in pair
diffusion. For example, consider a uniformly doped sample that is irradiated
with high energy protons (see Figure 28a). The production of vacancies
and self-interstitials occurs mainly in a region near the average projected
range of the protons, R,(see Figure 28b). These point defects diffuse into
the bulk and towards the surface. This in turn produces a non-uniform
redistribution of the dopant atoms in the Si as shown in Figure 28~~~ The
initially uniform B or P doping shows a dip centered at R between two
smaller peaks. Thus the dopant atoms diffuse in the same &ection as the
diffusing point defects.
Two known mechanisms can account for these results. Either the
dopant atoms respond to the chemical pumping of aself-interstitial flux, or
they become tightly bound to either type of point defect and diffuse as a

7, (INTERSTITIAL

--I--- fLUX)
-t_ ‘Si
I
C F’B

X
Figure 27: A schematic diagram showing the expected redistribution of a buried
layer under the influence of a flux of self-interstitials chemically pumped from
the surface by a phosphorus diffusion.
 Diffusion and Ion Implantation 491

(c)

Figure 28: Protonenhanced diffusion experiments supporting the notion of

coupled impurity-point defect pair diffusion in silicon. (a) initial distribution of
dopant in silicon, (b) production rate of vacancies and self-interstitials due to
proton irradiation, (c) dopant concentration after irradiation.

dopant atom-point defect pair.37 From our previous discussion the chemical
pumping effect is unlikely. Thus the question remains: which type of point
defect ismorelikelytopairupwiththedopantatoms?Theanswerappears
to depend in an unpredictable way on the type of dopant atom. For that
reason, the following sections will describe what is known about each of
the important dopants in Si.

Arsenic Diffusion Models

Arsenic is believed to diffuse primarily via a vacancy mechanism. In
this section the current understanding of As diffusion via a vacancy
mechanism will be reviewed. The characteristics of As diffusion as inter-
preted by this model are summarized inTable 5. The entropy of diffusion of
the As+V- pair is much larger than the entropy of the As+90VX pair-l3 So, in
spite of the larger activation energy (Q,,=4.05eV and Q,,=3.44eV), the
As? pair dominates As diffusion above lO5o”C, as shown in Figure 29.
DiffusionofAs+Wpairsislessimportantthanin thecaseof P.Thisisdueto
a smaller pair binding energy (1.37eV). In an oxidizing ambient little
492 Semiconductor Materials

Table 5: Characteristics of Arsenic Diffusion

(Vacancy Model Interpretation)

Property Result

AS,- > > AS; As+v- pair diffusion dominates

at T > 1050%
As%= binding energy ip Fewer As%= pairs than P+V=
‘0.25 eV less than P’V’ a. Less gettering of metal donors
b. No emitter push above 700%
c. No effect on [Oil precipiration
V& pair binding energy 1. Significant [VAsJ form at
= 1.6 eV n( = 2x1020cm-3 at 1OOOYI
2. Reduces n solubility
3. Causes retarded base diffusion
insomecases
2.5 eV required to make Ar Little oxidation-enhanced diffusion
interstitial

enhanced diffusion of As occurs because 2.5eV (Table 5) is required to

create an As interstitial atom. Thus diffusion continues to be controlled
primarily by the local vacancy concentration rather than by the Si self-
interstitial supersaturation created by the oxidizing surface.
It can be seen in Figure 29 that As diffusivity can be enhanced when
diffusion occurs in heavily doped n-type Si. This concentration dependence
isfurtherdescribedinFigure30whereD,,versusAsconcentrationcurves
are plotted. The implication of such a concentration dependence is shown
in Figure 31. The As impurity profile no longer is described by an erfc
solution to the continuity equation for diffusion. An approximation to this
solution will be given in a later section.
Another feature of the As profile in Figure 31 is that the total As curve
deviates from the measured free electron concentration curve. It has been
proposed that this discrepancy is due to Asclustering at high temperatures.57
Thus, much of the study of As diffusion in Si has centered around the
clustering phenomenon. The most recent contribution by Guerrero, et a15*
suggeststhat clustering involves Asatomsalongwith one negativecharge
(electron or V-). This result was obtained by fitting various models to room
temperature free-electron concentration versus total As data such as that
shown in Figure 32. The functional dependence of n on C, (total As
concentration) depends upon the source of As (implantation or diffusion)
and temperature. Other authors have tried to fit similar data with calculations
and have arrived at different conclusions regarding the chemical and
electrical form of the As cluster.
 Diffusion and ion Implantation 493

TEMPERATURE ("C)

lo-l2 ARSENIC

'\A EXTRINSICDATA

IO-l3

u
,”
2
E
”

z o GHOSTAGORE

10-15 . MASTERSAND FAlRfl

. AODA
A FAIR AND TSAI
o BALD0 et al.
lo-l6 m WEBER et al.
x CHAN AND MAI

10-17

;
10-18I
6 6.5 7 7.5 8 8.5 9

Figure 29: Arsenic diffusivitiesin intrinsicand extrinsic n-type silicon.

The clustering reaction can act to reduce As diffusion. Consider one

model in which the As cluster is a vacancy with two As atoms-VAs,.57 The
reaction is

V= + 2As+ = VAs,. (56)

Then, the total As concentration is

c, = c, + CVh + cvh- + CVh2 I

(57)
494 Semiconductor Materials

10-11,

E . 1ooo’c
0 02

{ ’ N2
A N2
10500 A 02
10-12 C0 WET 02
1lOOC 0 02
t

10-15, i ! I jI/i 1 I !illlll ( 1 ;Iji!j

1013 1019 1020 1021
C(cm-3)

Figure 30: Arsenic diffusivity vs. total arsenic concentration. The solid curves
are calculated. The data represent diffusions in various furnace ambients.

where the formation of V-As+ and WAS+ pairs are included. By writing
down the equilibrium reactionsfortheformation of eachspecies in Equation
57 and setting C,, = n, then C, becomes

c, = n + K,(Th2+ K&Th3 + K&T)n', (58)

where K(T)‘s are the equilibrium constants Equation ,58 can be used to
describe the data in Figure 32.
 Diffusion and ion Implantation 495

The effective diffusion coefficient of As is defined as

Dh e -J tac+X*, (59)

which is Fick’s First Law. If J is the flux of monatomic As, C,,, with a linear
concentration-dependent diffusivity, then

CA, ecA5
J = -Di - -
ni ax (60)

(61)

Substituting Equation 58 and solving for D,, yields

Di (nh$
DA =
4K&Th3
1+ (62)
1 + 3K&Tb2

102’ c

F
9oo"c
2020 MIN.
.-CT

DEPTH(Nm)

Figure 31: Total arsenic CT and free electron profiles in silicon following an
arsenic diffusion.
496 Semiconductor Materials

: IMPLANTED~DIFFUSED LlMIT(1050 cj
uE
-Z CHEMICAL SOURCE

10::

lx1016cm.3 (1050 Cj

I I I lllll I I111111
102” lo’!
CT (cm”)

Figure 32: Electron concentration vs. total arsenic for chemical source arsenic
diffusion and diffusion of an ion-implanted arsenic layer with the same inte-
grated concentration.

D,, is the effective diffusivity of As in Si that results when monatomic As+

diffuses substitutionally while inactive, stationary As complexes (VAs,) are
forming to reduce the flux of diffusable ions. Equation 62 is plotted in Figure
33 and is compared with measured data of D,, versus C, The reduction in
D,, when clustering occurs is evident.
The individual components that make up Equation 57 areshown plotted
in Figure 34 at 700°C and 1000°C. At 700°C the contribution of WAS+
becomes significant. This also corresponds to the temperature at which As
diffusion becomesgreatlyenhanced, much like Pdiffusion at highertemper-
atures.

Phosphorus Diffusion Models

The characteristics of P diffusion in Si are summarized in Table 6 using
the vacancy model of diffusion for interpretation. As a result of the large
diffusion entropy of P with neutral vacancies, ASdx, low-concentration P
diffusion is dominated by the availability of VXvacancies.13 At high concen-
trations (C>>n,) the P+IF dominates diffusion. Thus, the diffusivity shows
 Next Page

Diffusion and ton Implantation 497

Y
v).
“5 10-14
xl o KENNEDY AND MURLEV
d

1 = 1000T.

CTO=8.5x102~ATOMS/cm3

10-15
10’9 1020 1021
C+ATOMS/cm3)

Figure 33: The effect of diffusivitv of arsenic vs. total concentration for dif-
fuiions into p-type silicon at 1000%.

1016 1017 1018 1019 1020 10 1

CONCENTRATION (cnT3)

Figure 34: Arsenic and arsenic-vacancy pair concentrations vs. electron concen-
trations at two temperatures.
8
Microlithography for VLSI

R. Fabian Pease
Stanford University
Stanford, California

INTRODUCTION

The high resolution patterning of material for the fabrication of VLSI

circuits is one of the key pacing technologies in the evolution of micro-
electronics. Feature sizes are now approaching the wavelength of light
whilethepatternedareaextendsuptol cm2forasinglechipandupto1 50
cm2 over a wafer. Thus, the pattern complexity is equivalent to ten thousand
television images. However, these patterns are required to be defect free,
withfeaturesizecontrolofabout0.25um.Tomakeacompletecircuit,upto
a dozen such patterns must be overlaid with an accuracy of 0.25 urn.
Projections of scaling of integrated circuit devices indicate that dimensions
may shrink by another factor of four.
For most VLSI circuits making just one such pattern calls for many
steps. First a mask, a pattern of chromium on a glass substrate, is formed,
usually by electron beam lithography. After etching the pattern in the
chromium film, the mask image is projected onto a resist-coated wafer.
Following development of the resist, the pattern is transferred into the
underlying circuit material. By”lithography” we mean thegeneration of the
pattern in the resist. Transfering the pattern from the resist to the circuit
material is usually done by etching which is described in other chapters.
Thus, two lithographic steps are required to generate each level on the
wafer, the first to generate the mask pattern and the second the wafer
pattern.
Each lithographic step has several processes;

( i) Spin coating the workpiece with a thin (0.1-2 urn) film of resist

541
542 Semiconductor Materials

(ii) Formation of the appropriate, high resolution, aerial image

through the use of a focused electron beam in the case of mask
making and an ultra-violet image of the maskforwaferexposure.
(iii) Interaction, both physical and chemical, of the aerial image with
the resist in the exposure process.
(iv) Development of the resist pattern by selectively dissolving
away the exposed (for a positive resist) or unexposed (for a
negative) regions of the resist film.

In the sections below we describe these processes. We first describe

mask making in considerable detail because of its relative simplicity and
then go on todescribe the more complex processesforwaferexposure. In
the case of wafer exposure the aerial image can be formed by contact or
proximity printing but these techniques have largely been supplanted by
projection. A final section is a brief litany of emerging new technologies
togetherwith a list of referenceswhere the readercan pursue these topics
further. The main thrust of this chapter is to present an account of today’s
mainstream lithographic technologies.

FORMING THE RESIST FILM

Both negative and positive electron beam resist are widely used for
mask making. Because the image is built up by scanning a focused beam
sequentially over each address, the process is slow. Therefore, there is
considerable emphasis on resist sensitivity which is usually, unfortunately,
quantified as the dose in C/cm2 required to bring about the desired
chemical change.
Negative resists are long chain polymers containing groups which, on
electron bombardment, form crosslinks between adjacent chains.’ Such
groups include:

(i) Vinyl - CH + CR2

(ii) Ally1 - 131 + CH-Cl12

(iii) Epoxy - Cl+,-,CI12

0

Those portions of the film that are crosslinked are insoluble in a suitably
chosen developer.Typical required doses range from lO.‘to 10-5C/cm2for
10 keV electrons.
Positive electron resists are also long-chain polymers. However, positive
resists contain groups which, on electron bombardment, cause chain
scission and hence locally reduced molecular weight. The exposed regions
are now selectively soluble in a suitably chosen developer. Examples of
such materialsarepoly(methyl methacrylate)(PMMA)*and poly(butene-1
sulfone) (PBS)3. The chain scission process also results in gas evolution
which may also promote the selective solubility of the exposed regions.
 Microlithography for VLSI 543

Typical required doses are somewhat higher than those for negative
acting resist and range from 1O+ to 1OW4 C/cm2 for 10 keV electrons.
The resists as purchased are solutions of the above polymers in
volatile solvents. A few ml. of the solution are dispensed onto the center of
thewaferwhichisspunatapre-determinedratewhilethesolventevaporates
to leavea polymerfilm of predictable thickness.The theoryofthespinning
action is quite complicated because some material is lost through cen-
trifugal action and the viscosity of the remaining material changes during
evaporation of the solvent.4 Often the thickness, t, of the remaining film is
given by the expression:
t l klJ/&

where k is a constant related to viscosity

s is the solids content in the solution expressed in percent by weight.
w is the angular velocity.
For mask making the surface of the substrate must be quite flat, much
lessthanO.l pmoverdistancesof uptol cmandlessthanl pmoverall.The
minimum thickness of the resist is set by the maximum allowable defect
density, less than one per square inch. Although there exists little quantitative
information on defect density versus resist thickness, the minimum value
is usually 0.4 urn. Unlike masks, the surface of wafers may contain step
heightsexceeding 1 pmduetopreviouspatterningsteps. Resistfilmthick-
nesses of up to 2 to 3 pm may be required to coat these surfaces uniformly.

GENERATION OFTHE AERIAL IMAGE FOR

ELECTRON BEAM MASK MAKING

The image is formed by focusing a writing electron beam onto the

resist film and scanning the beam across the film in the appropriate pattern.
In general, mechanical scanning of the workpiece supplements the elec-
trical scanning of the beam. One advantage of this arrangement is that
large area electrical scanning becomes less important and makes it easier
to maintain the focus and positional accuracy of the deflected beam. The
writing strategy and a schematic view of the most widespread commercial
instrument, “EBES” developed at Bell Laboratories5, is shown in Figures 1
and 2. The choice of the convergence semi-angle (Yis important. Too large
avalue results in unacceptably large beam diametersdue toaberrationsof
the final beam forming lens. Too small a value results in unacceptably low
beam currents due to limits of source brightness and space charge. These
limitsarediscussed in detail elsewhere6 andaresummarized in Figure3. It
should be noted that if the electron energy is increased then the beam
current can be increased proportionately. The specifications for the current
version of EBES, Perkin-Elmer’s MEBES 3, are shown in Table 1. The
writing rate is 80 MHz, or 8x1 O7 exposed addresses per second. A rough
calculation of the exposuretime indicatesthat at a 1/4pm addresssizethe
rate comes to 2 cm*/minute. Also note that the optimum value of (Yis about
1O-2radians. Although beam diameters of less than 5 nm have been used
544 Semiconductor Materials

SYSTEM

CHIP PATTERN

WRITING PATH
(Table mollon)

Ial WRITING STRATEGY

BEAM BLANKING
--------em

, LASER
BEAM DEFLECTION
I INTERFEROMETER _--__----- -_
I

WRITING TABLE I

, I
SERVO e .- J
MOTOR I
I
I

MAG 7
INPUT

lb) SCHEMATIC VIEW

Figure 1: (a) Writing strategy used in Bell Laboratories Electron Beam Exposure
System “EBES”: a single stripe of the circuit pattern is read out repeatedly from
memory then is written on to each chip site. (b) Schematic view of EBES. The
feedback system employs beam deflection to compensate for table position errors
(After D.R. Herriott et al.‘).
 Microlithography for VLSI 545

ELECTRON SOURCE (at -VI

ELECTRON LENS

BLANKING ELECTRODES

DEFLECTION COILS

- FINAL LENS

APERTURE

BEAM OF SEMI-ANGLE
OF CONVERGENCE a

WORKPIECE

Figure 2: Schematic view of an electron beam column employing two lenses

which focus a demagnified image of the source onto the workpiece. The beam
can be blanked, swept away from the aperture, by energizing the blanking elec-
trodes. The deflection coils serve to scan the beam across the workpiece while
the aperture serves to control the convergence semi-angle (Y. Larger values of (Y
lead to increased current but at the expense of larger aberration disks.

for specialized patterninga most mask generation is carried out with

beams diameters in the range of 0.1 to 0.5 pm, respective currents of 5 nA
to 300 nA and an electron energy of 10 keV.

INTERACTION OF ELECTRONS WITH THE WORKPIECE

Theelectronsenteringtheresistfilm notonlybringaboutthechemical
effectsalluded toearlier, butarealsoscattered bythefilmandsubstrateso
that the lateral extent of the interaction can exceed the diameter of the
impinging beam. This effect is known as the proximity effect and has been
the subject of large numbers of papers. The effect lends itself well to
546 Semiconductor Materials

ELECTRON-ELECTRON
INTERACTIONS

(I (rad)
Figure 3: Contribution to focused electron beam diameter as a function of semi
angle of convergence a. Often the total beam diameter is estimated by adding in
quadrature the contributing diameters. The electron energy, E, is IO keV with
energy spread AE = 3 eV, chromatic aberration coefficient 4 cm, spherical aber-
ration coefficient CS = IO ems, cathode current density 10 A/cm’, and column
length 66 ems.

Table 1: Outline Specifications of a Commercially Available

Electron Beam Pattern Generator “MEBES 3” Manufactured by
the Perkin Elmer Corporation

Address and Beam Giameter 0.1 urn to 1.1 urn

Efaxiamum Writing Area 6 .l” x 6 .l”

Level-to-Level overlay Position Accuracy 0.12 Urn

Electron Energy 10 keV

Writing Rates 40 MHZ, 80 MHZ

Required Temperature Control 2 O.lY

 Microlithography for VLSI 547

modelling by a Monte-Carlo technique which has been verified by experi-

ment.g~lo Monte-Carlo simulations of 10 keV and 20 keV electrons are
shown in Figure 4. Qualitatively the extent of scattering of the electrons is
much less for the lower energy 10 keV electrons, however, the 20 keV
electrons are scattered less by the resist so that there is a sharper
concentration of energy dissipation around the point of impact. Fortunately,
for making photolithographic masks with minimum dimensions of 1.5 to 2
pm, the use of 10 keV electrons and 0.4 pm resist is a reasonable compro-
mise and is a widely used combination which does not require elaborate
correction for proximity effects. If either thicker resist or finer dimensions
are required, then higher electron energies and some form of local dose
variation for correction of proximity effects may become desirable. How-
ever, for most of today’s mask making, the above combination of 10 keV
electrons and a resist thickness of 0.4 pm allows us to treat the proximity
effect as just anothercontribution to beam diameter.The magnitude of the
contribution can be determined by simulation” or by experimentga10 to be

r2
J(r) + Jb) exp (- 2)
='p

where Jr is the current density at radius r, and rP= 0.2 pm + 0.1 pm for the
case depicted in Figure 4a. At higher voltages two gaussian terms are
needed for an adequate description.
The chemical effect of electron bombardment has already been des-
cribed as generating crosslinks between adjacent polymer chains to
create an insoluble gel. We can invoke a simple model to describe quanti-
tatively the resist’s behavior in terms of the parameters, sensitivity and
contrast.
The starting point of the model is to assume the following:

X - brn X -- pm

,a, 10 Icav lb1 20 keV

Figure 4: Trajectories of electrons scattered by a typical target comprising 0.4

pm polymeric resist on a silicon substrate. Substitution of glass as the substrate
material would give rise to a slightly greater extent of scattering.”
548 Semiconductor Materials

(0 The local rate of generating crosslinks is proportional to the

local power dissipated by the electron beam.
(ii) When two or more molecules are crosslinked together they
form an insoluble group.
(iii) The number of crosslinks per unit volume obeys a Poisson
distribution.
(iv) There are many crosslinking sites per chain such that only a
negligible fraction form crosslinks at the lowest exposure
needed to crosslink virtually all molecules.
(v) Associated with each chain is a volume, V,, within which a
crosslinking event results in a bond to a neighboring chain.
(vi) The effect of the resist material on the incoming beam is
unaffected bycrosslinking,i.e.thedistributionofpowerdissipa-
tion is constant during exposure.
(vii) The energy A(z) where z is the depth into the resist. We shall
initially assume that A is constant with depth.

For very low exposures, only isolated pairsof molecules arecrosslinked

together. On development, these pairs per se may not be dissolved, but all
the surrounding uncrosslinked material is dissolved and washed away so
that no resist remains after development. At some critical dose enough
chains are crosslinked together so that a skeletal gel is formed which
remains after the developing solvent has leeched out the uncrosslinked
polymer chains. Beyond this exposure level, we assume that each crosslink
that bondsapreviouslyuncrosslinked moleculecontributesthat molecule
to the gel. The fractional thickness, T,, of resist remaining after develop-
ment is equal to the fraction of (identically sized) molecules, each with the
samevolume,V,,,, that haveat least 1 crosslinkto neighboring molecules. If
N, is the mean local concentration of crosslinks then the mean number of
crosslinks per volume Vm is N,Vm. The fraction of molecules with no
crosslink to neighboring molecules is, from the Poisson distribution, exp
(-V,,,NJ Therefore, the local fractional thickness remaining is

Tr* * 1 - exp (-vrJie 1

for doses in excess of the critical dose and

where Cl is the local dose (in C/cm*)

g is the number of crosslinks generated per eV dissipated (the
sensitivity of the resist material)
q is the electronic charge

T, l 1 - exp(-v, Ag Q/q)
Therefore, a plot of Tn versus log,, Q can be drawn (Figure 5). The general
form is clear and understandable. At doses below the critical dose Tn = 0.
 Microlithography for VLSI 549

0.8 -

EXPOSURE (C- cm’*)

Figure 5: Fractional thickness remaining after development T, as function of

exposure for PGMA-co-EA negative electron resist (COP) for V = 10 kV. The
solid line is the model, the circles are experimental points (Reference 12).

At increasingly higher doses, increasing numbers of molecules are cross-

linked until virtually all molecules are crosslinked together so that continued
exposure adds virtually nothing. However, the shape of the curve in Figure
5 can also be used to quantify two resist parameters. One is the sensitivity
or dose required to bring about the required value of T,. Thus, forT, = 0.5,
-V, Ag Q/q = In 0.5.

0.7x1 .6x10-lg
Q-, vm k3 C/cm:!

This looks quite reasonable since when the required dose is reduced for
largerV,,afilm madeof largermolecules requiresasmallerconcentration
of crosslinkstobondthemalltogether.Also,at IargevaluesofAtheenergy
dissipated per incident electron per unit depth, and g, the number of
crosslinks per eV dissipated will also tend to lower Q.
The other parameter is the contrast, or gamma, which is a measure of
the minimum ratio of exposures needed to bring about a required difference
in T, (often 0 to 50%). If we approximate the curve if Figure 5 as three
straight line segments(shown dotted) then theslopeof thecentral portion
is the contrast (y) defined as dT,/d(log,, Q). If this slope is equal to the
maximum slope of the solid curve then we can quantify y as

dTn
d(loglO)Q I l -
eloglOe +085 l

ElX

Note that this value is independent of g, A, V,,,. According to this simple

550 Semiconductor Materials

model the contrast of negative acting, crosslinking resists is about 0.85

and independent of their constituents. As it happens a great many negative
acting electron beam resist materials do have approximately this value of
contrast. Of course, a high value is desirable because this means that less
contrast in the aerial image is needed to bring about agiven relief image in
the resist. A number of materials are reported to have values of up to 1.6.
There are a number of possible explanations. One is that those few
materials with abnormally high values are the most attractive and hence
are selected for intense study. Another is that the above simple model may
not apply so well to these few materials. For example, a higher value of y is
obtained if we postulate that more than 2 molecules must be crosslinked
together to form an insoluble gel. Nonetheless, the simple model above
accounts for the main features of negative acting, crosslinking, electron-
beam resist. It is quite straightforward to embellish the simple model. A
spread in thevalues of molecularweight can be modeled as an equivalent
spread in the values of V,. It can be determined, as has been reported
experimentally13, that this will give a lowervalue of y than a material with a
singlevalueofV,ormolecularweight.Anon-uniformvalueofAcanalsobe
accounted for by describing each elemental layer according to the above
model. It so happens that for the case we are concerned with, 10 keV
electrons exposing 0.4 urn thick resist the assumption that A be uniform
throughout the resist thickness is not a bad one.
The negative resist most frequently used for mask making is poly
(glycidyl/methacrylate-co-ethylacrylate) referredtocolIoquiallyasCOP.13
It hasacontrastofabout0.9,closetothevaluepredicted byourmodel,MW
of 180,000 and a g value of .Ol crosslinks per eV. Determining Vm is tricky
but if we take V, as the mean volume occupied per molecule and the
specific gravity as 1 gm/cc, then V, = 2x1 O-lgcc. From experiment and
from simulation of electron scattering, a 10 keV electron, on the average,
dissipates l/3 of its energy in a resist film 0.4 urn thick;

10,000 8
whence A + + 10 eV/cm/electron
3x0.4x10-4

whence for T, + 0.5 Q + 3.6~10’~ C/cm2

This is remarkably close to the value shown in Figure 5 although a figure of

2x10.’ C/cm2 is usually recommended for this material.
To determine the 2-dimensional relief image obtained as a result of 10
kV electron beam of known diameter exposing a 0.4 pm-thick negative
resist, we can employ a crude model in which the local thickness after
developing is given by the original thickness multiplied by the value of T,
corresponding to the local energy dissipated throughout the thickness of
the resist. In practice neither this nor any other model is yet used because
the negative crosslin king resists used swell considerably on developing. A
doubling of the thickness during development has been observed. Even
with a developing solvent mixture optimized to minimize swelling the
shape of the image is set by the rheological behavior of the resist in the
developing and rinsing solventsand in the subsequent post-development
 Microlithography for VLSI 551

bake. Some example of images in negative electron resist are shown in

Figure 6. Thus these particular materials do not lend themselves either to
useful modelling or to high resolution, steep-sided patterns. For making
patterns of minimum critical dimensions of 4 pm or greater, however, such
materials are in widespread use because of their sensitivity, ease of use
and adhesion.
For mask making the subsequent pattern transfer step is accomplished
by: wet etching of a 60 nm thick chromium film with a buffered ceric
ammonium nitrate solution. Thus good adhesion is necessary but a steep
sided resist profile is not.
The most frequently used positive resist material for electron beam
mask making is poly (butene I-sulfone) (“PBS”).3 The repeat unit of the
chain is:

On irradiation by electrons, the predominant chemical reaction is chain

scission accompanied by the evolution of SO, gas. The exposed regions
can be selectively dissolved away in a solution of water and methyl iso-
amyl ketone (MIAK). The curve of T, versus dose of 10 keV electrons
(Figure 7) indicates that the minimum required dose is 8x1 O-7C/cm* and
that the contrast is about 1.5. The curve shown in Figure 7 depends
critically on the development process since considerable swelling occurs
on development, though to lesser extent than with COP. Thus, a model of
the exposure and development process that has some theoretical basis
and that also reliably predicts the resulting relief image does not yet exist
for this material. To compound the issue, it is not always easy to obtain
good SEM micrographs of PBS patterns because the material is believed
to deform as a result of the electron irradiation in the SEM. At the minimum
exposure level, feature edges have very shallow slopes (Figure 8) although,
with much higher exposures(20&/cm, at 20 kV) and modified developing,
crisp submicron features have been reported.14 In practice, masks with
controlledfeaturesizesdown to 1 pm are produced using0.4pm thickPBS
resist and 10 keV electron exposure. The linewidths have a standard
deviation of less than 0.08 pm and defect densities are adequately low. As
with COP, the subsequent pattern transfer step is wet etching of a 60 nm
chromium film with a buffered solution of cericammonium nitrate. Examples
of portions of chromium mask made in this way are shown in Figure 9.

EXPOSURE AND DEVELOPMENT OF

PHOTORESIST ON SEMICONDUCTOR WAFERS

We must now expose the resist on the wafer in accordance with the
maskpattern.Thesimplestwayofaccomplishingthisisbycontactprinting
or proximity printing. The formertechnique allows excellent resolution but
is prone to defects especially when many contacts are needed to assure
accurate alignment. Thus, contact printing is not in widespread use for
552 Semiconductor Materials
 Microlithography for VLSI 553

I I
+=
P
f \ \r =l6
a
2 \
: \
\
\
zY 1 \
::
i
I-
-l 0.5 -
2
0
F I
s:
u
IL 10-8 10-7 10-6 10-5

EXPOSURE _ C/cm2

Figure 7: Fractional thickness remaining after development versus exposure for

poly (butene 1 -sulfone) resist exposed with 10 kV electrons (Reference 3).

Figure 8: SEM photograph showing end view of an image formed by electron

exposure of PBS resist (photograph courtesy of E. Crabb and G. Eiden).
554 Semiconductor Materials

Figure 9: Two views of chromium masks made with electron beam exposure of
PBS resist (photographs courtesy of D.H. Dameron and J.P. Ballantyne).
 Microlithography for VLSI 555

VLSI. The defect problem is alleviated by proximity printing in which a gap

of 15-30 pm exists between mask and wafer. Unfortunately, this gap
degrades resolution so that this technique is no longer the method of
choice for high density circuit manufacture. The method now adopted is to
project an image of the mask onto the wafer by means of a lens or mirror
system. There are two main classes of projection exposure tools also
referredtoas”maskaligners”.Thefirstisthescanningprojectionalignerin
which a doubly reflecting system (Figure 10) forms an erect image over an
arc-shapedfieldofview.Theopticsaresuchthatoverthefieldofviewthere
are essentially no aberrations for numerical aperture values (NA) up to 3.
By mechanically scanning both the mask, containing the pattern to be
transferred to the wafer, and the wafer simultaneously through the illumina-
tion over the field of view an image of the complete pattern on the mask is
transferred to the resist on the wafer. This scanning projection technology
has been in use for about eight years and can be used forthe manufacture
of circuits with linewidths down to less than 2 pm. The specifications for
onesuch system, the Perkin-Elmer Micralign 660 HT@areoutlined inTable
2. The other form of projection aligner is usually referred to as a “stepper”

LOEJECT

Figure IO: Schematic view of doubly reflecting optics used in scanning pro-
jection printing.
556 Semiconductor Materials

Table 2: Outline Specifications for the Perkin-Elmer “Micralign 660 HT”

Scanning Projection Printer

Throughput : ‘100 6-ind, wafers per hour

Exposing Wavelengths: 240 nm to 436 nm

Resolution: 0.9 urn to 1.25 urn lines and spaces

Auto-Alignment: * 0.25 urn (98% of population)

Magnification Compensation: * 2 urn range + 0.25 pm precision

Machine-to-Machine Overlay: x 0.45 (98% of population)

Uptime : In excess of 90%

because the image of the mask pattern occupies only a small portion (1 x 1
cm*) of the wafer area and the whole area is filled up by stepping the wafer
mechanically and repeating the exposures. Refracting focusing is usually
used for the optics. With this technique, VLSI chips with feature sizes of 1
l/4 pm are being manufactured. The specifications of two such steppers
are shown in Tables 3 and 4. With these techniques both positive and
negative photoresist are used although the former is becoming the most
popular.

FORMATION OF THE AERIAL

IMAGE IN PROJECTION MASKALIGNERS

In both the scanning projection and the stepping aligners the physics
of image formation is the same. An outline of the basic scheme is shown in
Figure 11. A mask is illuminated and the projection optics focuses an
image of the mask at the wafer surface. As with electron beam lithography

Table 3: Outline Specifications of the Ultratech Model 1000 Wafer Stepper

Throughput: 24 6-inch wafers per hour

Exposing Wavelengths: 390 nm - 450 nm

Numerical Aperture: 0.315

Effective Partial Coherence: 0.45

Resolution: [O .8X(NA) = 1 .l urn lines and spaces]

Field Size : 20 mm x 7.6 mm (max. rectangle)

Machine Alignment f 0.26 urn ( 2-sigma)

Total RMS Overlay Precision: * 0.35 urn

 Next Page

Microlithography for VLSI 557

Table 4: Outline Specifications of the GCA Model 63006 Wafer Stepper

Throughput: 40 1% mm wafer/hour

Alignment Precision: f 0.15 urn TIR, Global

Numerical Aperture: 0 JO

Resolution: (working) 1 .l urn [0.8X(NA) I

Field Size: 20 mm diam.

Exposing Wavelength: 436 nm (g line)

Magnification: l/5 x

FOCUSING SYSTEM
MASK (MIRROR OR LENS) WAFER
PATTERN --

/
/
/
/
/
/
/
5
RAYS APERTURE IMAGE OF MASK
DEFINING Q PATTERN OF
MAGNIFICATION M

Figure 11: Basic optics required for projection printing.

the semi-angle of convergence, (Y, is a critical parameter although for

somewhat different reasons. Because the optical engineer can arbitrarily
control the shape of the refracting or reflecting surfaces, the images are
virtually aberration-free over the field of view. The sharpness of the aerial
image is set by diffraction, provided that the wafer surface is in the plane of
bestfocus. Whentheilluminationisintheformofaplanewavefrontandthe
mask pattern is a 1 -dimensional grating whose amplitude transmissivity is
a sine wave, then there is only first order diffraction. If (Yis large enough to
accept these diffracted beams then, according to the Abbe principle for
microscopic image formation,15 the image is formed with full contrast at
the wafer surface. The converse is true, that if (Y is too small to accept the
diffracted beams then there is zero contrast at the wafer and the grating is
9

Metallization for VLSI Interconnect

and Packaging

Paul S. Ho
IBM Thomas J. Watson Research Center
Yorktown Heights, NY

INTRODUCTION

Over the past several years, a significant fraction of the resources of

the semiconductor industry has been focused on the development of
systems with very large scale integration (VLSI). For hardware, this consists
of primarily the development of device chips and packaging architecture.
Significant progress has been made in both areas with great improvement
in the circuit density and performance. Advances in chip development are
illustrated in Figure 1 where one can see that an exponential increase in
thecircuitdensityformemoryandprocessorchipshasbeenachievedwith
time.’ At this time, dynamic memories of 256k bit density are available on
the market and plans for manufacturing memory chips of 1 M bit density
have been announced by several companies in the United States and
Japan. Comparable progress has been made in the development of logic
chips,suchasmicroprocessors,which havemorecomplexstructuresthan
the memory chips. This trend, if sustainable, indicatesthat development of
the 4 M bit memory chip is to be expected in this decade. This will require
the development of ultra-large-scale integration with minimum device
dimensions in the micron or even submicron range.’
Such progress is achieved largely through continuing reduction in
device dimensions. In the course of this development, the metallization
structures of the device and packaging have evolved into one with a high
degree of complexity. It is the objective of this chapter to discuss the
implications of VLSI on metallization and some of the basic problems.

575
576 Semiconductor Materials

TNumber 01 transistor Iunctions

is

Figure 1: Progress in silicon chip technology since 1960 (Source: Siemens). Note
that the degree of integration quadruples about every 3 years. While the develop-
ment in microprocessors may show after the 32 bit level, the advance in dynamic
memories remains constant (Reference 1).

Before discussing specific issues of metallization, it is instructive to illustrate

the drasticchange in the metallization structure by showing in Figure2 two
bipolar devices manufactured about a decade apart3The early device has
only one active element in a chip with a dimension of about 2.5 mm by 2.5
mm. In contrast, thecontacts in the recent chip havedimensionsof about 3
micron by 3 micron. If the device density can be increased simply in
accordancewiththedimensionsofthecontacts,thenumberofdevicesfor
the lattercan be increased about 300X300 times. Scaling of such magnitude
was not accomplished because interconnections had to be provided to
wire the devices. To fulfill this requirement, a very large portion of the area
of this chip had to be used for the interconnect structure. As a result, this
chip contains only about 1000 active elements which is about 100 times
less than the density allowed by stalling the contact dimensions. Even
with only 1000 elements, the overall structure required for this chip is
highly complex, evolving from a simple single-level structure to one with a
multilevel architecture.
In addition to device density, interconnect is important in determining
the performance of the device chips. For example, by comparing the
dimensionsofthecontacttothatoftheinterconnectofthemultilayerchip,
one can see that its performance is probably not limited by the switching
speed of the contacts, but rather by the time delay for signal propagation
through the interconnect.
With the increased circuit density on the chip, more device functions
can be assembled onto a single circuit board. While this provides a high
 Metallization for VLSI Interconnect 577

Protective

PbSn
solder pad Cu-Sn mrermetallic

2.3 /.m Al-J% Cu

b 0.85 v A:4% Cu

Silicon 0. I5 pm Cr.Cr,O)

Figure 2: Schematics of interconnect metallization structure for (a) an early bi-

polar device and (b) a current advanced bipolar device. Note that the size of the
chip in (a) containing one transistor is about 0.25 cm by 0.25 cm while the con-
tact dimension in (b) is about 3 pm by 3 pm (Reference 3).
578 Semiconductor Materials

degree of flexibility for the functional design of the chip, to enhance the
performance and the level of integration of the whole system, new packaging
structuresare required which can utilize the high density and performance
of the device chips. This has brought forth significant improvements in the
performance and level of integration of the packaging system. As indicated
by the statistics in Figure 3, the wiring density in packaging has grown
exponentially with time, but at a rate less steep than that of the device
density.4 Although this has not been as well recognized in the past, it has
becomeclear recently that packaging isan important issue, particularlyfor
the high end computer systems where performance is the prevailing
factor.
Thiscan beillustratedbycomparingtheIBM3033and3081 computer
systems.5As shown in Figure4, the performance of the central processing
unit, as measured by system cycle time, can be divided into chip and
packaging portions. While the cycling time in the chip has been improved
about 20%, the improvement in the packaging portion is about threefold.
(The improvement in the circuit chips should not be measured by speed
alone since there issignificant enhancement in the circuit densitywhich is
not shown in Figure 4). The improvement is achieved primarily through a

500-

200-

loo-

so- ELSI 24-mm MC

20-

13 10-
z
c
$ 5-
9
B
P 2-
3
f?
1 I I I I I I
o-1 1 10 IO2 IO3 IO4 lo5

Maximum arcuits per package component

Figure 3: Progress in circuit density with time at the packaging module level.
The abbreviations associated with the data points represent different versions of
IBM packaging modules (Reference 4).
 Metallization for VLSI Interconnect 579

new design of the interconnect module and board in the packaging

system. The distributions of the wiring structure at different levels of these
two systems are compared in Table 1 a. The new designs of the module and
board provide a high level of integration which makes it possible to
eliminate a large portion of the wiring cables in the 3033 system. This
greatly simplifies the wiring structure and provides significant improvement
in the reliability as well. It is instructive to compare the number of inter-
connects for the 3081 module and its equivalent in 3033 technology. As
summarized in Table 1 b, the high level of integration in the 3081 system
makes possible a reduction of about tenfold in the number of interconnects.
Thus interconnect metallization is important in determining both the
density and performance of the system. Since these are the general goals
ofVLSI, theoptimization of the metallizationstructure becomesan essential
part of the VLSI technology. Careful consideration should be given to not
only the layout of the interconnect but also other aspects, such as material
characteristics, processing reliability and manufacturingcost.As the trend
continues toward device miniaturization, interconnect metallization will
become even more important.
In this chapter, several basic aspects of VLSI interconnect and
packaging will be discussed. It is divided into two parts: system requirements
and material characteristics. The discussion of system requirements focuses
on the wiring structure and the impact of device scaling. The wiring
structure is a complex but fundamental issue arising from the need for
interconnecting more devices when the device density increases. Device

Card

Module

Figure 4: Comparison of system performance of the IBM 3033 and 3081 cen-
tral processing units (Reference 14).
580 Semiconductor Materials

Table 1: Comparison of the IBM 3033 and 3081 Technologies

a. Percentage distribution of total wire length by packaging level (Ref. 5).

Packaging level 3033 Processor 308 1 Processor

Chip 1.3 9.2

Module - 41.9

Card 38.8 -

Board 12.9 31.1

Cable 47.0 17.8

100% 100%

b. Average number of logic interconnections between pat caging levels in two

technologies (Ref. 14).

3033 Technology

equivalent 308 1 Module

Chip-to-module 22,560 4366

Module-to-card 22,560
670 (no card)
Card-to-hoard 4,000

Total 49.120 5038

scaling imposescertain requirements on the device structure and functions

which have to be fulfilled by properly matching the materialsand design of
the interconnect structure.Thesetwotopicsdefine thegeneral requirements
of interconnect metallization forVLSI. With the requirementsclarified, the
material characteristics of interconnect will be discussed, with emphasis
placed on the thermal and electrical properties. This will be followed by
discussions of two material reliability problems: contact resistance and
electromigration. These problems are used to illustrate the impact of
scaling on specific interconnect functions. Some of thecurrent approaches
to solve them will be indicated. It is not the intent of this article to review the
different metallization schemes, nor specific device structures and proc-
essing developments. Some of these subjects are reviewed in other
chapters and some have been discussed in the literature.6,7
 Metallization for VLSI Interconnect 581

WIRING STRUCTURE

In Figure 2, one can see that the interconnect structure on a device

chipservesfour main functions: contacttojunction andgate, interconnection
between device cells, interlevel insulation, and input and output signal
pads. Inacomputersystem,interconnectstructureshavetobeprovidedto
connect the device chips to form a central processing unit as well as to
interface with other functions, e.g. storage devices, printers and terminals.
While it is beyond the scope of this chapter to discuss the overall issues of
system integration, one can readily recognize that the design of the
interconnect wiring structure is very complicated. The complexity originates
from thecombinational natureof interconnectingaverylargeensembleof
elements.8 This can be readily recognized using asimpleestimate that for
N elements, there ar N(N-1)/2 possible binary connections. So, when the
number of circuit elements increases beyond about 10k on a chip, the
wiring becomes very complicated. Such an estimate overprojects the
number of interconnects required since in practice devices are not wired
randomly. Instead, the circuits are grouped in specific ways according to
their functions and the placement of various types of circuits is optimized
to reduce the number of interconnections. The nature of this problem has
been investigated by treating it as a statistical optimization process of
interconnecting a certain number of device cells subject to some overall
layout of a functional block on a logic chip.g,10 The result follows the so-
called “Rent’s rule” which specifies the number of connections (or pins) P
required to wire N devices cells in a system by the following relationship.

P = aNb (1)

where a and b are parameters with a between 2 to 3 and b about % to 2/3.1l

This rule can be illustrated by the results obtained by Heller et al.‘O
Using a statistical simulation method, they calculated the wiring require-
mentsforalogicchipasafunctionofthegatedensity.Asshownin Figure5,
the number of wiring tracks required follows Rent’s rulewith bvarying from
about ‘12at low gate density to about 2/3at high gate density. This example
shows the empirical nature of the Rent’s rule since its parameters vary
with the device density. The increase in b with gate density shows that the
wiring requirements actually exceeds that predicted by Rent’s rule based
on low gate density.
As device density increases, there is anotherfactorcontributing to the
increase in the wiring requirements. This is the increase in the average
length of each connection. Thisaltogetherwith the increase in the number
of connectionscauses the total wire length to increasedrastically, asseen
from results obtained by Heller et al. (Figure 6). These results can be used
to estimate semi-quantitatively the impact on the wiring requirements of a
bipolar chip as the device density increases. For example, when the
number of logic circuits increases from 100 to 1000, the number of
connections required increases from 13 to 20 while the total wire length
increases by a factor of about 100. Assuming the wire track width can be
scaled proportionally according to the numbersof circuits, i.e. byafactorof
582 Semiconductor Materials

% I
I I
100

GATES/CHIP
I
1000

Figure 5: Results of a numerical analysis showing the “Rent’s rule” for a logic
chip. This rule correlates empirically the number of wire tracks required per cell
to the device density on a chip (Reference 10).

,“~o,thetotalwiring areawouldstill haveto increase byafactorofv lo.This

indicates that as device scaling continues, the circuit layout and the chip
becomes increasingly dominated by interconnect wiring. Eventually, it Will
becomeimpossibletouseallthecircuitsonachipsimplybecausesomeof
them cannot be wired properly.
This can be seen from the statistics of a recent bipolar chip’* with a
surface area of 0.29 cm* and a gate count of about 1500. The total length
required for wiring is 4m. With a wire channel width, line width plus line-to-
line separation, of 6.5 pm, the total wiring area is 0.26 cm2, which is about
90%ofthesurfaceareaofthechip.Thusthestructureofthischipisclearly
dictated by the wiring requirements of the interconnect.
In the layout of the wiring structure, several factors are important to
consider in order to optimize the device performance. First, the length of
connection should be minimized. This is equivalent to minimizing the RC
response time for optimum circuit performance. Second, the layout should
minimize the cross talk in order to reduce the level of inductance noise
coming from the random switching of individual circuits. Third, it is desirable
to keepall theconnectionsascloseto theaverage lengthaspossible.This
reduces the random fluctuations of the switching voltage at the contact.
Fourth, the placement of circuits should distribute the power dissipation
evenly. This is to minimize the local heating, a problem particularly important
for driver circuits. And finally, the layout should facilitate detection and
correction of errors and defects.
 Metallization for VLSI Interconnect 583

it
I

;i

2
E
k-

5
104-
0
dOTOTAl_
)///-
O
0

AVERAGE /

CIRCUITS/CHIP

Figure 6: The average length of interconnect and the total wire length on a logic
chip as a function of device density. The lengths are measured in circuit pitches,
i.e. the square root of the area per circuit (Reference 12).

An effective approach in meeting these requirements is to employ

multilevel interconnects. The structure of the multilevel chip in Figure 2
gives an example of a 3 level design. In this structure, all the wire tracks in
one level run in one direction while those in the adjacent level run in a
perpendicular direction. Such a structure provides a simple means to
miminize the cross talk and the average length of the interconnects.
In the design of the multilevelstructure, many material and processing
requirements have to be considered in addition to wiring placement. For
example, the number of levels can be reduced by packing as many lines as
possible on one level. This demands high precision and good control of the
patterning processes, such as lithography and metal etching. The use of
multilevel interconnects can relax the wiring density requirements but
causes problems in other processing areas, such as planarization and
topography of interlayer contacts. The method of dealing with these
problems often depends on the overall objective of the system design, e.g.
performance or cost. These factors have to be optimized together with
wiring placement.
The design of the wiring structure for the chip is only the first step to
building the interconnections of the computersystem. After the chip level,
otherlevelsof interconnectionsare requiredforassembling thechipsinto
the central processor and for interfacing the processor storage and
peripheral equipment. As shown schematically in Figure 7, the packaging
system has to also provide mechanical support, power, cooling, etc. in
order to assume proper function of the system.13 The complexity of the
packaging system depends on the functional requirements of the computer.
For high end systems where the design is driven bydensityand performance,
584 Semiconductor Materials

Figure 7: Schematic representation for the structure of a computer package.

This structure contains thermal and mechanical supports for the chips as well as
the high-speed interconnections that permit information exchange between chips
and peripheral equipment (Reference 13).

packaging can become very complicated and usually requires a high level
of integration and optimization. This can be illustrated by the packaging of
the IBM 3081 system. This system contains two main levels of wiring
structure: the module and the board. The module is designated as the
thermal conduction module (TCM). Each TCM contains about 100 device
chips, each of which has about 2000 circuits. It is built into a ceramic
substrateofabout5.5 mmthickand 10cm bylOcmsquare(Figure8).The
wiring structure in the board is designed for each board to support 10
modules.15 It has a 20-layer structure containing about 6,000 connectins
with dimensions of 60 cm by 70 cm. The wiring complexity of this board is
comparable to that of the TCM.
It is interesting toestimatethewiring requirementsforthemoduleand
theboardonthebasisofRent’srule.Takingtheparameteratobe2.5andb
0.6, the number of interconnects required for each chip is about 250
connectionsforthe2000circuits.Tosupportthe100chipsononemodule
requires 16 times the I/O connections of an individual chip. This turns out
to be about 4,000 connections for each module. These requirements
evolve the module into a structure with more than 30 interconnect layers
 Metallization for VLSI interconnect 585

B;IW phe
- ,

Figure 8: (a) Exploded view of the thermal conduction module assembly. (b)
Schematic drawing showing the wiring structure of the multilayer ceramic sub-
strate used in the thermal conduction module (Reference 14).
586 Semiconductor Materials

as shown in Figure 8. In order to optimize this structure, the layers are

organized into three levels: the wiring redistribution layer, signal redistrib-
ution layers and powerdistribution layers.At the board level, toconnect 10
suchmoduleswithatotalof40,OOOinterconnectsontoone boardrequires
about 600 connections according to the Rent’s rule. Compared with Table
1 b, these estimates of 4000 interconnects per module and 600 per board
are in reasonableagreement with the numberof interconnectionsactually
used.
The complexity of interconnect wiring necessitates the use of sophisti-
cated computer-aided design techniques. It is beyond the scope of this
article to review this important and fast developing area except to point out
that advanced methods of statistical mechanics have recently been
employed forwiring placement. For example, Kirkpatrick et al.16 employed
a novel approach of simulated annealing based on the Monte Carlo
technique. In such simulations, most of the interconnect requirements
mentioned above can be incorporated as boundary constraints. This
method can be applied to design wiring layout on a chip as well as
interconnects between chips in a package module. An example of the
application of this method isshown in Figure9 where the length distributions
for an interconnect structure calculated by various statistical methods are
compared. The results obtained by simulated annealing has a narrower
“peak” distribution, indicating the method is more efficient in comparison
with other methods in placing interconnects with an average length.

. _ _ _ _ _ _ _ _ _ _ _ _ _

--.
,------ 1
i .._...... 1

r 50
. _ ___
-.-.
--=.

-.-.
_
] :--+ : : : : i -- (
0
0 2 4 6 8 10
1 3 5 7 9

Channel position

Figure 9: Histogram of the maximum wire densities within a given channel cal-
culated using various methods of interconnect routing. The channel position
provides a measure of the length of the interconnect. The top dash line repre-
sents the results obtained by the simulated annealing technique (Reference 16).
 Metallization for VLSI Interconnect 587

IMPACT OF DEVICE SCALING

In general, the aim of device scaling is twofold: first, to improve the

device performance, particularly its speed and second, to increase the
device density. These goals impose certain requirements on the function
and dimension of various components in the device, which constitute the
so-called scaling rules. The scaling rules differ for field effect transistors
(FET) and bipolar devices because of their different operating principles.
Based on aconstant field approximation, Dennard et al.17first derived aset
of scaling rules for MOSFET devices by assuming all dimensions can be
scaled linearly. They found that as the device dimensionswere reduced by
a factor of k, its performance as measured by the delay per circuit may be
enhanced by the same factor if the dopant level increases by k while the
voltage and current are reduced by k. On this basis, one can deduce the
scaling factor for other parameters pertinent to interconnect metallization,
such as the resistance, capacitance, current density, power dissipation
and etc. These factors are listed in Table 2.

Table 2: Scaling Results for Some Device Parameters

Scaling Factor

Device Parameter FET Bipolar

Device dimension t,,, L, W I/k I/k

Delay time/circuit I/k I/k

Doping concentration k k

Voltage I/k -1

Current I/k I/k-l

Power density 1 -k-k*

Capacitance I/k l/k

Line resistance k k

Line response time 1 -1

Line current density k -k*

Scaling of bipolar devices is more complicated because its vertical

structure and operation principle do not allow similar linear scaling employed
for FETdevices. The wide spectrum of bipolar circuit designsadds additional
complications to deducing a general set of scaling rules. Another parameter
588 Semiconductor Materials

relevant to the discussion of interconnect is the applied voltage. Since the

switching voltage can not be less than the voltage drop across a p-n
junction, which is usually about half of the bandgap of the semiconductor
(e.g. about 0.6 eV for Si), scaling of the voltage is restricted. Indeed, the
voltage level used in devices is usually set to be a constant, chosen as a
standard by the industry. Based on constant-voltage scaling, Tang and
Solomon18 employed device simulation techniques to analyze the effect
of scaling on device parameters. They found that for an optimum power-
delay product, the current density increases about linearly with the reduction
in device dimensions. For 12L type circuits, Princelg deduced separately a
set of scaling rules based on a linear scaling of delay time. He found that
the current density varies approximately with the square of the dimension.
Results of these two studies lead to somewhat different scaling of device
parameters which are summarized in Table II. There are certain limitations
as to how far the scaling rules can be extrapolated before encountering
difficulty in device processing or basic physics. For example, the minimum
switching voltage in FET devices is limited by the noise level and voltage
fluctuations generated by random switching and variations in line dimen-
sions. This restricts the lower bound that thevoltage level in an FETcan be
reduced. Usually, the gate voltage can not be substantially reduced below
0.5 Ev. This restricts the scaling of the voltage in FET devices to a level
similar to that of the bipolar devices. Line thickness is another parameter
that can not be reduced infinitely. Practical thickness is usually not less
than about 5000 A. There are additional limitations coming from basic
device physics.20 Such problems will affect the scaling rules, particularly
for devices with dimensions in the submicron range.
In spite of these difficulties, the resultes summarized in Table II
providesomegeneralguidelinestoexaminetherequirementsimposedby
device scaling on the interconnect functions. For FET devices, scaling of
the device dimensions and circuit delay by k requires the doping concen-
tration to increase by k while voltage and current decrease by k. On this
basis, the response time of an isolated interconnect line will remain
unchanged. (The implication of a constant line response time on the
system performance and complications due to interference between
conductor lines will be discussed in the next section.) In addition, the l/k
scaling of thevoltage and current is balanced by the k2 increase in device
density. This results in a constant power density for the chip although the
current density increases by k. Thus to a first order approximation, scaling
of FETdevices will not change the cooling requirementsat the chip level in
spite of the increase in the device density. It does require, however, the
current-carrying capability of the line to be higher.
For bipolar devices, the fact that the voltage level cannot be scaled in
accordance with the device dimension causes increases in power density
and line current density exceed the scaling factor. Depending on the
desired performance level, these two parameters can increase as much as
k2, making the requirements for cooling and current-carrying capabilities
significantly more severe than for FET devices. These factors plus the
intrinsic complexity of the device structure make the development of an
interconnect structure for bipolar devices considerably more difficult than
for FETs.
 Metallization for VLSI Interconnect 589

To illustrate quantitatively the increasing demands due to device

miniaturization, the values of several key device parameters are given in
Table 3 for three stages of device development. These highlight several
key areas for future concern, including the formation of shallow contacts
with high dopant concentrations, the reliability of very thin gate insulators,
the development of conductor lines with high electromigration resistance
and the design of efficient cooling structures. While some of these problems
will be discussed in the following sections, it becomes clear that scaling
brings forth a set of requirements in addition to those from wiring placement
for the design of VLSI interconnects. In general it is difficult to design a
structure optimizing all these factors. A practical approach is to choose a
certain combination of metallization and structure to optimize some
designed functions of the system. For example, for bipolar logic circuits
where speed and power dissipation are important, the metallization should
be of low resistance and with reasonable cross-sectional area to reduce
the current density and time delay. In contrast, for FET memory chips
where density and reliability are important, the line dimensions should be
minimized with the possibility of using thermally stable but resistive
refractory metals.

Table 3: Scaling Trends in Device Dimensions

Period Line Junction Oxide Current Density

Width Depth Thickness (1 O5 A/cm2)

(rm) (rm) A FET Bipolar

1970’s 3-6 -1 -1000 0.2-0.5 0.5-l

198045 1.5-3 -0.25-5 250-500 0.5-I 2-4

Late 1980’s 0.5-1.5 -.I-.25 100-250 l-2 8-15

ELECTRICAL CHARACTERISTICS

When a signal pulse is transmitted through a conductor line, a certain

amountoftimeisrequiredforthesignalleveltorisefromzerotoitsoriginal
magnitude. This rise time corresponds to the wiring delay and can be
calculated by treating the conductor as a transmission line. For the usual
situation of long pulses, i.e. pulse lengths longer or at least comparable to
the wire lengths, the rise time equals 2.3 times the RC constant, where R
and Care the resistance and capacitance of the wire respectively. The RC
constant can be expressed as follows
590 Semiconductor Materials

C = CWL
t OX

and (2)

wherep is the resistivity, L the wire length, W the wire width, t, thickness of
the wire, E the permittivity, and t,, the thickness of the oxide. Equation 2
showsthatift,andt,,canbescaledinthesamemannerasL,thelinedelay
would remain constant (seeTable 2 also). Therefore, the line delay becomes
an increasingly larger portion of the total circuit delay as the device
dimension decreases. Eventually it can become a substantial part or even
dominatethesystem response timeforverysmalldimensions. In practice,
linearscalingisdifficulttoaccomplishfordeviceswithsubmicrondimensions
sincet,andt,~areusuallylimitedtoabout0.5ymand1OOArespectively.In
addition, L of all the interconnects does not scale uniformly as we discussed
previously in the wiring placement section.
In general, the effect of the line delay will become a problem when the
minimum dimension reaches below about 2 pm. The impact is less for FET
memory circuits than for bipolar logic circuits because of the bipolar
circuits more complex wiring structure. For the 3-level bipolar chip with
about 2 pm minimum dimension shown in Figure 2, the wiring delay
constitutesasignificant portionofthesystem processing time. Inaddition,
for VLSI applications, the chip dimension is usually enlarged in order to
accommodate the high device density which, when combined with a more
complx wiring structure, results in broadening of the overall length distri-
bution of the interconnects. This widens the distribution in the RC time
constants with substantial increases for the portion of the wires with long
lengths.
To minimize the RC delay, it is usually important to use materials with
low resistivityand permittivityto build the interconnectstructure. InTables
4 and 5 are summarized some of the physical propertiesforthe commonly
used conductor and insulator materials. *‘a** (The resistivities for thin films
of these metals are not given here since they depend in general on various
parameters, e.g. method of deposition and grain structure. They are about
20-40% higher for pure and large grain films of Al and noble metals but can
be 2 to 3 times higher for impure refractory metal films.) Because of their
excellent conductivities, it isclearwhy Al, Au and Cu are the most commonly
used metals. However, in certain applications, because of processing
requirements (e.g. the annealing temperature) or device design (e.g., the
high-densityself-aligned polycidegate), materialsof lesserconductivities,
such as refractory metals, silicides and even highly doped polycrystalline
silicon are used.
 Metallization for VLSI Interconnect 591

Table 4: Selected Properties of Metals

(Reference 21)
Bulk Coeflicient
Electrical or Thermal Thermal
Melting Resistivity Expansion Conductivity
Metal PoinL(“C) (10-Q-m) (10-6/w (W/mw

‘f% 960 1.6 19.7 418.4

Al 660 2.65 23.6 220

AU 1063 2.2 14.2 297.06

CU 1083 1.7 17.0 393.29

Pd 1552 10.8 11.0 71.13

PI 1774 10.6 9.0 71.13

MO 2625 5.2 5.0 146.44

W 3415 5.5 4.5 200.83

Ni 1455 6.8 13.3 92.05

Cr 1900 20 6.3 66.94

Table 5: Selected Properties of Insulators

(Reference 22)
Thermal
Thermal Conduc-
Dielectric Expansion Strength tivity
Materials Constantt (10-6/“c) w?SI) (CGS)

96% A120, 9.3 6.4 46.0 0.06

92% AI,O, 8.5 6.5 48.0 0.04

Electrical
5.5 4.4 13.0 0.004
Porcelain

SiO, 3.8 0.6 8.0 0.005

S$N, 6.0 3.0 85.0 0.08

AJ NI81 8.8 4.5 53.3 0.02

Glass-
Ceramic [7]

t Dielectric constant is defined as the ratio of permittiviry.

592 Semiconductor Materials

For the insulators, SiO, is the universal material used to form the
dielectric layer on circuit chips. It has a low dielectric constant of 3.5 and
can be produced with extremely low defect density by oxidizing the Si
substrate to a thickness as small as l OO-2OOA. This makes it well suited for
gate insulator applications although forsubmicron devices, there is some
question regarding the integrity of SiO,asagate insulatorforthicknesses
below 100A.23 For interlevel insulation, silicon oxide up to 2 ,um thick
produced by sputtering or evaporation (often not of the exact SiO, stoichio-
metry) is often employed. Si,N, is frequently used in combination with SiO,
in spite of its high dielectric constants, Its excellent mechanical strength
makes it well suited to serve as a lithographic masking material. Examples
of the Si,N,/SiO, combined layer can be seen in Figure 2.
Forpackagingapplicationsceramicsformed byvariouscombinations
of oxides, particularly Al oxides and Si oxides, are common materials. For
example, the multilayerceramic module shown in Figure8 employs materials
of several oxide mixtures. The ceramic materials have relatively high
dielectric constants (about 7-8) and have to be processed at elevated
temperatures (above 1500°C). Special, and often complex, processes
have to be developed for the application of this type of material forforming
multilayer structures. For example, high temperature processing neces-
sitates the use of metals with high melting points, such as the refractory
metals. This increases the response time of the system due to the high
resistivity of these metals. To circumvent these difficulties, polymeric
materials are being considered to replace the ceramics in chips as well as
in packaging.24 The main advantages of this class of materials are the low
dielectric constant (about 3.5, similar to SiO,) and the low processing
temperature (usually below 400°C). High-temperature polymers such as
Polyimides are used to satisfy processing requirements where thermal
stability up to 400°C is required.
Some of the problems relating to wiring delays for VLSI applications
have been discussed by McGreivy. 25 He has considered the change of the
access time for a static NMOS (N channel) RAM with decreasing design
rules. His results are shown in Figure 10. The access time decreases
continuously with shrinking device dimensions down to about 1.5 to 2 pm.
Below that, the effect due to the RC delay of the interconnect becomes
observable and its magnitude depends on the resistivity of the material
used. For refractory metal gates with sheet resistivities of 1 ohm per
squarecm(sheet resistivityequalsp/t,),adecreasein theaccesstimecan
still be achieved below 1.5 pm although the gain is very small. The access
time is doubled what one would expect to achieve in an ideal scaling
model. For resistive polysilicon gates with 20 ohm per square cm sheet
resistivity, corresponding to a 1 pm thick gate with 200 ohm-cm resistivity.
The access time increases with decreasing geometry due to the RC delay.
Theaccesstimebecomesaboutanorderofmagnitudemorethantheideal
case in the submicron range.
He has also considered the problem of parasitic capacitance. His
results for the variation of the capacitance components of interconnect as
a function of line width are shown in Figure 1 1. Of the three capacitance
components, only the metal-to-substrate capacitance, C,,, decreases
 Metallization for VLSI Interconnect 593

Refractory Metal (1 ohmlnw

Gate ____--
_____---
1&zzz?ng I I 1 IIlll
0’ ’
2 3 4 5 6 7 .3 910
0.5 I
Gate Length (microns)

Figure 10: Variation in the access time of a 4k NMOS RAM with decreasing de-
sign rule for gate interconnects with different resistivity (Reference 25).

with scaling. The edge capacitance is relatively constant while th parasitic

capacitance C,, increases with decreasing line pitch. The net effect is for
the total capacitance to increase in the submicron range, similar to the
resistance component although the effect is less. The end result is an
overall increase of the system access time.
There are other electrical problems related to wiring interconnects.
The broadening of the distribution in wire length mentioned already is
particularly important, The presence of afraction of long wires will increase
the overall time delay. The length variation also introduces nonuniform RC
response time. This disturbs the switch synchronization of the system,
whichcanbeaparticularlydifficultproblemforbipolarlogiccircuits.Asline
pitch decreases, inductance effect due to switching of adjacent lines
increases. This generates random voltage noise which can affect device
switching. Again, the problem is more serious for bipolar logic circuits.
Mostoftheseproblemscan bereduced byusingmultilayerstructureswith
wiring running orthogonally in adjacent layers. This approach is particularly
effective if combined with a statistically optimized wiring placement design,
such aswas mentioned previously. Multilayerstructures, however, require
long and complex processing steps, so the advantages will have to be
balanced against cost effectiveness and the overall design objectives.
 594 Semiconductor Materials

t-wm
+cw’ -+wm--.I
I

I
tfox
SiOz

Substrate
-C
7 me
-C
7 ms

2.0

I .5
C apacitance
(Relative

to c
ms
at 1 micron)
I .o

0.5

w m' ws
(microns)

Figure 11: Variation of components of interconnect capacitance with design

rules. The various components are defined in the upper figure (Reference 25).
 Metallization for VLSI Interconnect 595

MATERIAL REACTION

In the multilayer structure, various materials are integrated to serve

the designed function of the device. Interfaces are formed with different
combinations of materials, such as metal-metal, metal-insulator, metal-
semiconductor and semiconductor-insulator interfaces. In addition to the
interfaces, there are structural defects in thin films, such as grain boundaries
and dislocations. The close proximity of layers, the different material types
and the presence of structural defects are all factors contributing to mass
transport in the device structure. During processing or operation of the
device, atomic transport is further enhanced by the elevated temperature
as well as by the external driving forces, such as the applied voltage or the
current density. The resultant material reactions often change the device
characteristics, giving rise to reliability problems.
The concern for device reliability will become more important as
device dimensions are reduced and more complex multilayer structures
are used. For example, a reduction in the vertical dimension of interlevel
thickness will increase interfacial reaction which can result in junction
penetration as well as a change in the dopant profile at the contact.
Discussion in this section focuses on the characteristics of materials
reactions in multilayerstructures, emphasizing the roles of atomic mobility
and driving force as well as damage formation induced by flux divergence.
In a multicomponent solid, the atomic flux can be expressed generally
as

where c, is the mobile concentration of the ith element characterized by a

diffusivity D, at temperature T. The driving force Fi is derived from the
gradient of the chemical potential ,U~as

Fi = -vpi

The chemical potential pi can be expressed as

pi = kT In ci + pi(ci) + uivi + qi+i + . . .

where p, is written as originating from the concentration c,, the internal

chemical free energyp,(c,), and other external contributions, such asthose
from the stress ui and electric potential cpi; vi and q, are the atomic volume
and charge respectively. Consequently,

Fi = yVci-v{&))-oiei-qiEi

where E, and Ei represent the deformation strain and the electric field
respectively.
Inthisform,thedrivingforceinamulticomponentsystemcanoriginate
596 Semiconductor Materials

fromthreetypesofsources.Thefirstsourceisrelatedtotheconcentration
gradient which is generally recognized as the diffusion term. The second
force comes from the internal chemical energy gradient representing the
driving force associated with the change in the chemical form of the ith
element, e.g. the compound phase or the composition in a concentrated
alloy. The last type relates to external constraints such as an applied stress
u, or an electric field E,.
Combining Equations3 and5, it isclearthat the existence of an atomic
flux requires not only that the atoms move, i.e., D,#O, but also that there is a
nonvanishingdrivingforce.Thustheroleofthedrivingforceisasimportant
as the diffusivity although the present discussion will address mainly the
diffusivity issue since the variety of driving forces makes a systematic
discussion of the role of the forces difficult. (One exception is the later
discussion on electromigration.)
The existence of an atomic flux by itself is not sufficient to cause
damageformation. Inorderforthattooccur,alocaldepletionoraccumulation
of materials is required. This condition can be expressed by the flux
continuity equation as

dci Ci.-,P
-V.Ji + +
-Z=

where the rate of accumulation or depletion equals the negative flux

divergence plus the rate of dissipating the excess concentration ci-cio
from equilibrium (Z is the time constant for the process). In a bulksolid, the
flux divergence is usually generated by gradients of macroscopic para-
meters,suchastemperatureandstress.Inamultilayereddevicestructure,
it can originate from twoothertypes of inhomogeneities. One is associated
with the interfaces where two different materials join, and the other is due
to the presence of microstructural defects, e.g. grain boundaries and
dislocations. These two types of structural inhomogeneities provide high
diffusivity paths for mass transport which often give rise tofluxdivergence.
Grain boundary triple points or abrupt changes in grain size are well-
known examples of structural inhomogeneities. (See, for example, the
discussion in Reference 26.) For multilayered devices, such defects are
usually more important than the macroscopic ones since their effect on
atomic transport is significantly higher. Structural imperfections will become
even more important asfurtherdevicescaling producessteepergradients
in the structure as well as closer proximity of the interfaces.
The characteristics of diffusion in thin films have been reviewed by
Balluffi and Blakelyz7 and Gupta and HOBO. The diffusivities via various
defect structures can be summarized as a function of a homologous
temperature T/T,,,, where T, is the absolute melting point, as shown in
Figure 1 2zg. Using thisdata, therelativecontributionsof differentdiffusion
processes in thin films can be estimated. For metallic films in the device
operating temperature range of 0.3-0.6 T/T,, diffusion is dominated by
grain boundaries and dislocations instead of lattice defects (Figure 13).
For nominal films with grain size L in the 1 pm range, i.e. log(l/L) = 4, grain
boundaries usually dominate.
 Metallization for VLSI Interconnect

THE DIFFUSIVITY SPECTRUM -

FOR FCC. METALS

Tm/T

Figure 12: Summary of diffusivities via various types of structural defects. The
temperature scale is normalized to the absolute melting temperature T, (Ref-
erence 29).

6c T/T,,,=0.6,-----7 1 c T/Tm=O.5,__-_, 1

-6

0 2 4 6 8 IO 12 0 2 4 6 8 IO 12

Log @m-2) Log Qcm-2)

Figure 13: Regimes of grain size (gs.) and dislocation density Pd over which lat-
tice diffusion (I), grain boundary diffusion (b), or dislocation diffusion (d) is
dominant. The calculation is based on steady-state diffusion through a thin film
specimen of an fee metal as a function of the homologous temperature (T/T,)
(Reference 27).
598 Semiconductor Materials

The amount of grain boundary diffusion can be estimated from the

diffusiondistance(D,t)‘/*, whereD,isthegrain boundarydiffusivityandt is
the time. Known values of D, have been summarized for metal films in
Figure 1 4.30 Between 0.3T/T, and 0.6T/T,, D, is approximately 1 0-15-1 O-lo
cm*5’, taking the thickness of the grain boundary S to be lo-’ cm.
Accordingly, for a period of 1 O3 sec., the diffusion distance in the boundary
is in the range of .Ol to 1 pm. At higher temperatures, such as those used in
device processing, about 4OO’C, the diffusion distance can be one to
several orders of magnitude higher. Comparing these diffusion distances
with the dimensionsof submicron devicestructures, thediffusion distance
as estimated shows that atomic transport via structural imperfections in
about 10 min. is sufficient to cause material reaction throughoutthe device
structure. Thus it is clear that the high rate of diffusion is a basic reliability
problem in VLSI technology.
This has led to the use of diffusion barriers.31 The general approaches
include the use of single-crystal or epitaxial films, the use of amorphous
films, stuffing the boundaries with impurities or second phase particles,
and by imposing a barrier with a high activation energy for diffusion, e.g.
nitrides,carbidesoroxides. Exceptforthelastapproach which isclosetoa
true diffusion barrier, the others often achieve the results by changing the
nature of the structural defects instead of reducing the intrinsic rate of the
diffusion process.The use of refractory metalliccompound, e.g.TiN, will be
described later as an example of a barrier for reducing material reaction at
junction contacts.
The correlation between diffusivities and the absolute melting point
shown in Figure 12 provides a useful calibration for the relative thermal
stabilities of various materials used in interconnect structures. For example,
comparing Al (T,, 933”k) and refractory metals (e.g., T, of MO, 2983”k),
equivalent stability at 0.5 T,corresponds to200”CforAI but about 1200°C
for MO. For device structures requiring high-temperature reliability, the
refractory metals are significantly superior than Al and are often used in
spite of their high resistivity.

METALLIZATION RELIABILITY

Junction and Gate Contacts

The scaling results in Table 2 indicate the impact on junction properties
is to increase the contact resistance while reducing the junction depth.
This problem affects both Schottky diodes and ohmic contacts although
these two types of junctions have different reliability requirements because
of their specific circuit functions. The problem of contact resistance has
been investigated by several groups3* and the results are shown in Figure
15. The variation of the specific contact resistance R, with a dopant
concentration, N,, is comprised of two regions: the charge transport is
mainlycontrolled bythermionicemissionfor Nnlessthan 101gpercm3, but
by tunneling for N, more than 10lg per cm3. To reduce the contact
resistance, it is essential to operate in the tunneling region which requires
high dopant concentrations.
 Metallization for VLSI Interconnect 599

T(K) AS FRACTION OF T,,,(K)

0.9 0.6 0.7 0.6 0.5 0.4 0.3

(Ni-0.5Co)Au”(n)
\\

” 1.5 ” 2.0 ” 2.5 ” 3.0 ’ 3.5“I’ 4.0 4.5

T,,, /T(K)

T(K) AS FRACTION OF T,(K)

0.90.60.7 0.6 0.5 0.4 03

I I I I I
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Tm 1 T(K)

Figure 14: Plot of the grain boundary diffusivity against the reciprocal normal-
ized temperature T,/T for (a) data obtained by sectioning techniques in thin
films and some bulk materials and (b) data obtained by permeation techniques
in thin films (Reference 30).
600 Semiconductor Materials

300 K
- THEORY
. PISl -s,

-!- ( ,O”Ocm”* )

A
Figure 15: Theoretical and experimental values of specific contact resistance.
Note that for doping level exceeding 1019 per cm3, R, is dominated by the tun-
neling process while for doping level of 1017 per cm3, thermionic emission domi-
nates and R, becomes constant (Reference 32).

To see the effect of scaling, considera typical contact of PtSi on n-type

Si. Even for a high dopant concentration of 1 OIQcm-3 where conduction is
dominated by tunneling, the specific contact resistivity is about 1 Oe6 a-
cm2.Foracontactof3ymX3ymdimension,thecontactresistanceisabout
1Ofi. It will increase to 100 n when the contact size is reduced to 1 PmXl
~m.Anincreaseinresistanceofthismagnitudecandegradetheswitching
time and reduce the voltage swing to affect the normal device operation.
Since the increase is nonlinear with scaling (see Table 2), the problem
becomeseven moresignificantforsubmicronjunctions.Theusualremedy
forthe problem is to increase the dopant concentration to ensure conduction
by the tunneling mechanism. For example, when the doping of the PtSi
contact is increased to 10zo cmm3, the resistivity is reduced by about a
factorof about 105. Contact junctions with such high dopant concentrations
have many material problems, such as the stability of the dopant profile
during processing and interfacial resistance due to contamination. Thus
one can readily understand the extensive recent interest in studying the
formation of shallow contacts with high dopant concentrations.
The concern for the selection of a metallizaion scheme extends
 Metallization for VLSI Interconnect 601

beyond the initial formation of shallow contacts. Particularly important in

this regard are the thermal stability of the contact and the retention of
shallow junction profiles during processing. It as been recognized that the
usual method of using Al to form junction contacts has severe limitations
for VLSI applications. The difficulty arises from Al penetration of the
junction as a result of the formation of Al spikes caused by Si dissolution
into A133.This is a particularly significant problem for shallow contacts
since it induces leakage current which, in severe cases, can short the
junction electrically. The incorporation of Si into Al to alleviate junction
penetration proves to be ineffectiveforshallow contacts since the precipi-
tation of Al doped Si at the contact interface gives rise to high contact
resistance.34
These problems led to the use of silicides to prevent Al penetration of
junction contacts. Silicides are compound phases usually formed by
reacting a deposited layer of transition metal with Si.35 Silicides have two
important advantagesforforming junction contacts. First, the formation of
a silicide establishes a silicide-silicon interface below the original metal-
silicon interface, thus producing a junction interface free of processing
defects and contamination. Second, the amount of silicon consumed can
be limited by restricting the annealing time in the formation of silicide
contacts to shallow implanted junctions.
Silicides have several other material characteristics useful for integrated
circuit applications.36”7 First, some silicides have electrical conductivities
exceeding heavily doped polysilicon by several orders of magnitude. The
resistivities of silicides formed on polysilicon38 are summarized in Table 6.
Second, it can be oxidized. And third, different metals form silicide Schottky
diodes with barrier height varying from 0.5 to 0.9 eV. The combination of
these material characteristics extends the usage of silicides beyond
contact metallurgy into other VLSI applications. Notably among these are
the use of silicidesfor interconnecting lines, the formation of low and high
barrier diodes in Schottky transistor logic circuits and in combination with
polysilicon for self-aligned bipolar contacts and MOS gates.3g
The use of silicides is not free of metallurgical problems. Particularly
relevant are the thermal degradation of the silicide contact40s41and reliability
problems associated with stress generated due to silicide formation.42
Thermal degradation is a particular concern fortheAl/silicide/Si structure
when subjected to post-metallization annealing. This step is often required
for removing process-induced damage in the insulator or during deposition
of passivation layers. Depending on the process, the temperature can
exceed 500°C for an hour or longer. The basic problem which has been
recognized for some time40 is caused by the phase instability of silicide in
contactwithAL41 Thedissociationofsilicideisdriven bytheformationofan
Al-transition metal compound with a higher thermodynamic stability than
the silicide. This precipitates the dissociated Si (p-doped by Al) on the
silicon substrate, causing changes in the junction characteristics. The
sequence of steps in the degradation of theAI/Pd,Si/Si junction is illustrated
schematically in Figure 16. This mechanism of junction degradation is
similar to the degradation of AI(Si contacts. Thus, it appears that the
silicide serves only as a “sacrificial” barrier to delay the reaction between
602 Semiconductor Materials

Table 6: Resistivities of Various Silicides Formed on Polysilicon

(Reference 38)

Method of Sintering Resultant

Silicide Formation Temperature Resistivity
(“C) (rS1-cm)

TiSi2 Metal on Polysilicon 900 13-16

Cosputtered Alloy 25

ZrSi2 Metal on Polysilicon 35-40

II 45-50
HISi,

VSiz 50-55

NbSiz 50

TaSiZ 900, 1000 60-70, 35-40

Cosputtered Alloy 900 or 1000 50-55

C&i2 Metal on Polysilicon 700 -600

MoSiz Cosputtered Alloy 1000 -100

II 1000 -70
WSiz

FeSi Metal on Polysilicon 500 150-200

8, >lOOO
FeSi, 700

CoSi2 Cosputtered Alloy 25

NiSiz Metal on Polysilicon 900 -50

Cosputtered Alloy -50-60

PtSi Metal on Polysilicon 800 28-35

Al and Si, leaving the nature 0; junction degradation unchanged. The

thermal stability of the Al/silicide/Si system has been reviewed recently by
Wittmer.43
Ironically, this necessitates the use of another barrier to protect the
silicide layer from reacting with Al. Two approaches have proven to be
effective. One is to incorporate a thermally stable intermediate layer, such
as TiW44 or TiN45 while the other is to use phase separation to form the
barrier layer during silicide formation. 46 For example, if a PdW mixed layer
is used to form the contact, Pd,Si will form at the contact upon annealing
due to its faster reaction kinetics and W will separate out to form a
protective layer. In addition to being a single-step process, the consumption
 Metallization for VLSI Interconnect 603

SCHEMATIC PRESENTATIONOF
AI/Pd$i/Si REACTION

Pd+Si

a) INITIAL STAGE

AI/Pd
COMPOUND
IZFFU A13Pd4Si
Pd2 Si
‘:nSI ’ / l’ 7
::,
b) INTERMEDIATE STAGE

c) FINAL STAGE

Figure 16: Schematic presentation of the different reaction stages in AI/Pd,Si/Si

junctions. Note that Si precipitate can reach the contact interface before the PdlSi
layer is completely consumed by passing through pinholes existing in the PdzSi
layer as shown in b) (Reference 41).

of silicon can be limited by reducing the concentration of the reacting

element in the mixture. A structure making use of aTiW barrier in a bipolar
device with a PtSi contact is shown in Figure 17a.
The problems associated with gate metallization systems differ from
those of contacts because the metal is not in contact with Si. Since device
density is important for MOS devices, more emphasis is placed on the
patternability and geometrical aspects of the structure, such as edge
coverage. There is a need, in addition, to reduce the resistance of the
polysilicon gate line to improve the switching time. For this purpose, the
approach of using a silicide-silicon combined layer, polyicide, has been
604 Semiconductor Materials

BURIED LAYER

(b)

Figure 17: Schematic cross sections of silicide contacts to (a) bipolar and (b)
MOS devices. Note also in (b) the combined use of silicide and polysilicon for
gate metallurgy (from Reference 43).

widelyaccepted.47OnecancomparetheresistivitiesofsilicidesinTableVI
to those of metals in Table4. In Figure 17b, an example of a polyicide gate
used in a recent MOS device is shown.

Electromigration
Electromigration describes the movement of atoms in a metallic
conductor induced by the passage of a direct current. Its magnitude is
determinedbytheatomicdiffusivityandthecurrentdensity. Electromigration
induceddamageintheformofopensorshortsintheinterconnectlinesisa
result of a local divergence of the mass flux. This divergence can be
generated by various types of inhomogeneities, such as those from grain
size variation local heating and stress gradients.48
With regard to electromigration, the main impact of scaling is to
increase the current requirements of interconnecting lines. This problem
has two basic aspects, onefrom the increase in the current density and the
other from the reduction in device dimensions.4g From Table 2, the current
density is seen to increase linearly with the scaling of MOS devices and
 Metallization for VLSI Interconnect 605

more than linearly for bipolar devices. This increases the driving force for
electromigration as well as the Joule heating generated in the conductor.
With the heating increase asj*p, the effect can be significantly higherthan
the driving force coming from the linear increase in j. The combination of
these factors can raise the conductor temperature giving rise to higher
atomic diffusivity and electromigration flux. This problem, together with
the increased powerdensity, necessitates an improvement in heat dissipa-
tion during device operation. The combined effect of these factors will
inevitably cause the electromigration flux to increase beyond thatcaused
by the increase in current density alone.
The increase in the current density can be estimated based on the
trend in device dimensions. For present devices with dimensions of about
3 pm or larger, the current density can reach 2 X 1O4and 5 X 1 04A/cm2for
MOS and bipolar devices, respectively. For the next generation of devices
with minimum line dimensions in the range of 1.5 to 3 pm, j increases to
about 5-l 0 X 1 O4 for MOS and 2-4 X 1O5 for bipolars devices. This trend
continues and can result in j exceeding lo5 and lo6 respectively, for
submicron MOSand bipolardevices.Thisisan increaseof 102-103timesin
the current density. Since an isolated metal wire can carry only about 1 O4
A/cm2 before melting, the Joule heating generated in a line carrying 1 O5
A/cm2 must be almost completely removed through the substrate and/or
the passivating overlayer. When the current reaches ~10~ A/cm2, any
imperfection in the substrate, such as processing defects or interfacial
barriers, can cause thermal runaway todestroythe line. Even without such
a catastrophe, the heating effects of such high current densities will
increase the rate of electromigration, resulting in a significant reduction in
the lifetime. In practice, this is reflected by an increase in the exponent n in
the lifetime equation of t,,=Aj-” exp (AH/IV)outside the normal range
between 1 and 2. This effect adds considerable difficulty in extrapolating
the lifetime under operating conditions for submicron lines from results
obtained in accelerated stress tests50
The otherelectromigration problem duetosize reduction isgeometry-
related and caused by scaling into the submicron range. For metal films, it
is generally observed that the grain size is about the same as the film
thickness. For a 1 p thick film, the common thickness of interconnecting
line, there will be only a few grains spanning across a l-3 pm wide line. At
the device operating temperature, the electromigration flux is confined to
grain boundaries. With a small number of the grains across the line, each
individual divergent site in the grain structure becomes potentially more
damaging since a line can fail without requiring a statistical linkage of
several divergent sites, as would be the case of a line many grains across.
This shortens the conductor lifetime while increasing the randomness of
the failure statistics, i.e. increasing the statistical deviation ain the lifetime.
Both trends have been observed in lifetest@’ as well as in computer
simulation for linewidths down to about 2 pm52. This effect is significant
since the extrapolated lifetime for device operation can be significantly
reduced by an increase in u.
Another effect which results from the increase in the grain size-to-line
width ratioisadecreaseintheroleofthegrain boundaryinmasstransport.
606 Semiconductor Materials

Particularly for multilayer structures, scaling in the line width causes a

reduction in thegrain boundary area per unit line length relative tosurface
and interface areas. This increases the relative contributions of surfaces
and interfaces53 to mass transport. Since these structures have diffusivities
generally exceeding that of grain boundaries, the total electromigration
rate will be increased accordingly. Even though electromigration at surfaces
and interfaces has seldomly been studied, the effect can be estimated
fromtherespectivediffusivities.Asseenfrom Figure1 2,atabout05T,,the
surface diffisivity is about 1OX that of the grain boundary diffusivity. Thus,
the total electromigration rate can be substantially increased in the multi-
layer structure if the surface and interface contribute.
In addition to the two aspects of electromigration discussed already,
one new area of concern emerges, namely the behavior of device contacts
and step coverage. In certain applications, e.g. the emitter contact in
bipolar devices, performance enhancement in scaling requires as much
dimension reduction as possible. Consequently, the emitter contact can
be subject to current densities exceeding lo5 A/cm2. This problem is
complicated by two factors. First, the contacts are often formed using a
combination of materials such as silicides and polysilicon. And second,
current crowding usually occurs when current flow converges vertically
into a contact. The combination of these factors will change the nature of
the divergent site, Joule heating and the local electromigration flux.
Consequently, theformation of electromigration damage at thesestructural
elements can be basically different from that of a metallic conductor line.
Very few studies on this aspect of electromigration have been reported,
particularlyforsmall geometriesof interest toVLSl applications. Although
a recent investigation54 of AI/Si contacts reported severe effects due to
current crowding and Joule heating.
Studies on electromigration and life tests have been reviewed.48*50
While most of these investigations have focused on Al-based metallurgy
for line widths more than 2pm, two systems have been developed for fine
linesbelow2pm.Oneis basedonagrainstructuremodificationoftheAlCu
metallurgy.55 Using a low Cu concentration of 05wt.% and suitable anneal-
ing conditions, Al lines with “bamboo” like grain structure can be formed.
With the grain boundary placed normal to the current flow, grain boundary
electromigration is greatly reduced. Lifetime of such lines at 5 pm was
found to improve by an orderof magnitude overthe same material without
specifically oriented grains. The lifetime showed a significant upward
trendwith the decrease in linewidth below2 pmalthough thecorresponding
aseemed to increase. The observed increase in the lifetime is opposite to
otherstudies51v52 and was attributed toan improvement in the uniformity of
grain structures in the line. The other approach taken was to incorporate
an Al-transition metal intermetallic sandwich layer in the AlCu structure.56
The intermetallic compound was formed by reacting Al with a thin layer of
transition metal, e.g. Crand Ti. The intermetallic layerwasfound to improve
the AlCu grain texture and also serve as a barrier forvoid linkage to the top
and bottom AlCu layer. Between l-2 pm, the lifetime was found to improve
50-l 00 times in comparison to AlCu while u remained almost unchanged.
 Metallization for VLSI Interconnect 607

SUMMARY

In this chapter, the fundamental aspects of metallization schemes for

VLSI interconnects were discussed by considering system requirements
and material characteristics.Toassesssystem requirements, theincrease
in wiring complexitywasfirst explored asastatistical optimization problem.
With device dimensions approaching 1 pm, wiring placement becomes
a dominant factor in the design of the chip layout and packaging structure.
For the design of VLSI interconnects, device scaling brings forth a set of
requirements in addition to those from wiring placements. The impact was
assessed by considering the scaling rules for FET and bipolar devices,
emphasizing the increasing demands on the functional requirements of
the interconnect metallization. The discussions on material characteristics
focused on the electrical and thermal properties with emphasis placed on
the basic parameters including electrical resistivity, dielectric constant
and diffusivity.
Thiswasfollowed by a discussion of two important reliability problems
in metallization, junction contacts and electromigration. The projection
based on the scaling rules makes it clear that as the device dimension
approaches about 1 pm, there will be serious materials problems for
junction contacts and electromigration. There are two aspects of the
problem. The first is material-related because of the use of new materials
and the othergeometry-related. Some approaches used todeal with these
two problems have been described.
Compared with otherfactorswhich can potent’ially limit VLSI develop-
ment, such as those imposed by the basic physics of the devices, inter-
connect metallization seems to be of immediate concern and will become
increasingly important. The future development of VLSI may well depend
on how successfully these problems. can be overcome.

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2. R.H. Dennard,J. Vat. Sci. Techno/. 19537 (1981).
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11. B.S. Landman and R.L. Russo, IEEE Trans. Compuf. C-20:1 469 (1971).
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608 Semiconductor Materials

13. W.D. Grobman, J. Vat. Sci. Technol. A3:725 (1985).

14. A.J. Blodgett and D.R. Barbour, IBM J. Res. and Develop. 26:30 (1982).
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17. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous and A.R.
LeBlanc, /EEE J. Solid Stafe Circuits SC-g:256 (1974).
18. D.D. Tang and P.M. Solomon, IEEE J. So/id State Circuits: SC-1 4, 679 (1979).
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by D.F. Barbe, Springer-Verlag (1982). Chp. 2.
20. See, for example, B. Hoeneisen and CA. Mead, So/id State Electronics, 15819
(1972); ibid 15981 (1972).
21. Metals Handbook, 8th Ed. Vol. 1, Am. Sot. for Metals (1961).
22. B. Schwartz in Electronics Packaging Materials Science, p. 49, (E.A. Giess, K.N.
Tu and D.R. Uhlmann eds.) Materials Res. Sot., Pittsburgh (1985).
23. D.J. McGreivy in VLSl Technologies (D.J. McGreivy and K.A. Pickar eds.) p. 21 l-
224, IEEE Computer Society Press, Los Angeles (1982).
24. D.J. S~aphim, L.C. Lee, B.K. Appelt, and L.L. Marsh in Electronics Packaging
Materials Science p. 21, (E.A. Giess, K.N. Tu and D.R. Uhlmann eds.)
25. D.J. McGreivy in VLSl Technologies (D.J. McGreivyand K.A. Pickar eds.) p. 185
197, IEEE Computer Society Press, Los Angeles (1982).
26. F.M. d’Heurle and R. Rosenberg, Phys. Thin Films, 7:257 (1973).
27. R.W. Balluffi and J.M. Blakely, Thin So/id Films, 25:363 (1975).
28. D. Gupta and P.S. Ho, Thin So/id Films, 72:399 (1980).
29. N.A. Gjostein in Diffusion, p. 241, Am. Society for Metals, Metals Park, Ohio
(1973).
30. D. Gupta, D.R. Campbell and P.S. Ho in Thin Films: lnterdiffusion andReactions
(J.M. Poate, K.N. Tu and J.W. Mayer eds.) p. 161, Wiley, New York (1978).
31. P.S. Ho, Thin SolidFilms 96:301 (1982); R.S. Nowicki and M.A. Nicolet, Thin Solid
Films 96:317 (1982).
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AY.C. Yu, So/id State Nectronics 13:239 (1970).
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34. H.C. Card in Metal-Semiconductor Contacts, Inst. of Physics Conf. Series No. 22,
Manchester, England (1974).
35. K.N. Tu and J.W. Mayer, in Thin Films: lnterdiffusion and Reactions, ed. by J.M.
Poate, K.N. Tu and J.W. Mayer, Wiley-Interscience (1978). Chp. 10.
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37. S.P. Murarka, J. Vat. Sci. Technol. 17, 775 (1980).
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Dev. ED-27:1409 (1980).
39. CM. Osburn, M.Y. Tsai, S. Roberts, C.J. Lucchese and C.Y. Ting in VLSI Science
and Techno/ogy/7982, ed. C.J. Dell’Oca and W.M. Bullis, The Electrochemical
Society, Inc. (1982), p. 213.
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Bullis. The Electrochemical Society Inc. (1982), p. 194.
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44. J.A. Cunningham, P.R. Fuller and CT. Haywood, IEEE Trans. Reliab. 19:182
(1970).
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46. KN. Tu, J. Vat. Sci. Technol. 19:777 (1981).
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47. C.Y. Ting, SS. lyer, C.M. Osburn, G.J. Hu and AM. Schweighart in VLSI Science
and Technology/7982, ed. C.J. Dell’Oca and W.M. Bullis, The Electrochemical
Society, 1982, p. 224.
48. F.M. d’Heurle and P.S. Ho in Thin films-lnterdiftusion and Reactions. ed. by
J.M. Poate, K.N. Tu and J.W. Mayer, Wiley Interscience (1978). Chp. 8.
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51. G.A. Scoggin. B.N. Agarwala, P. Peressini and A Browillard, Proc. 13th. IEEE
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10
Characterization of Semiconductor Materials

Gary E. McGuire
Tektroni& incorporated
Beaverton, Oregon

.Characterization of semiconductor materials frequently conveys the

imageofanalyzingthesinglecrystallinesubstrate.However,semiconduc-
tor materials include a broad range of high purity gases, solvents, metals,
organics, dielectrics and single crystalline substrates. The analysis of
these materials requires an extensive array of analytical tools in order to
fully characterize them. Even a brief introduction to this array of tools is
beyond the scope of this chapter. Instead, a short description of some of
themorepopularanalytical techniqueswill begivenwiththemajorempha-
sis being placed on those techniques which provide physical and chemical
information.
The ultimate goal of semiconductor device production is to produce
components with theappropriateelectrical properties. Due to the reduced
size of theelectricallyactive region ofVLSl devices, the numberof impurity
and dopant atoms allowed is extremely small, quite often below the
detection limit of ma iyanalytical techniques. Collectively, theseelements
produce ek..rronic states within the semiconductor band gap which
impact device performance, yield and reliability. The interaction of chemi-
cal impurities with physical defects can result in precipitate formation and
stacking fault generation, both of which influence the mechanical and
electrical properties of the substrate.
The presence, location and role of dopantsand adventitious impurities
are highlydynamic.Thesubstitutionalorinterstitallocationsforimpurities
are only two of the many possibilities that arise when impurities interact
with defects in the crystal lattice. Device processing, especially at elevated

610
 Characterization of Semiconductor Materials 611

temperatures, constantly changes the microstructure of the device which

can induce both desirable and undesirable electrical properties depending
on the location in the wafer.
Asaresult,characterizationstrategiesmustconsiderthenatureofthe
material, the impurity level and distribution, microstructure and electrical
properties. Since each analytical tool provides only a small segment of the
necessary information, a series of techniques may be required. This
chapter illustrateswhere some of the more popular analytical tools may be
applied and the type of information that may be obtained from them.

SURFACE ANALYSIS TECHNIQUES

Auger Electron Spectroscopy

Figure 1 shows an energy level diagram which depicts the Auger
Electron (AE) process. Incident photons, electrons or ions with sufficient
energy will create a core hole through the excitation of an ionizing photo-
electron.’ The atom, left in an excited state, de-excites through the emission
of x-rays or Auger electrons which are characteristic of the energy levels

PHOTOELECTRON
AUGER ELECTRON
OR
IONIZING ELECTRON -(KQL2,3)

AUGER ELECTRON: EKL,L~~ =EK-EL,-EL~,~ 4

PHOTOELECTRON: EpE =hl'l -EK- +

X-RAY FLUORESCENCE: hYf = EK-EL

t

Figure 1: Energy level diagram describing the processforthe emission of Auger

and photoelectrons.
612 Semiconductor Materials

involved. For example, the kinetic energy of the Auger electron illustrated
in Figure 1 is typically described as

E = E, - E,, - E, - r$
KL1L2.3 213

where EK is the energy of the ionized core level, Et, .is the energy of the level
from which the electron originates to fill the inmal core hole, E~23 is the
energy level from which the Auger electron originates and C#Iis the work
function. Multiplecharacteristic Augertransitions may beobserved due to
the various core energy levels available for photoexcitation and the multiple
combination of energy levels available for de-excitation and Auger emission.
TheAugerelectronisusuallydescribed bythethreeenergylevelsinvolved
in its emission. Figure 1 depicts the KL, L,, Auger transition.
The kinetic energy of the AE is independent of the excitation source.
As a result, the tendency has been to use electron beams in the l-20 KV
potential energy range for excitation. Electron beams are the preferred
excitation source because they can be focused to a small spot size and
deflected to a region of interest on the sample.
The AE transition is characteristically a small feature sitting on a large
background of inelastically scattered electrons.2 The most prominent
feature in the electron spectrum is the contribution due to backscattered
electronsfrom the primary beam.Thedata has been presented historically
in the dN(E)/dE versus E format as a means to enhance the Auger signal.
More recently the data has been presented in the N(E) versus E due to the
availability of computers for background subtraction.
Figure 2 shows a schematic diagram of an Auger spectrometer. The
optics for the primary beam are coincident with the cylindrical mirror

Figure2: Schematic diagram of a cylindrical mirror analyzer Auger spectrometer.

 Characterization of Semiconductor Materials 613

analyzer. In most modern spectrometers a LaB,filament is used to provide

high brightness. Spatial resolution of from 25-50 nm may be achieved by
sacrificing beam current and sensitivity. A secondary electron detector is
incorporated to facilitate locating the electron beam on the sample areaof
interest.
The focal point of the electron optics and the electron spectrometer
are designed to be identicaL3 When a sample is positioned at the focal
point, the electron beam irradiates the surface, giving rise to the Auger
electrons which pass through the acceptance slits into the spectrometer.
A negative potential applied to the outer cylinder of the spectrometer
deflects the electrons through the exit slit onto the electron multiplier. By
sweeping the voltage on the outer cylinder, the electron energy spectrum
may be scanned.
The shallow escape depth or inelastic mean free path of electronsas a
function of energy is the factor which gives AES its surface sensitivity,
Figure 3.4 In the range of interest, from O-2000 eV, the inelastic mean free
path (IMFP) is only a few monolayers. Although many studies have been
conducted to more accurately determine the IMFP, there is still a large
uncertainty in this function.
Characteristic Augertransitions may be observedforall elements with
three electrons or more. As a result AES is often used to survey the surface
compositionof materials. Forexample, Figure4showsanAESspectrumof
the surface of a Si wafer coated with an Al layer that is doped with
approximately 4% atomic Cu, after etching in a Ccl, plasma. The plasma
etch removes the Al but leaves residualcu since it does not have the same
volatility as Al. The Cu rich residue is only a few monolayers thick and as a
result can only be detected by surface analysis techniques such as AES.

1 10 100 1000

EnergyWI
Figure 3: Plot of electron inelastic mean free path versus energy which illustrates
the shallow sampling depth of the electron spectroscopies.
614 Semiconductor Materials

L Cl

-1 , I I I I I1 I I I I I I Il.1 1 I
200 400 600 800 1000 1200 1400 1600 1800 2000

ELECTRON ENERGY ,eV

Auger spectrum of residue left after plasma etching a copper doped

aluminum layer in CCi4.

Bycombiningthesurfacesensitivitywith ionsputtering, depth profiles

of the elemental composition may be generated.5 This is accomplished
throughtheuseoftheiongunshowninFigure2.Theiongun bombardsthe
surface with a flux of inert ions in the 2-5 keV range, removing controlled
amounts of material due to the transfer of momentum from the impinging
ions to the surface atoms. By monitoring the Auger signal intensity of
selected elements as a function of sputtering time a plot can be generated
which represents the concentration asafunction of depth. Figure 5 shows
thein-depthprofileofamultilayeredsampleofchemicallyvapordeposited
SiXN, on thermally grown SiO, on a Si substrate.6 For amorphous materials,
the profile of the boundary between succeeding layerscan bequitesharp.
Artifacts of the sputtering process may arise due to a variety of factors,
however, the information gained as a result of an in-depth profile with a
resolution of 20-50A usually outweights the disadvantages.
Auger spectra usually contain features which are characteristic of the
surface chemistry of the system under investigation as a result of the
participation of the valence band electrons in the Auger process. These
features have been studied for many systems and may be used in combi-
nation with the elemental composition as a means to identify the chemical
oxidation state. Figure 6 illustrates the change in theGa L,M,,M,, Auger
electron kinetic energy and line shape in two chemical different chemical
environments7TheGaAugerpeakisshifted by4.9eVfortheoxideformed
on GaAs by anodic oxidation relative to the energy observed for the
underlying GaAs substrate. A similar shift of 5.8 eV is observed for the As
L,M,,M,,AugertransitionforAsin theanodicoxiderelativetoAsinGaAs.
Chemical shifts of this magnitude have been observed for most elements.
Since the spectral features are complex and the magnitude of the chemical
 Characterization of Semiconductor Materials 615

SPUTTERING TIME
(min)
Figure 5: Auger depth profile of chemically vapor deposited Si3N4 on thermally
grown SiOz over Si.

I I I

L3%,5M4,5

%GaAs) Ga(Ga203)

WI/E
1525
(Ga2(

I I I I
055 1080 1105
KINETIC ENERGY (eV)

Figure 6: Gallium Auger lineshapes for anodic oxide grown on GaAs.

616 Semiconductor Materials

shift relatively small it is not simple to determine the composition of

multicomponent systems.
Since the primary electron beam can be focused to a small spot and
rastered scanned over the surface, elemental distribution maps may be
obtained of the surface composition. This is accomplished by fixing the
pass energy of the spectrometer so that only one transition is being
monitored. If more than one element is of interest sequential elemental
distribution maps may be generated as shown in Figure 7. One typically
looks for inter-relationships in the maps as an indication of compound
formation, corrosion, etc.s When the Auger transitions exhibit features
which are indicative of certain oxidation states these may be mapped out
aswell. Elemental orchemicaloxidationstatedistribution mapping may be
combined with ion sputtering to generate a three dimensional picture of
the sample.
AES has been a powerful tool in the investigation of a wide range of
materials problems in thesemiconductor industry. One application forwhich
AESisparticularlyweIIsuited isthestudyof diffusion inthinfilms. Figure8
illustrates schematically the three diffusion processes encountered in
thin polycrystalline films. Grain boundary diffusion transports material
from the underlying substrate through a thin polycrystalline film more
rapidly than bulk diffusion. Rapid surface diffusion then distributes the
material across the specimen. Surface analytical techniques like AES
have been used extensively in the investigation of diffusion in thin metal
couples used in thesemiconductor industry. This may beaccomplished by
monitoring the surface composition while annealing the sample in-situ to
determine the arrival time and increase in concentration of the diffusing
species. Byannealingatdifferenttemperatures,onecangenerateaseries
of curves of surface concentration versus annealing time from which an
Arrenhius type plot may be generated.g An alternate approach which has
been used is to anneal a series of samples at different times at a fixed
temperature then profile through the film to determine the extent of
interdiffusion.‘O
AES has a detection limit of approximately0.1 %atomicor 1 018atoms/
cm3 in Si with a sensitivity variation of 50-l 00 across the Periodic Table.
Several handbooksofAugerdataproviderelativesensitivityfactorsforthe
elements which may be used to quantify experimental results.” There
remainsextensiveworkthatneedsto bedone, however, beforeAESistruly
aquantitative technique. In addition, even though AES has relatively poor
sensitivity, it is one of the more popular analysis techniques for the
evaluation of surfaces and interfaces.
AES may beutilizedon awidevarietyof materials, but duetotheuseof
an electron beam forexcitation it does have limitations. The electron beam
and ion beam used for sputtering may induce sample decomposition. This
problem is accentuated by the high current densities that occurwith small
probe diameters. Insulating materials may be difficult to evaluate due to
sample charging effects. The inbalance of currents from the primary beam,
the secondary electrons and the sample result in asurface potential which
distorts the Auger electron energy.
 Characterization of Semiconductor Materials 617

Figure 7: SEM image and 0 and S scanning Auger maps of zone refined Fe foil.
The numbers indicate the approximate orientation of the surface normal of the
various grains.
618 Semiconductor Materials

SURFACE
DIFFUSION

Figure 8: Schematic diagram of the diffusion paths in thin polycrystalline ma-

terials.

Photoelectron Spectroscopy
Photoelectron spectroscopy is a technique which has many similarities
toAES.ThesameenergyleveldiagramusedtodescribetheAugerprocess
may be used to describe the photoelectron process.12 Excitation of the
ionizing photoelectron may be accomplished through the use of a variety
of energetic photons orcharged particles. The primary focus in this text will
be on monochromatic x-ray excitation of photoelectrons (XPS). Use of a
monochromatic excitation source is essential to this spectroscopy, since
the photoelectron’s kinetic energy is directly dependent on the energy of
the excitation source. By knowing the energy of the x-ray with a high
degree of accuracy and measuring the kinetic energy (KE) of the emitted
photoelectron from the relationship:

BE= ho-KE+@ (2)

one can determine the binding energy (BE) of any electron energy level
less than the photon energy.
A variety of electrostatic electron energy analyzers have been pro-
duced commercially. One of the most popular is the cylindrical mirror
analyzer, Figure 9, similar to that used for AES. A two stage, two cylindrical
mirror analyzers in tandem, device is employed to enhance the energy
resolution. An x-ray source, either an Al or Mg anode, mounted in proximity
to the sample is used for excitation. The x-rays flood a broad area of the
sample since they, unlike the electron source in AES, can not be easily
focused. The acceptance angle of the spectrometer determines the area
of analysis, which is typically a few millimeter diameter circle. With adjust-
able aperture slits the sampled area may be reduced to a few hundred
micrometers.
Figure 10 shows a schematic diagram of another common variety of
XPS spectrometer. It employs an x-ray monochrometer to enhance the
x-ray line width, eliminate satellite x-ray lines and focus the x-rays. The x-
 Characterization of Semiconductor Materials 619

Precision Analyzer

Sputler Ion Gun

Figure 9: Schematic diagram of a two stage cylindrical mirror analyzer and x-ray
source used for XPS.

NONOCHRO!CATOR
CRYSTAL

HEKISPHrRICkI.

ELECTRON GUI

Figure 10: Schematic diagram of a XPS system utilizing a bent quartz crystal x-
ray monochrometer in conjunction with an electrostatic lens and hemispherical
analyzer.
620 Semiconductor Materials

rays from an Al anode are allowed to diffract off of a bent quartz crystal
before interacting with the sample. The natural Al x-ray linewidth is approxi-
mately0.9 eVwhile that of the monochromizedsource is approximately0.4
eV.13Thefocusing propertiesofthemonochrometerproduceaspotsizeof
approximately 150 micrometers. l4 Due to the loss in x-ray intensity in
going through the monochrometer, most spectrometers of this type employ
an electrostatic lens to increase the collection efficiency of photoelectrons
going into the hemispherical analyzer and a position sensitive, multiple
array, detector to enhance the count rate.
Photoelectron spectrometers employ ion guns for in-depth profiling
as in AES. Since the area of analysis is much larger than in AES, the ion
beam isdefocused inordertogeneratea uniform ionflux.Thisreducesthe
ion etch rate but does not prevent one from monitoring signal intensity as a
function of ion sputtering time. In addition, many XPS systems have both x-
ray and electron beam sources for combined multi-technique analysis by
XPS and AES.
Figure 11 shows the Ag3d photoelectron spectrum. The trace illustrates
the relative simplicity of the spectra. The spectral features are Gaussian-
like sitting on a low background. The spin-orbit splitting of the energy
levels, in this case the 3d,,, and 3d,,,, is well characterized and easy to
recognize due to the predictable intensity ratios. The spectra are usually
plotted in the N(E) versus BE format even though the energy analysis is of
N(E) versus KE. Each element exhibits a unique set of photoelectron (PE)
transitions corresponding to its atomic energy levels. The PE transitions
are a function of atomic number so that the energy levels of adjacent
elements in the Periodic Table are all shifted to higher binding energy.
As suggested by this unique set of binding energies, XPS is a good
elemental surface analysis technique. Figure 12 shows a spectrum from a

0’
380 375 370 365 360

BE, eV

Figure 11: XPS spectrum of the Ag3d transition showing the spin-orbit splitting
into the 3d512 and 3d312 components.
 Characterization of Semiconductor Materials 621

SILICON SLICE WITH RESIWAL OXIE

I I I I I
si2p
- Boo- Si0#4,3eV S1,99.8eV
ts
cvl
Z
2
2
z
2ii400-
55
sw

Oh
I I I I I
110 106 102 94
BINDING ENERGY%)
Figure 12: XPS spectrum of a Si surface with the native oxide showing the
chemical shift in the Si2p transition.

clean Si wafer to illustrate this point. Two Si2p transitions are observed,
one for elemental Si and one for the native oxide formed on the wafer as a
result of air exposure. One can get a feel for the surface sensitivity of XPS
since the native oxide thickness is typically less than 30A. The surface
sensitivity, as in AES, is controlled by the inelastic mean free path of the
electron as illustrated in Figure3, rather than the path length of thex-rays
used for excitation.
The ability to distinguish different oxidation states, as in thecase of Si
and SiO,, has been one of the recognized strengths of XPS. These chemical
shifts in the core level binding energies are due to changes in the valence
electrondensityduetocompoundformation.Although,thechemicalshifts
maybeaslargeas10-12eV,thereisfrequentoverlapformanycompounds
as illustrated in Table 1.15 However, there are many sources of chemical
information in the spectra. The sources include first the identification of
the elements present and their relativeconcentrations, then thechemical
shift of the cation to determine its approximate oxidation state and finally
the chemical shift of the anion to determine its oxidation state. Table 2
illustrates the magnitude of the chemical shifts observed for anionic
species X-*, X0,-* and X0,-* when X is S, Se and Te.16 Combination of this
information gives a detailed picture of the chemistry of the surface under
investigation in many cases. There are other spectral features which
provide additional chemical information but which are too detailed for the
scope of this text.
Figure 13 illustrates the use of XPS in the investigation of the anodiza-
tion of GaAs.7 Both the As3d and Ga3d transitions may be observed. By
combining XPS analysis with ion sputtering the composition of the ano-
622 Semiconductor Materials

Table 1: Chemical Shifts in the Cr2p,i2 Transition of Chromium Compounds

Chromium, Cr 2% 24

COMPOUND 2px BINDING ENERGY, eV

573 578 663

Table 2: XPS Chemical Shifts

Oxidation AE Relative to
Compound State Elemental State

S Se Te
x-2 -2 -1.4 - 0.8 - 0.6

x0 0 0 0 0
x03-2 +4 3.6 3.7 29

x0.4 +6 5.5 4.2 3.6

W. L Swsrtq K. J. Wynna ld D. M. Hmulm, ANAL CHEM, 43 1884 (1971)

dized layer is obtained at various depths. The outer surface appears to be

predominately Ga,O, as determined by the chemical shift in the Ga3d
peak and the absence of As. In the bulk of the oxide, the composition is a
mixtureofAs,O,andGa,O,asdeterminedfromthechemicaIshiftsin both
the As3d and Ga3d transitions. At the oxide-GaAs substrate interface
there is a transition region where both the As3d and Ga3d exhibit two
 Characterization of Semiconductor Materials 623

N(E)/E

40 20 0
BINDING ENERGYWI

Figure 13: XPS spectrum of anodized and annealed GaAs showing the chemi-
cally shifted Ga3d and As3d transitions at various depths in the oxide and at the
GaAs substrate.

peaks, one for the oxide and one for GaAs. The oxidation of many compound
semiconductors has been studied by XPS. The composition of the oxide,
especiallyasafunctionofdepth, hasbeenfoundtobestronglydependent
on the method and conditions of formation.
Investigation of metallization schemes used to contact semiconductor
devices is another key area where XPS has been applied. As an example
Figure 14 shows the Pt4f and Si2p spectra obtained from the silicides
which are formed when Pt is used to contact Si.17 Two different silicides
may be formed depending on the annealing conditions used in the process.
The PT 4f,,, and 4f,,, doublet exhibits a chemical shift of less than 1 eV
between the Pt,Si and PtSi phases which may be formed. This chemical
shift is easily detectable. The corresponding Si2p transitions have essen-
tially the same binding energy. The chemical information obtained from
XPScomplimentsthatobtainedfromavarietyofotherthinfilmandsurface
analysis techniques in the investigation of a variety of contact materials.
Since the photoelectron spectra of many elements exhibit only small
chemical shifts for a series of compounds in which the electronegativity
varies over a wide range, it is frequently necessary to examine the other
features of the spectrum. One of these features which frequently exhibits
useful chemical information even when the photoelectron spectra do not,
624 Semiconductor Materials

PI 4fdoublet

00 78 76 74 72 i

BINDING ENERGY,eV

Figure 14: XPS spectrum of the Pt4f,/, and Pt4fS/2 doublet and Si2p transition
of the two silicide phases, PtzSi and PtSi, of platinum.

is the corresponding Auger transitions. Since Auger emission is a multi-

step process in which two electrons are emitted, the Auger and photo-
electron, the electron shells surrounding the atom have more time to
undergo relaxation. This almost always results in larger chemical shifts for
the Auger transitions.
Table 3 compares the binding energies of photoelectron and Auger
transitions for a series of metals and their oxides.15 In all cases, the Auger
transition exhibits a factor of two larger chemical shift over that of the
photoelectron transition. However, it is important to remember that the
Auger spectra are more complex and exhibit broader line widths. In
addition, Auger transitions are not always available due to the limited
energy range of excitation of the x-ray source.
The detection limit for XPS is approximately 0.5% atomic or 5 X 1018
atoms/cm3 in Si with a sensitivity variation of 1 02. Data sets ar.e available
which provide relative sensitivity factors based on peak area.18 The sensi-
tivity factors are specific to the instrument design, yet, once established
the results are more easily quantified than AES data.
The x-rays used for excitation do less damage to the surface than
charged particle excitation sources. There is evidence for x-ray induced
desorption even though only to a minor extent. Sample charging is minor
since only the secondary electron and sample return currents must be
balanced.
XPS has traditionally been more of a research tool in the semiconductor
industry but is becoming more of a routine analytical technique as more
people realize the extensive chemical information that may be obtained
from the spectra.

Secondary Ion Mass Spectroscopy

Secondary Ion Mass Spectroscopy (SIMS) is the mass analysis of
secondary ions generated by ion sputtering. As illustrated in Figure 15,
 Characterization of Semiconductor Materials 625

Table 3: Chemical Shifts in X-Ray Excited Auger Spectra

Binding Energy, eV (Al Radiation)

Compound 3d KLL LMM MNN
--2P ---
Mg 49.8 300.8

MgO 51.2 307.2

Al 72.8 93.5

A1203 75.4 100.2

Zn 9.9 494.0
10.7 498.8
Ge 29.4 341.5
33.2 349.3

Ag 374.0 1128.2
Ag,SO, 374.2 1132.2
Sn 492.9 1048.3
Sn02 494.8 1053.4

lncldent Ion beam

Figure 15: Schematic diagram of secondary particles and radiation generated by

an incident ion beam.
626 Semiconductor Materials

bombarding the surface of a solid with an energetic ion beam generates a

variety of secondary transitions, including electrons, photons and ions.
Detectionofanyofthesesecondaryeventscouldserveasthebasisforany
analytical probe. However, SIMSequipment isoptimizedforthedetection
of positive and secondary ions.
There are several major design features which must be taken into
consideration in selection and application of SIMS as an analytical tool.
One of these is the use of SIMS as an ion imaging tool, ion microscope, or
as an ion microprobe. The ion microscope utilizes an ion lens to image the
ions removed from an area of the sample surface. It often has many of the
other features of an ion microprobe and, as a result, is positioned at the top
end of the line in performance and price. Figure 16 is a schematic of an ion
microprobewhichcontainstheessentialfeaturesofaSIMSsystem.These
include the ion source and secondary ion mass analyzer. The ion source
shown here is a duoplasmatron source which has the capability of gener-
ating ion beams from a gas source of l-2 micrometers spot size at up to 20
KV potential. Other ion sources include the hot filament activated gas
sources which achieve 100 micrometerspot sizesat potentials of typically
5 KV maximum and liquid metal ion sources which achieve spot sizes of
2000A using field emission of low melting point metals.
More expensive instrument designs have a primary ion mass analyzer
to separate the positive and negative ions and the neutrals which are
produced in the source. Since the ions are charged a condenser lens may
be used to focus the ions while charged deflection plates are used to
position the beam or raster it over the sample surface.

Primary
Ion Mass

Condenser Lens

Sample

Figure 16: Schematic diagram of a secondary ion probe mass spectrometer.

 Characterization of Semiconductor Materials 627

Applying a potential to the sample increases the secondary ion collec-

tion efficiency due to their radial distribution. Simple electrostaticanalysis
is often used prior to the mass analyzer in order to select a narrow energy
distribution of the secondary ions. This allows improved performance of
the mass spectrometer. The mass spectrometer can be a quadruple
analyzer for low to intermediate charge to mass ratio resolution or a
magnetic sector for high resolution.
Since SIMS is basically a depth profiling technique in that generation
of secondary ions requires removal of material, it is necessary to generate
the ions from a uniform depth. Since ion beams have Gaussian shapes, it is
necessary to raster the beam over an area slightly larger than the area of
analysisinordertomaintainaflatsamplingarea.1gOtherwise,ionscoming
from the sidewalls of the crater would result in a signal coming from a
region of shallow depth, often referred to as the memory effect. This is
avoided by gating the detection system such that the signal is only
accepted when the primary ion beam is away from the crater wall.
The key design consideration for SIMS instrumentation istheefficient
generation of secondary ions. One aspect of this is the selection of the
primary beam energy. As can be seen in Figure 17, the sputtering yield,
atoms removed per incident ion, is dependent on the incident ion energy.
SIMS ion sourcesare usually designed to operate in the5 to20 KVenergy
region. There is no benefit in going to higher accelerating voltages since
the sputtering yield is flat or decreases above 20 KV.
Only a few per cent of the atoms removed by sputtering are ionized.
The remaindercomeoff as neutral atomsoratom clusters. Properselection of
the primary ion can enhance the ion yield. Electropositive primary ions
enhance the yield of negative secondary ions while electronegative pri-
mary ions enhance the yield of positive secondary ions. On this basis, the
favored primary ions are O- and Cs+, although there are other factors
which may dictate the use of other primary ions.
The secondary ion yield is a function of the electronegativity of the
elements. When a negative primary ion beam is utilized the relative
positive ion yield will be greatest for those elements with the lowest

SRJJ-TERING WELOS _
(atoms/ion) FOR ARGON -

loo Energy (keV)

Figure 17: Plot of the sputtering yield versus ion energy for argon on copper.
628 Semiconductor Materials

electronegativity. Figure 18 illustrates the variation in secondary ion

intensity as a function of atomic number, which correlates with electronega-
tivity.*O Conversely, when a positive primary ion beam is utilized the
relative negative ion yield will be greatest for those elements with the
highest electronegativity.
The SIMS spectrum is a plot of the secondary ion intensity versus the
mass to charge ratio. As can be seen from Figure 19, the spectrum from
even high purity elements like Si can be very complex. The spectrum
consists of ionized atoms and isotopes, ionic complexes, and multiply
ionized species. The ion intensity is usually plotted on a log scale due to the
dynamic range, 1 06, of the data.
Figure 20 illustrates the range of sensitivities*’ available for P im-
planted in Si, from 1 017 to 1 O*l atoms per cm3. This is a factor of 1O-l 00
moresensitivethan AESorXPS. However,SlMSdataisdifficulttoquantify
because the ion yield is matrix dependent. As a result, other techniques
such as neutron activation analysis are used to normalize the SIMS data.
The depth resolution of SIMS is approximately 20A, the depth from which
secondary ions are generated. As illustrated here the surface sensitivity in
combination with the inherent sputtering can be utilized to generate in-
depth profiles of 0.5 micrometers or more with high sensitivity. The depth
scale, however, is not known accurately since the sputter rate depends on
a wide range of variables. The sputter depth is frequently determined
through the use of mechanical stylus techniques, ellipsometry or inter-
ferometric techniques.

Re

10’ 5

Relative i -Th

iFnsity 10’ z
*
A&

@e I ’
Cd
Sb

ITI

I I I I I Auk I I I
30 40 so 60 70 80 90 100

Atomic Number (Z)

Figure 18: Plot of the relative positive secondary ion yield versus atomic num-
ber for 13.5 keV oxygen ions.
 Characterization of Semiconductor Materials 629

1
100, . . . . . . . . . . , ,
High Purlly Silicon
Oxy5rn Bombardment
IO

,, I
t

5
s 0.1

.
.?
;; 0.01
z
cc

0.001

0.0001

0 IO 20 30 40 so 60 TO eo 90 100 II0 120 130 no I50

YOSS/ChlIVJl

Figure 19: Plot of the relative secondary ion intensity versus the mass-to-charge
ratio resulting from oxygen bombardment of high purity silicon.

6OkeV “P Implants
,..‘,‘.,,,,,,,
Normalized lo Doses Determined
By Neutron Acllvalion

Dose - I 09 x I O”at/cm
1’ 13x 10’sat/cm2
1'fOx10"at/cm7
: 5: 90~10'~at/crn~

0.1 0.2 0.3 0.4 0.6 0.6 0.7

Depth (micrometers)

Figure 20: Depth profiles of phosphorus implanted into silicon at 80 keV show-
ing the concentration versus depth.
 630 Semiconductor Materials

Even with these limitations SIMS is a powerful tool for the analysis of
dopants in semiconductor materials. Figure 21 illustrates an example
where SIMS has been used successfully. Boron profiles in Si are shown
before and after laserannealing. 22Thedopantisredistributedasaresultof
laser annealing. The maximum B concentration decreases while the tail of
the profile diffuses to a greater depth. It is interesting to note that the
redistribution of B is concentration dependent. The tail of the implant
profile is redistributed to a much greater depth after laser annealing forthe
high dose implant than the low dose implant.
SIMS is one of a few analytical tools capable of distinguishing isotopes.
This has resulted in some well designed experiments that take advantage
of this feature. For example, Coleman et al. 23 utilized SIMS to investigate

0 0.1 0.2 0.3 0.4 0.5

Depth (micrometers)
Figure 21: Depth profiles of boron implanted into silicon at different doses
showing the concentration versus depth before and after laser annealing.
 Characterization of Semiconductor Materials 631

the anodic oxidation of GaAs. By using isotopically labeled H,O, theywere

able to distinguish the mechanism by which anodic oxidation proceeds.
Figure 22 illustrates the depth profiles that were obtained from a GaAs
(001) waferanodized in H,018 then H,016andanothersampleanodizedin
theoppositesequence.Fromthisstudytheauthorswereabletoshowthat
oxygen is incorporated into the growing oxide at the oxide-electrolyte
interfaceasopposed to theoxide-semiconductorinterface. Mass tansport
occurs through the interstices of the growing oxide.
The most frequent application of SIMS in the semiconductor industry
is in the analysis of dopants in single crystalline substrates. However,
SIMS is widely used in the analysis of a broad range of materials but with
some limitations. Easily ionized elements such as Na, Li or Cl may migrate
during ion bombardment. The charge that builds up on insulators during
ion bombardment may reach sufficient field strength to cause charge
induced ion migration. This effect may be minimized by lowering the
sample temperature of by neutralizing the surface charge. This may be
accomplished by a number of techniques including positioning a hot fila-
ment in proximity to the sample or exposing the surface with a scanning
electron beam. The degree of success in neutralizing the surface charge,
however, greatly influences the secondary yield. The ratio of neutral
species versus secondary ions increases as a result of ion neutralization
during sputtering.
The many factors that influence ion yield make quantification of the
datadifficultandlimittherangeofapplicationsofthetechnique.Byadding

“FYS
SECOND

RELATIVE
DEPTH
Figure 22: Depth profile of the isotopic distribution of oxygen in an anodic
oxide’grown on GaAs(001): curve (A) is for GaAs(001) anodized in HzO” then
Hz016 while curve (B) is for anodization first in Hz016 then Hz018.
632 Semiconductor Materials

a photon source with sufficient energy to ionize the material removed in

the sputtering process to the SIMS system, the ion yield can be increased
to approximately 100%. Through the use of the additional photon source,
the matrix dependence of the ion yield can be minimized. The data
obtained in this manner is much easier to quantify. There is the added
benefit of improved sensitivity since only ions are detected.
An example of this approach, which is frequently referred to as Sputter
Assisted Laserlonization(SALI) isshown inFigure23.Curve(a)showsthe
SIMSspectrumofaGaAswaferusingstaticAr+ bombardment,whilecurve
(b) shows a comparable SALI spectrum with the introduction of a 248 nm
laseraz4 The SIMS spectrum exhibits a significant difference in the Ga+ and
A&intensity. Withtheadditionoftheionizing laser,theionyieldsofGaand
As are more nearly equal and the ion yields of trace elements in the GaAs
are enhanced.

Resonance Ionization Spectroscopy

Resonance Ionization Spectroscopy (RIS) is a technique which is
similar to SALI. The material to be analyzed is removed from the surface of

75&t -_
‘;i
.E 181Tat+
II
= 6000 x25
(b) SALI
_t r- I I 1

“so0 820 1140 1460 1780 2100

CHANNEL (20 NS/CH)

Figure 23: The positive secondary ion SIMS spectrum in trace (a) is from a
GaAs wafer under static Ar+ bombardment. A SALI spectrum is shown in trace
(b) for the same surface under static Ar+ bombardment, plus an accompanying
248 nm laser for ionization.
 Characterization of Semiconductor Materials 633

the sample by ion sputtering. A laser beam is positioned above the sample
so that it intersects with the vapor cloud of atoms as shown in Figure 24.
Thelaseristunedtothefrequencynecessarytoionizetheatomofinterest.
The ions are extracted from the sample region, then energy analyzed
before passing into a mass spectrometer. The spectrum like SIMS is a plot
of the intensity versus the mass-to-charge ratio.25
RIS reportedly is capable of achieving sensitivities reaching 1 part in
10’2 and aselectivity that eliminates ambiguity in the interpretation of the
results.26 Several factors contribute to the enhanced sensitivity of RIS
over similar techniques like SIMS. RIS has a lower background. The ions
that are generated during the sputtering process are extracted before the
laser pulse ionizes the remaining neutral species. As a result, only ions
generatedinthelaserpulsepassintothemassspectrometer.Additionally,
only selected ions are generated in the laser pulse. Figure 25 shows the
five basicschemes used in theresonance ionization process?‘j Typically, a
tunable dye laser is adjusted so that it emits precisely the correct wave-
length to excite an electron in an atom from its original state to a higher
state. Occasionally, a second photon from a second laser is used to excite
the atom further to an even higher state. After excitation, a second or third
photon is used to interact with the excited atom, causing the electron to be
released from the atom. Thereby, producing a positive ion and a free
electron. The key to RIS is choosing resonately excited states that can be
easily excited and that have large photoionization cross-sections, so that
they can be ionized with high efficiency. It is possible to saturate all of
these processes with commercially available lasers, so that an atom in the
initial state will be excited through the resonant intermediate states and
into the ionization continuum with unit probability during a single laser
pulse.
RIS is extremely selective, in that, only atoms of a given element are
ionized. The intermediate excited states through which the ionization
proceeds may be chosen such that they are uniquely characteristic of that

DEFLECTION

DOUBLE-FOCUSING
MASS SPECTROMETER

ENERGY MASS
ION SOURCE

TUNABLE DYE LASER

Figure 24: Schematic diagram of sputter initiated resonance ionization spec-

trometer.
634 Semiconductor Materials

1 2 3 4 5

Figure 25: Schematic diagram of the five basic schemes for RIS.

element. As a result, RIS provides sensitive analysis of solid samplesforall

the elements except He and Ne. Sensitivities of down to 1Ol” atoms/cm3
have been reported for Na in Si.27
Figure 26 shows a plot of the concentration of B in Si as measured by
RIS versus the B concentration determined by electrical resistivity.25
There is generally good agreement between the values down to the part-
per-billion level. The RIS values for the samples lowest in B lie above the
least squares line fitting the values for the samples with the higher B
concentration. This is attributed tocontamination resulting from sputtering of
the stainless steel slits, a common problem for RIS in the detection of
extremely low concentration levels.
Several approaches have been taken to remove material from the
sample surface to be introduced into the laser beam where resonance
ionization occurs. When an ion beam is utilized, many of the analytical
capabilities are similarto SIMS. The sampling depth of approximately20A
is determined by the sputtering process. The depth that is probed depends
on how long one wants to continue the analysis. Due to the generation of a
crater during the sputtering process, the ion beam must be rastered and
the signal gated such that only material from the flat portion of the crater,
uniform depth, is analyzed.
SinceRISisthenewestofthesurfaceanalysistechniques,thereisyet
much to be learned about its sensitivity and sensitivity variation. It shows
 Characterization of Semiconductor Materials 635

102-7 l BORON in SILICON

10-3 10-2 10-l 100 10' 102 1 3

TEKTRONIX VALUES (PPM)

Figure 26: Correlation plot showing the boron concentration in silicon measured
by RIS versus the value determined by electrical measurements.

promise of being one of the most sensitive analytical techniques available

for solids analysis. Commercially produced instruments are now available
which should accelerate the learning process.

Rutherford Backscattering Spectroscopy

Rutherford Backscattering Spectroscopy( RBS) is the energy analysis
of ions that are backscattered from a surface. Typically ions with low mass,
such as H+ or He+, are accelerated toward a target at a potential of 0.5 - 2.0
MeV.Asshown inFigure27,thetarget,M,,recoilswhiletheprimaryion,M,,
scatters at an energy E, at an angle 8. The scattering energy, E,, is easily
calculated from the relationship,

2
E, = W,, M,, @E,

1
where
M, cos0 + dMp2 - M,2sin2r3
K= (3)
MI + M2

The scattering cross-section is a smoothly varying function of the

targetatomicmassasshown in Figure28. From thiscurveit isobviousthat
the scattering efficiency is very low for those elements with low atomic
mass. In addition, it is difficult to distinguish elements which have similar
masses when the elements have high atomic masses.28
Figure 29 shows the equipment necessary to perform RBS. The
accelerator must be capable of generating MeV ions from the light elements.
 636 Semiconductor Materials

Modern instruments make use of compact tandetron accelerators which

allow the construction of RBS systems which are not significantly larger
than other surface analysis equipment. The analysis of the backscattered
ionsmaybeachievedthroughtheuseofanelectrostaticanalyzerorasolid
state detector. The solid state detector, the preferred detection system, is
positioned in front of the target at an angle of approximately 30” from the

Al REST
EO

AntR COLLISION

M2’“1

Figure 27: Schematic diagram illustrating a Rutherford backscattering collision.

k=
I
M,cosl3 + ~4~4;-
4 + Mz
’
M:sin*O
I

TARGET ATOM MASS IAMU)

Figure 28: Plot of the Rutherford backscattering cross-section versus target

atomic mass.
 Characterization of Semiconductor Materials 637

From Acceleralor

u u Beam

Moving Delector Holder

v
CUWeill
lnlegralor
Multi Channel
Analyzer

Figure 29: Schematic diagram of a Rutherford backscattering spectrometer.

incoming primary beam. A thin mylarsheet is placed in front of the detector

to attentuate low energy secondary ions and secondary electrons.
The spectra are plots of scattered ion intensity versus energy. An RBS
spectrum is the sum of a family of curves from each atomic mass in the
target. As shown in Figure 30, KE, represents inelastic scattering from the
front surface of the target.28 At a depth X, the primary ion loses additional
energy through electron scattering both going intoand escaping from the
solid. Since Rutherford scattering occurs at all depths, a curve is generated
which is the sum of all these events. Each atomic mass in the target
generates a separate curve based on its scattering cross-section.2g
Figure 31 illustrates the application of RBS in the analysis of the
silicides formed during the interaction of Ni and Si.30 The dashed line
represents the as-deposited Ni on Si case, where the Ni and Si exhibit
distinct scattering energies. Upon heating at 300°C for 90 minutes, Ni,Si
forms which is represented by the open circles. The curve for Ni has
decreased in intensity and broadened while the silicide portion of the Si
curve has moved toward the Ni. Additional heating results in a further
decrease in intensity and broadening of the Ni curve and an increase in the
Si curve for the silicide. Since the scattering cross-sections for Si and Ni
are known, the stoichiometry for the different phases of silicide can be
calculatedwithouttheuseofstandards.Therearemanyexampleslikethis
in the literature where a heavy metal in a matrix of a low atomic mass
element lends itself to RBS analysis.
Since RBS is essentially a non-destructive quantitative analysis tech-
nique, it is frequently used to calibrate other surface analysis techniques.
It, however, has a limited range of sensitivity of about 1018 atoms/cm3 in a
Si matrix.31 This sensitivity is adequate for calibrating XPS and Auger
samples but not for many SIMS samples.
638 Semiconductor Materials

SCATTERING -TTHlN FILM-

YIELD

REAR SURFACE FRONT SURFACE

L L
E, Et kE,
ENERGY OF BACKSCATTERED ION

Figure 30: A plot of the Rutherford backscattering yield versus the energy of
the backscattered ion with an accompanying illustration showing the scattering
location in the sampled depth.

As Deposlted I
I%, - NI
I -8
6- I
3OO’C’1 90’ Annealing i I
- N12SI
300 lC 90 mln

4- 300’ C 90 mln - NISI _

351’ C 30 mln
:, i
Addillonal ! d
Sequenlial go I I
Annealing lo I

2 10 r ]
.O :
.O ;
-0 1
:o : i
t l * I

0 L-J
0.6 1.0 1.4 1.6

ENERGY (MeV)

Figure 31: RBS spectra of the phases of nickel silicide formed following the
deposition and annealing of nickel on silicon.
 Next Page

Characterization of Semiconductor Materials 639

Of the surface analysis techniques, FIBS is unique in its ability to

distinguishwhetheradopantoccupiesasubstitutionalorinterstitialsitein
a crystalline lattice. When the primary ion beam is oriented along the
crystalline planes, the ions penetrate long distances into the crystal along
the open channels. Scattering occurs at crystal imperfectionsand intersti-
tial impurity sites. Figure 32 compares the FIBS spectra from Si implanted
Si (100) samples which are positioned such that random scattering and
channeling occur.32 The virgin sample exhibits minimal scattering except
in the random orientation, indicating the quality of the crystal. After implanta-
tion, the crystal has undergone extensive damage which is evident in the
increased scattering along thechanneling direction. Subsequent heating
at 550°C and 850°C anneals out much of the damage, however, the crystal
quality of the virgin sample is not recovered.
The same equipment used to do FIBS can be used for nuclear reaction
analysis (NRA).28 Instead of Rutherford scattering the primary ion must
penetrate the nucleus of the target atom and induce a nuclear reaction as
depicted in Figure 33. The nuclear reaction cross-section as a function of
incident ion energy must be known in order to select an energy which will
result in adequate yield. The energies required for NRA are frequently
higher than thuse used for RBS.
Table4 listssome useful nuclear reactions. NRAcompliments RBS in
that, many of the useful nuclear reactions are for low atomic number
elements for which RBS has low sensitivity. Since the nuclear reaction

1500 - 1
I I I I I I

RANDOM
I * n
<HO> ALIGNED:
VIRGIN
AS IMPLANTED a”,: MO
ANNEALED AT 550 ‘C FOR 50 min
iz ANNEALED AT 550 ‘C FOR 50 min, 850 ‘C FOR 10 min 3
F
600

0
0.4 8 0.40 0.32 0.24 0.16 0.06 0 0.08
DEPTH (prnl
Figure 32: FIBS spectra for Si(100) in the random and <I IO> aligned directions
before and after 80 keV 3oSi+ implant and subsequent anneal at 550” and 850°C.
INDEX

Index Terms Links

Acceptors 27
Adsorption
adatom 412 421
binding energy 411
Amphoteric 362
Atomic mobility 96 102
Auger electron spectroscopy (AES) 6 611
analysis 67 70 178 294
chemical shift 614
cylindrical mirror analyzer 613
detection limit 616
energy level diagram 611
profiling 66 614

Bipolar devices 65 87 576 581 587

590 603 605
Boltzmann constant 464

Capacitance, parasitic 106 149 592

Capacitance-voltage technique 59 71

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Index Terms Links

Carrier
concentration 27
velocity 27
Channel 1 4
current 4
Charge 58 59
fixed oxide 58
mobile ionic 58
oxide trapped 59
Chemical vapor deposition (CVD) 6 80
boron nitride 115 122
polycrystalline silicon 106
Si 82 94
Silicon carbide 106 115 122
SiO2 75 106 115
Si3N4 75 105 106 115
Chemisorption 333 421
Child-Langmuir Law 209 397
CMOS 89
Collector 111
Condensation 410
Conductivity 308
Crucible 12 19 20
Crystal Growth
Czochralski 9
float-zone 9 20 475
seed crystal 12 82
Crystallographic orientation 84 133
Crystal puller 11

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Index Terms Links

Deep level transient spectros-

copy (DLTS) 7 71 659
Defect 6 94
density 55 67 86 172
monovacancy 473
point 421 455 470 472 490
498 500
saucer pits 33
Denuded zone 42 91 92 173
Deposition
orientation dependent 149 172
Desorption
association reaction 421
ion-induced 367
mean residence time 411
Diamond lattice 26
Die 22
Dielectric
breakdown 67
constant 4 60
films 47 48 58
interlevel 440 592
isolation 106 109 112 136 155
Diffusion 6 455 595
activation energy 464 469 486 488 491
Arrhenius expression 469 616
barrier 55 439 602 606
bulk 415 616
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Index Terms Links

Diffusion (Cont.)
coefficient 69 463 495
continuum theory 456
diffusivity 469 476 482 487 495
501 596
dopant 67 69
Fick’s Laws 456 495
flux 466
grain boundary 596 606 616
Henry’s Law 460
interstitialcy 466 476 500
oxidation enhanced 70 479
oxygen 40 50 67 74
predeposition 459
surface 415
vacancy 465 491 496 501
Diode 96
Dislocation 6 13 23 24 32
475
misfit 94 178
Donor 27
oxygen 40
Dopant 15 18 19 20 21
63
MBE films 361
N-type 15 22 61
P-type 15 22 61
segregation 61
substitutional 477 488
Drain current 4
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Index Terms Links

Dynamic random access memory

(DRAM) 4

Eddy current sensor 22

Effusion cell 426
Electric field 73
Electromigration 6 604
Electronic printer printhead 112 114
Electron paramagnetic resonance (EPR) 473
Electron spin resonance 70
Ellipsometry 55 70
Enthalpy 468 488
Entropy 468
Epitaxial
homoepitaxy 84
heteroepitaxy 84
silicon 22 82 84 85 86
89 90 91 178 183
Etching 126
anisotropic 6 109 112 126 136
138 145 149 157 158
162 172
chemical 23 24 64
choline 187 189
cleanup 186 187
concentration dependent 127
Dash 173

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Index Terms Links

Etching (Cont.)
defect etch 91 92 128 172
planar 126
RCA clean 187
reactive ion 6
Schimmel 173
Secco 172 173
Sirtl 172 173
vapor 86 89 90 91
Wright-Jenkins 173 178
Yang 173
Evaporation 329 336
flash evaporation 348
hot-wall evaporation 349
rate 337
rate monitors 354
reactive evaporation 352
sources 340
sublimation 350
three-temperature 419
uniformity 345
of alloys 347
of compounds 347

Fermi level 471

Field effect transistor (FET) 587
Flatband voltage 60

G
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Index Terms Links

Gate
delay 1
insulator 4
length 1
oxide 1 60 592
voltage 4
Gettering 34 41
backside 91 94 173
oxygen precipitates 173
vacuum 335
Gibbs free energy 468
Grain boundary, polycrystalline
silicon 73 91

Hall mobility 424

High electron mobility transistor
(HEMT) 363
Hydrophilic 25
Hydrophobic 25

Implantation 6
Impurity 6 15 18 43 90
gettering 65
N-type 84
P-type 84
substitutional 477
Inelastic mean free path 613
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Index Terms Links

Infrared 36 38 654
epitaxial layer thickness measurement 658
Fourier transform (FTIR) 7
sensitivity 657
Ingot 11 12 15 18 20
22
Integrated circuits 9
Interface
SiOs/Si 58 59 61 62 65
66 67 68 70 71
traps 59
Interferometry 249
Interstitial 20
oxygen 37 38 41
self 455 472 499
silicon 69 70
Ion bombardment
cleaning 422
influence on microstructure 425
influence on stress 430
ion beam mixing 428
Ion implantation 512
critical energy 520
electronic stopping 519
implantation masking 522
ion channeling 527
Lindhard, Scharff & Schiott
(LSS) range theory 528
nuclear stopping 519

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Index Terms Links

Ion implantation (Cont.)

projected range 521
range theory 515
Ion plating 424

Junction 82
breakdown voltage 61
depth 1 67 506

Knock-on sputtering 367

Knudsen cell 343
effusion cell 343 351

Lifetime, minority-carrier 34
Lithography 541
Abbe principle 557
contact printing 551
electron beam lithography 6 543 570
ion beam 6
numerical aperture 555 558
optical 6 559
projection printing 555
wafer stepper 556
x-ray 6 571

M
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Index Terms Links

Melting point 82
Metailization 575
multilevel 440
ohmic contact 438 598
polysilicon 592
Rent’s rule 581
silicides 439 601
step coverage 440
wiring structure 581
Microstructure 6 415
Mobility 27
atomic 90
Molecular beam epitaxy 330 355
apparatus 356
application 362
epitaxy growth 360
three-temperature evaporation 420
MOS device 58 65 73 87 89
91 109 133
gate 601 603
Multiquantum well laser (MQW) 363

Neutron activation analysis (NAA) 7 664

charged particle activation 666
sensitivity 665
Nitridation plasma 67
polycrystalline silicon 73
thermal 66

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Index Terms Links

Nuclear reaction analysis (NRA) 639 666

hydrogen 295 300
Nucleation 41 96 102 412
preferential 416
sites 94 415 424

Ohmic contacts 438

Optical emission 249
Outgassing rate 333
Oxidation
ambient 48 65 67 68
Anodization 46 73 75
dopant concentration dependence 63 478
mechanism 68 70
orientation dependence 49 62
plasma assisted 72
reaction kinetics 47 50 51 52 53
54 67
silicides 73
surface preparation dependence 64
temperature 49 52
thermal 46 48 50 51 52
54 55 59 70 75
Oxide 70
capacitance 60
charge 62 65 69 71
interlevel insulation 592

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Index Terms Links

Oxygen 15 19 20 31 32
35 37 91
diffusion 39 40
dissolved 9 38

Packaging, thermal conduction

module 584
Packing density 109
Pascal 330
Periodic table 9
Group III 15 27
Group V 27
GroupVI 15
Phase transitions 6
Phosphorus 15 18 27 33
Photoluminescence (PL) 7 660
bound-exciton 661
detection limit 661
free exciton 661
Photomask 541 551
alignment 22
Photoresist, multiple level resist 568
negative 542 560
photoactive compound 560
positive 542 560
sensitivity 549
Physisorption 332

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Index Terms Links

Plasma 191
anisotropy 191 193 227 252
chemical effects 213
DC plasma 193 195 196
feedstock composition 210
fundamental aspects 192
mechanism 230
modeling 241
non-equilibrium 191
plasma body 193
plasma sheath 193 195 208 209 393
395
reactor loading 223
RF plasma 193 194 195 196 394
surface chemistry 217
Plasma etching 242
Al 263
compound semiconductors 264
defects 257
endpoint detection 249
equipment 244
oxide 260
patterning 242
radiation damage 257
selectivity 254
Si 259
silicides 259
silicon nitride 264
throughput 256
uniformity 253
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Index Terms Links

Plasma enhanced chemical vapor

deposition 265
compound semiconductors 310
film properties 284
Ge 310
interface properties 315
metals 311
reactors 268
silicides 312
silicon 305
silicon dioxide 301
silicon nitride 289
source gases 280
uniformity 281
Polishing 25
Polycrystalline 9 11
Polycrystalline silicon 6 24 74 96 104
109 112 308
gettering 91
interconnect 439
oxidation 73
polysilicon charge 11 21 82
Positron annihilation 474
Precipitates 6 42
carbon 34
oxygen 20 32 35 40 41
43 91 173
Preferential deposition, epitaxial
Si 96

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Index Terms Links

Q
Quartz crucible 9 11 12 48
reactor 82

Radiation damage 443

Radiation hardened 106 109 129 136
Radio frequency (RF), induction coil 9
Refractive index 285 292 294 302
Resistivity 15 20 25 31
Resonance ionization spectroscopy (RIS) 7 633
detection limits 633
resonance ionization schemes 633
Rutherford backscattering
spectro scopy (RBS) 6 70 294 316 635
energy analyzer 636
scattering cross-section 635

S
Scanning electron microscopy 96 158 162 640
backscattered electrons 641
energy dispersive x-ray spectrometer 642
secondary electrons 641
wavelength dispersive analyzer 645
Scanning transmission electron
microscopy (STEM) 7 475 646
bright field image 647
darkfield image 647
electron diffraction 648
electron energy loss spectroscopy 649
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Index Terms Links

Schottky barrier 362 598 601

Secondary ion mass spectroscopy
(SIMS) 6 70 624
detection limit 628
mass analyzer 628
secondary ion yield 627
Segregation 63
coefficient 15 18 20 21 31
34 35 38
surface 362
Sheet resistance 509 514
Silicide 6 73
molybdenum 439
paladium 439
platinum 439
tantalum 74
titanium 439
tungsten 439
Silicon carbide 34 111 122
Silicon dioxide 4 12 48 50 54
74 105 109 122
monoxide 25
silica 25
Silicon halide SiBr4 85
SiCl4 82 85 90 102 122
SiHCl3 82 95 90 102
SiH2Cl2 85 90 102
SiH4 85 90
SiHBR 85
Sil4 85
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Index Terms Links

Silicon monoxide 12 19
Silicon nitride 55 105 111 122
Solubility, oxygen 39
Spreading resistance 18
Sputter assisted laser ionization
(SALI) 632
Sputtering 329 364
alloys 376
bias 424 442
cleaning 422
compounds 376
glow discharge 378
ion beam 392
magnetron 382
mechanisms 365
planar diodes 378
reactive 400
RF sputtering 394
sputtered species 369
triode 381
yield 371
Stacking faults 6 32 33 69 70
91 104 155 157 173
178 183 500 647
oxidation-induced 499
Stereographic projection 133
Sticking coefficient 421

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Index Terms Links

Stress, compressive 430

deposited films 429
intrinsic 429
oxide 69 303
SINx films 295
tensile 430
thermal 429
Structure zone model 415 426
Movchan and Demchishin 416
Sublimation 343 350
Substrate 13
p+ 89
Substitutional 34 37 38 41
Susceptor 11

Target poisoning
reactive sputtering 402
Thermal decomposition 86
Threshold voltage 4 61
Torr 330
Transistor 82
Trap, defect 91

Ultra large scale integration (ULSI) 1 5 6 7 91

183

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Index Terms Links

Vacancy, diffusivity 487

silicon 70 455 472
Very large scale integration (VLSI) 1 5 6 7 70
73 91 181

Wafer 22 23 25 34
flatness 25
Work damage 22 23
Work function 60

X-ray diffraction 70
X-ray lithography 115
X-ray photoelectron spectroscopy (XPS) 6 70 303 618
Auger transition 624
chemical shift 621
detection limit 624
energy analyzers 618
monochrometer 618
profiling 620
X-ray orientation 22
X-ray topography (XRT) 7 653

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