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AM26C32
SLLS104L – DECEMBER 1990 – REVISED OCTOBER 2018

AM26C32 Quadruple Differential Line Receiver

1 Features 3 Description
1• Meets or Exceeds the Requirements of ANSI The AM26C32 device is a quadruple differential
TIA/EIA-422-B, TIA/EIA-423-B, and ITU line receiver for balanced or unbalanced digital
Recommendation V.10 and V.11 data transmission. The enable function is
common to all four receivers and offers a choice
• Low Power, ICC = 10 mA Typical of active-high or active-low input. The 3-state
• ±7-V Common-Mode Range With ±200-mV outputs permit connection directly to a bus-
Sensitivity organized system. Fail-safe design specifies that
• Input Hysteresis: 60 mV Typical if the inputs are open, the outputs always are
high. The AM26C32 devices are manufactured
• tpd = 17 ns Typical using a BiCMOS process, which is a combination
• Operates From a Single 5-V Supply of bipolar and CMOS transistors. This process
• 3-State Outputs provides the high voltage and current of bipolar
with the low power of CMOS to reduce the power
• Input Fail-Safe Circuitry consumption to about one-fifth that of the
• Improved Replacements for AM26LS32 Device standard AM26LS32, while maintaining AC and
• Available in Q-Temp Automotive DC performance.

2 Applications Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
• High-Reliability Automotive Applications
AM26C32N PDIP (16) 19.30 mm × 6.35 mm
• Factory Automation
AM26C32NS SO (16) 10.20 mm × 5.30 mm
• ATM and Cash Counters AM26C32D SOIC (16) 9.90 mm × 3.90 mm
• Smart Grid AM26C32PW TSSOP (16) 5.00 mm × 4.40 mm
• AC and Servo Motor Drives AM26C32J CDIP (16) 21.34 mm × 6.92 mm
AM26C32W CFP (16) 10.16 mm × 6.73 mm
AM26C32FK LCCC (20) 8.90 mm × 8.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic
4
G
12
G

2
1A 3
1 1Y
1B

6
2A 5
7 2Y
2B

10
3A 11
9 3Y
3B

14
4A 13
15 4Y
4B

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26C32
SLLS104L – DECEMBER 1990 – REVISED OCTOBER 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 8
2 Applications ........................................................... 1 8.4 Device Functional Modes.......................................... 9
3 Description ............................................................. 1 9 Application and Implementation ........................ 10
4 Revision History..................................................... 2 9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 12
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 12
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 12
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 12
6.4 Thermal Information ................................................. 4 12 Device and Documentation Support ................. 13
6.5 Electrical Characteristics........................................... 5 12.1 Receiving Notification of Documentation Updates 13
6.6 Switching Characteristics .......................................... 5 12.2 Community Resources.......................................... 13
6.7 Typical Characteristics .............................................. 6 12.3 Trademarks ........................................................... 13
7 Parameter Measurement Information .................. 7 12.4 Electrostatic Discharge Caution ............................ 13
12.5 Glossary ................................................................ 13
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ......................................... 8
Information ........................................................... 13

4 Revision History
Changes from Revision K (June 2015) to Revision L Page

• Changed II unit value From: µA To: mA in the Electrical Characteristics table...................................................................... 5

Changes from Revision J (February 2014) to Revision K Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1

Changes from Revision I (September 2004) to Revision J Page

• Updated document to new TI data sheet format - no specification changes ......................................................................... 1

• Deleted Ordering Information table. ....................................................................................................................................... 1
• Updated Features ................................................................................................................................................................... 1
• Added ESD Warning .............................................................................................................................................................. 3

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5 Pin Configuration and Functions

D, N, NS, PW, J or W Package

16-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP FK Package
Top View 20-Pin LCCC
Top View

VCC
NC
1B 1 16 VCC

1A
1B

4B
1A 2 15 4B
1Y 3 14 4A 3 2 1 20 19
1Y 4 18 4A
G 4 13 4Y
G 5 17 4Y
2Y 5 12 G
6 11
NC 6 16 NC
2A 3Y
7 10 2Y 7 15 G
2B 3A
8 9 2A 8 14 3Y
GND 3B 9 10 11 12 13

2B

3B
3A
GND
NC
Pin Functions
PIN
SOIC, PDIP, SO, I/O DESCRIPTION
NAME LCCC
TSSOP, CFP, or CDIP
1A 3 2 I RS422/RS485 differential input (noninverting)
1B 2 1 I RS422/RS485 differential input (inverting)
1Y 4 3 O Logic level output
2A 8 6 I RS422/RS485 differential input (noninverting)
2B 9 7 I RS422/RS485 differential input (inverting)
2Y 7 5 O Logic level output
3A 13 10 I RS422/RS485 differential input (noninverting)
3B 12 9 I RS422/RS485 differential input (inverting)
3Y 14 11 O Logic level output
4A 18 14 I RS422/RS485 differential input (noninverting)
4B 19 15 I RS422/RS485 differential input (inverting)
4Y 17 13 O Logic level output
G 5 4 I Active-high select
G 15 12 I Active-low select
GND 10 8 — Ground
1
6
NC (1) — — Do not connect
11
16
VCC 20 16 — Power Supply

(1) NC – no internal connection.

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage (2) 7 V
A or B inputs –11 14
VI Input voltage V
G or G inputs –0.5 VCC + 0.5
VID Differential input voltage –14 14 V
VO Output voltage –0.5 VCC + 0.5 V
IO Output current ±25 mA
Tstg Storage temperature -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±2000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 Vcc V
VIL Low-level input voltage 0 0.8 V
VIC Common-mode input voltage -7 +7 V
IOH High-level output current –6 mA
IOL Low-level output current 6 mA
AM26C32C 0 70
AM26C32I –40 85
TA Operating free-air temperature °C
AM26C32Q –40 125
AM26C32M –55 125

6.4 Thermal Information

AM26C32
THERMAL METRIC (1) D (SOIC) N (PDIP) NS (SO) PW (TSSOP) UNIT
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 73 67 64 108 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Differential input high-threshold VO = VOH(min), IOH = –440 VIC = –7 V to 7 V 0.2
VIT+ V
voltage µA VIC = 0 V to 5.5 V 0.1
Differential input low-threshold VIC = –7 V to 7 V –0.2 (2)
VIT– VO = 0.45 V, IOL = 8 mA V
voltage VIC = 0 V to 5.5 V –0.1 (2)
Vhys Hysteresis voltage (VIT+ – VIT−) 60 mV
VIK Enable input clamp voltage VCC = 4.5 V, II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –6 mA 3.8 V
VOL Low-level output voltage VID = –200 mV, IOL = 6 mA 0.2 0.3 V
OFF-state (high-impedance state)
IOZ VO = VCC or GND ±0.5 ±5 µA
output current
VI = 10 V, Other input at 0 V 1.5 mA
II Line input current
VI = –10 V, Other input at 0 V –2.5 mA
IIH High-level enable current VI = 2.7 V 20 μA
IIL Low-level enable current VI = 0.4 V –100 μA
ri Input resistance One input to ground 12 17 kΩ
ICC Quiescent supply current VCC = 5.5 V 10 15 mA

(1) All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.

(2) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-
mode input voltage.

6.6 Switching Characteristics

over operating free-air temperature range, CL = 50 pF (unless otherwise noted)
AM26C32C AM26C32Q
PARAMETER TEST CONDITIONS AM26C32I AM26C32M UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
tPLH Propagation delay time, 9 17 27 9 17 27 ns
low- to high-level
output
See Figure 2
tPHL Propagation delay time, 9 17 27 9 17 27 ns
high- to low-level
output
tTLH Output transition time, 4 9 4 10 ns
low- to high-level
output
See Figure 2
tTHL Output transition time, 4 9 4 9 ns
high- to low-level
output
tPZH Output enable time to 13 22 13 22 ns
high-level
See Figure 3
tPZL Output enable time to 13 22 13 22 ns
low-level
tPHZ Output disable time 13 22 13 26 ns
from high-level
See Figure 3
tPLZ Output disable time 13 22 13 25 ns
from low-level

(1) All typical values are at VCC = 5 V, TA = 25°C.

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6.7 Typical Characteristics

6

Output Voltage - V
3

0
HIGH
LOW
±1
0 10 20 30 40 50
Logic Input Current - mA C001

Figure 1. Output Voltage vs Input Current

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7 Parameter Measurement Information

VCC tTLH tTHL
VOH
Output 90% 90%
50%
A 10% 10% VOL
Device
Under tPLH tPHL
B Test CL = 50 pF
Input 2.5 V
(see Note A)
Input 0V
−2.5 V

TEST CIRCUIT VOLTAGE WAVEFORMS

A. CL includes probe and jig capacitance.

Figure 2. Switching Test Circuit and Voltage Waveforms

VCC
S1

G Input RL = 1 kΩ
G Input Device tPZL, tPLZ Measurement: S1 to VCC
VID = ±2.5 V A Input Under tPZH, tPHZ Measurement: S1 to GND
Test
B Input CL = 50 pF
(see Note A)

TEST CIRCUIT

3V
G 1.3 V
0V

3V
G 1.3 V
(see Note B)
0V

tPZH tPHZ tPZH tPHZ

VOH
Output VOH −0.5 V VOH −0.5 V
(with VID = 2.5 V) 50%
VOL
tPZL tPLZ tPZL tPLZ

VOH
Output
(with VID = −2.5 V) 50% VOL + 0.5 V
VOL + 0.5 V VOL

VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf
= 6 ns.

Figure 3. Enable/Disable Time Test Circuit and Output Voltage Waveforms

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8 Detailed Description

8.1 Overview
The AM26C32 is a quadruple differential line receiver that meets the necessary requirements for NSI TIA/EIA-
422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or low voltage
MCU to interface with heavy machinery, subsystems and other devices through long wires of up to 1000m, giving
any design a reliable and easy to use connection. As any RS422 interface, the AM26C32 works in a differential
voltage range, which enables very good signal integrity.

8.2 Functional Block Diagram

EQUIVALENT OF A OR B INPUT EQUIVALENT OF G OR G INPUT TYPICAL OF ALL OUTPUTS

VCC VCC VCC

17 kΩ 1.7 kΩ
NOM NOM
Input
288 kΩ Input Output
NOM 1.7 kΩ
NOM
VCC (A inputs)
or
GND (B inputs)

GND GND GND

8.3 Feature Description

8.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity
For a common-mode voltage varying from -7V to 7V, the input voltage is acceptable in low ranges greater than
200 mV as a standard.

8.3.2 Input Fail-Safe Circuitry

RS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200
mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is not
defined and can randomly assume high or low. Removing the uncertainty of random output states, modern
transceiver designs include internal biasing circuits that put the receiver output into a defined state (typically high)
in the absence of a valid input signal.
A loss of input signal can be caused by an pen circuit caused by a wire break or the unintentional disconnection
of a transceiver from the bus. The AM26C32 has an internal circuit that ensures functionality during an idle bus.

8.3.3 Active-High and Active-Low

The device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1
on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enables
active low operation. These are simply a way to configure the logic to match that of the receiving or transmitting
controller or microprocessor.

8.3.4 Operates from a Single 5-V Supply

Both the logic and receivers operate from a single 5-V rail, making designs much more simple. The line drivers
and receivers can operate off the same rail as the host controller or a similar low voltage supply, thus simplifying
power structure.
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8.4 Device Functional Modes

8.4.1 Enable and Disable
The receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled or
disabled. This allows users to ignore or filter out transmissions as desired.

Table 1. Function Table (Each Receiver)

DIFFERENTIA
ENABLES OUTPUT
L INPUT
A/B G G Y
H X H
VID ≥ VIT+
X L H
VIT < VID < H X ?
VIT+ X L ?
H X L
VID ≤ VIT-
X L L
X L H Z

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of the
cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors to
consider when determining the type of termination usually are performance requirements of the application and
the ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,
parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly, RS-
485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26C31C and AM26C32C, respectively, were tested at room temperature with a 5-V supply
voltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and the
bottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections, the
first plot shows output waveforms from the driver at the start of the cable; the second plot shows input waveforms
to the receiver at the far end of the cable.

9.2 Typical Application

AM26C31 AM26C32
(One Driver) (One Receiver)
RT
DIN ROUT
D D

Figure 4. Differential Terminated Configuration

9.2.1 Design Requirements

Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary from
system to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance,
Zo , of the cable and can vary from about 80 Ω to 120 Ω.

9.2.2 Detailed Design Procedure

Figure 4 shows a configuration with no termination. Although reflections are present at the receiver inputs at a
data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input
differential voltage and produces a clean signal at the output.

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Typical Application (continued)

9.2.3 Application Curve

Voltage (V)
1

±1

±2
Y A/B
±3
0 0.1 0.2 0.3 0.4 0.5
Time ( s) C001

Figure 5. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)

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10 Power Supply Recommendations

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

VDD

VCC
1B 1 16

1A 2 15 4B 0.1µF

Termination Resistor 1Y 3 14 4A

Reduce logic signal trace G 4 13 4Y

when possible
AM26C32
2Y 5 12 G

2A 6 11 3Y

2B 7 10 3A
GND
8 9 3B

Figure 6. Trace Layout on PCB and Recommendations

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-9164001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9164001Q2A
AM26C32
MFKB
5962-9164001QEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9164001QE
A
AM26C32MJB
5962-9164001QFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9164001QF
A
AM26C32MWB
AM26C32CD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C
& no Sb/Br)
AM26C32CDBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 26C32
& no Sb/Br)
AM26C32CDE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C
& no Sb/Br)
AM26C32CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C
& no Sb/Br)
AM26C32CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C
& no Sb/Br)
AM26C32CN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN
& no Sb/Br)
AM26C32CNE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN
& no Sb/Br)
AM26C32CNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 26C32
& no Sb/Br)
AM26C32CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 26C32
& no Sb/Br)
AM26C32ID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)
AM26C32IDE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)
AM26C32IDG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)

Addendum-Page 1
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

AM26C32IDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)
AM26C32IDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)
AM26C32IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I
& no Sb/Br)
AM26C32IN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 AM26C32IN
& no Sb/Br)
AM26C32INSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I
& no Sb/Br)
AM26C32IPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I
& no Sb/Br)
AM26C32IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I
& no Sb/Br)
AM26C32IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I
& no Sb/Br)
AM26C32IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I
& no Sb/Br)
AM26C32MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9164001Q2A
AM26C32
MFKB
AM26C32MJB ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9164001QE
A
AM26C32MJB
AM26C32MWB ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9164001QF
A
AM26C32MWB
AM26C32QD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q
& no Sb/Br)
AM26C32QDG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 26C32Q
& no Sb/Br)
AM26C32QDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AM26C32, AM26C32M :

• Catalog: AM26C32
• Enhanced Product: AM26C32-EP, AM26C32-EP
• Military: AM26C32M

NOTE: Qualified Version Definitions:

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM26C32CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C32IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C32IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26C32QDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26C32CDR SOIC D 16 2500 333.2 345.9 28.6
AM26C32IDR SOIC D 16 2500 333.2 345.9 28.6
AM26C32IPWR TSSOP PW 16 2000 367.0 367.0 35.0
AM26C32QDR SOIC D 16 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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