2022 3rd International Conference for Emerging Technology (INCET)

Belgaum, India. May 27-29, 2022

Hardware Posit Numeration System primarily based

on Arithmetic Operations
Alapati Madhu sravya N. Swetha Asisa Kumar Panigrahy
Dept. of ECE Dept. of ECE Dept.of ECE
2022 3rd International Conference for Emerging Technology (INCET) | 978-1-6654-9499-1/22/$31.00 ©2022 IEEE | DOI: 10.1109/INCET54531.2022.9825011

Gokaraju Rangaraju Institute of Gokaraju Rangaraju Institute of Gokaraju Rangaraju Institute of

Engineering and Technology. Engineering and Technology Engineering and Technology.
Hyderabad,India Hyderabad,India Hyderabad,India
[email protected] [email protected] [email protected]

Abstract— In this paper we discuss about the newly developed all ‫݉ݑ݊ݑ‬s Type III ‫ ݉ݑ݊ݑ‬called as posit, format system has
universal number system called posit number system which is similar representation with FP systems than Type I and Type II
also called as type-3 unum system. To overcome the ‫ݏ݉ݑ݊ݑ‬. Another way for representation of standard IEEE FP
disadvantages of floating point number system posits has been numbers and real numbers in computer system can be done by
proposed, they increase overall dynamic range and accuracy in using new format called Posit numbers. Thus they provide
comparison with the floats. This posit system format consists of many advantages over floating point systems. The main plus
sign bit, regime bit, exponent bit and mantissa bit. Its point of posit numbers is, they have an ability to be more
mathematical notation consists of a run-time variable exponent
precise, has higher dynamic range for any bit numbers having
part. This work implements the open source hardware Posit
numeration system primarily based on Arithmetic Operations on
same bit length, they are very accurate and can do arithmetic
Xilinx ISE tool. This system being at the starting stage has very calculations exactly. This posit number systems has many
restricted hardware solutions for its arithmetic architectures. applications, especially while performing applications having
The proposed work concentrates on the algorithmic development very large data content. For example, if we can convert a 64 bit
and generic HDL generators for basic posit arithmetic, that IEEE float’s into a 32 bit posit’s then we can induce twice as
includes the adder, multiplier, and division arithmetic for the much as numbers into the memory unit in one time. Thus these
given posit word length (N) of 32-bit with exponent size (ES) of posit numbers had gained interest in many developer’s, which
6-bit and its comparison with various bit lengths. resulted in developing various software tools for ‫݉ݑ݊ݑ‬s by
using C++,C, juila etc.
Keywords: posit number system, universal number system,
adder, division, multiplier. A. Universal number system (unum)
The concept of ‫ ݉ݑ݊ݑ‬was proposed by John L. Gustafson
I. INTRODUCTION in [8] as an alternative to the IEEE Standard for Floating-Point
We live in a world where the trade-off between cost, Arithmetic that has been the standard for decades ሺ‫ܧܧܧܫ‬͹ͷͶሻ.
performance and energy consumption is crucial in the area of The ‫ ݉ݑ݊ݑ‬system format can be used to express the real
VLSI field in electronics. The current demand of analyzing numbers and its range. These arithmetic format being evolved
large amounts of data, the high-performance computing (HPC), before last few years, has divided the ‫݉ݑ݊ݑ‬s into 3 different
or the limited computing resources available on the more number format types,
frequent embedded systems are developing new computer
The first ‫’݉ݑ݊ݑ‬s were the float’s and integer formats.
program solutions. For any information transfer
They can be represented either as an intact float’s or as open
communication pays a very important role whether it is in
interval in between two corresponding float’s, when
between human beings or any devices. In electronic word
computation has not provided accurate numeric answers then
communication between devices can be done through signals,
in standalized FP arithmetic and rounding will be executed. To
i.e., signals contain information that needs to be transmitted
execute these, ‫’݉ݑ݊ݑ‬s comprehend a “‫( ݐܾ݅ݑ‬uncertainty bit)”
from any transmitter to the receiver. These signals can be
at the end of all the fractional bit part to show with respect to
analog or digital. In digital signal processing(DSP), the signal
transformation is done digitally in binary format by using the accurate value or the interval, incase ‫ ݐܾ݅ݑ‬is either Ͳ‫ͳݎ݋‬Ǥ
various number system methods. These number systems The Type-1 ‫ ݉ݑ݊ݑ‬format is first introduced in year 2015,
mainly classified into following formats they are fixed point and is similar to ‫ܧܧܧܫ‬͹ͷͶ݂݈‫ ݃݊݅ݐܽ݋‬െ ‫ ݐ݊݅݋݌‬model which
number system, floating point(FP) number system and consists of the sign, exponent and fraction(or mantissa) bit
universal number system (UNUM). fields. Here from single bit to max length, the exponent and
The ܷ݊݅‫ݎܾ݁݉ݑ݈݊ܽݏݎ݁ݒ‬ሺ‫݉ݑ݊ݑ‬ሻ system concept was first mantissa bit field lengths are variable. Thus, exponent and
introduced in 2015 by John L. Gustafson , since then this fraction size field’s are included to ‫ ݉ݑ݊ݑ‬format. This format
number system has undergone many transformations as Type I, representation has been shown in Figure 1. Type-1 ‫݉ݑ݊ݑ‬s are
Type II, and Type III. Posit is the latest version of the Type III used to expand float’s to interval arithmetic, but has hardware
‫ ݉ݑ݊ݑ‬introduced in 2017. The word POSIT stands for Pose execution limitations due to their variable lengths. Information
from Orthography and Scaling with Iterations. Now, Floating about this format can be seen in [8].
point (FP) number system can be replaced with Unum. Among

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 B. Necessity for posits
At present all the real valued computations are being done
using IEEE 754 floating point format. Even though it had
achieved success it also has certain weaknesses. To overcome
Fig. 1. Type-1 ‫ ݉ݑ݊ݑ‬bits format [12] these weaknesses we moved to posit system. when compared
to IEEE 754 posits have higher precision, larger dynamic
The Type-2 ‫ ݉ݑ݊ݑ‬was first introduced in year 2016. It is range and are more accurate. Some of the disadvantages of
proposed to resolve some shortcomings of Type I, that is to IEEE 754 are listed below
reduce the complexity of the hardware design executions and
1) Small numbers having large size: IEEE 754 uses
different ways to present certain values. This format is not
compatible with ‫ݏݐܽ݋݈݂ܧܧܧܫ‬. Further, they show a clear, precision values of single and double format to
mathematical architecture based on mapping of values onto represent 32 and 64 bits. So the numerous
computations have values that are efficient and also
real projective line, which is the set represented asܴ ̂ ൌ
ܴ‫ڂ‬ሼ∞ሽ , its main idea is signed numbers that can change from have very limited range.
+ve to -ve, and the same points illustrate the values of േ∞. 2) Limited range for precision: IEEE 754 leave several
The format for Type-2 ‫ ݉ݑ݊ݑ‬is shown in figure 2 The above bits to represent positive/negative 0 and ∞, Not-a-
right part of the circle represents the set of real numbers ‫ݔ‬௜ and number, denormals. By taking all the above
have mirror values on vertical axis. The below half of the circle conditions complexity of the processor has been
has the reciprocal numbers of the top half, and has mirror increased.
values on horizontal axis. In this manner we can place opposite 3) Not following algebraic conditions: IEEE 754
and reciprocal values on horizontal and vertical mirrors sometimes does not follow algebraic conditions at the
respectively. Although Type-2 ‫’݉ݑ݊ݑ‬s has many time of computation. For example, floating point
mathematical properties for real numbers, but in practical they addition cannot always be associative.
have very limited scalability of about 20 bits or less [4, 9]. In 4) Displaying results that are inconsistent: This error
addition, ݂‫ ݏ݊݋݅ݐܽݎ݁݌݋݀݁ݏݑ‬which has dot product are quiet can be seen during dot product of two vectors.
costlier. These drawbacks resulted in development of posit 5) Having complicated designs for verification: To
format that can keep both Type II ‫ ݉ݑ݊ݑ‬properties, and also design an efficient floating point unit is very time
“hardware-friendly” taking process and it should handle all the
exceptional case errors and verifying them is a
complex task
To overcome these weaknesses we went for posits. When
compared to IEEE 754 floats, posits have some advantages
which are listed below.
1) Unique value representation: In IEEE 754 there are
two separate representations for +∞ and -∞ bits and
both are not equal, but in posits +∞ and -∞ are
represented with same bits.
2) No underflow bits: If the output of any operation is
not zero but it is smaller than any normalized number
underflow occurs, which is one of the issue in IEEE
754. This problem can be solved in posits by using
tapered precision.
3) Follow Algebraic conditions for any formats: posits
follow algebraic conditions for any different formats
Fig. 2. Figure shows real number line representation of Type-2 ‫݉ݑ݊ݑ‬s.
and holds associative condition in addition operation.
Type-3 ‫ ݉ݑ݊ݑ‬representation is called as ‫ݐ݅ݏ݋݌‬, was first 4) Handling Exceptional Bits: There are no NaN’s n
introduced in 2017. Here author described it as “designed as a posits and has single 0 and ∞ bit representation.
direct drop-in replacement for IEEE 754 standard for floating- 5) Disadvantages of posit numbers: One advantage of
point numbers” [4]. Their functionality is similar to that of floats over posits is having fixed bit representation
Type-2, on bases of the projective line. Hardware development for exponent and mantissa parts, so parallel decoding
is same to that of the can be done easily. Due to variable length of
‫ܧܧܧܫ‬͹ͷͶ݂݈‫ ݃݊݅ݐܽ݋‬െ ‫[ ܿ݅ݐ݄݁݉ݐ݅ݎܽݐ݊݅݋݌‬10] logic. This exponent and mantissa parts in posits, decoding is
format is followed for Ͳǡ േ∞ܽ݊݀݅݊‫ʹݎ݁ݓ݋݌ݎ݁݃݁ݐ‬. done in serial manner.[22]
The Valid is an arithmetic interval type of the posit system. II. POSIT BACK GROUND
It has equal size posit pairs, where every bit ends with the ubit
which indicate the bounds. However, information about valids In comparison to type-1 and type-2 ‫݉ݑ݊ݑ‬s, this posit
is not yet introduced by Gustafson. system format is a new data type format

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 Sign bit, Regime bits, Exponent bits and Mantissa bits. This
Posit number system being in starting stage has very finite
design solutions for arithmetic architectures. Here the author
designed arithmetic operations such as add, mult and div for 8
bit number format and also implemented pipelined architecture
Fig. 3. shows the format of an N-bit posit with ES exponent bits.[1] for above arithmetic operations for 32 bit word size and 6 bit
exponent size(ES) of posit number system format using verilog
The posit format composes of the sign bit, regime bits, HDL coding technique.
exponent bits and mantissa bit fields.
Manishkumar jaiswal, Hayden.h.so [2] In this paper the
x Sign Bit: author proposed an Hardware design which generate
– The 0 represents the +ve posit number. adder/subtractor for Type3 Unum posit. His main target is to
– The 1 represents the -ve posit number. Also for implement hardware architecture for newly developed posit
negative numbers, first we should take 2’s system under Type III ‫݉ݑ݊ݑ‬. Here algorithm flow for
compliment of left over bits before decoding regime, arithmetic operations such as posit add/sub are been introduced
exponent and mantissa bits. and its hardware architecture is designed. The main target of
– The posit exponent value can be termed as the this paper is to construct open-source parameterized verilog
HDL generator for above posit arithmetic.
combination of regime and exponent bits
x Regime Bits: Manishkumar jaiswal [3] It is the continuation of the above
– Regime bits were the sequence of eitherͲ‫ͳݎ݋‬, paper, here the author proposed a Universal number posit
terminated by its inverse bit, Its run-length gives Arithmetic generator on FPGA. Being a recently developed
value for regime bit. Posit lacks adequate hardware arithmetic architectures that
include run time variation in exponent and mantissa bits, Thus,
– A sequence of z-bit 0 ended with (z+1)th bit as 1
this paper is focused towards the posit arithmetic algorithmic
gives the value of -z (001՜ െʹሻ, (00001՜-4).
development and their generic hardware generator. It is
– A sequence of z-bit 1 ended with (z+1)th bit as 0 targeted on constructing basic posit arithmetic’s such as floats
gives the value of z-1 (110՜ 1), (11110՜3). to posit number conversion, posit to floating number
– Having regime bit value of ߢ, its participation in total conversion, add/sub and mult and are executed on a FPGA
ಶೄሻೖ platform.
exponent value is ʹሺଶ
ಶೄ
– Where ʹଶ can be denoted as ‫݀݁݁ݏݑ‬. Therefore J. L. Gustafson and I. Yonemoto [4] A posit is a new data
regime value can be given as ‫ ݀݁݁ݏݑ‬௞ type which is a straight replacement for
x Exponent Bits: ‫݀ݎܽ݀݊ܽݐݏܧܧܧܫ‬͹ͷͶ݂݈‫ݏݎܾ݁݉ݑ݊ݐ݊݅݋݌݃݊݅ݐܽ݋‬ሺ݂݈‫ݏݐܽ݋‬ሻ,
they don’t need interval arithmetic or variable size operand but
– Exponent Bits are unsigned bit integers which has
they have high accuracy, large dynamic range, having good
max of ES bit length. Its value defines the posit closure, has bitwise identical output for any system, have
number format simpler hardware and good at exception handing. Posit’s
– The value of total exponent is given as ʹ௘ . doesn’t underflow to 0 or overflow to λ. In short, in this paper
x Mantissa Bits: the author compared about floating point number system and
– These bits functions similar to that of the normalized posits number system and highlighted the advantages for
floating point standard. It represents the leftover bits opting posits.
after regime and exponent bits are filled. Yohann Uguen, Luc Forget and Florent de Dinechin. [5] In
– For any ES value, max mantissa length is given by this paper the author proposed about posit numbers and how it
N-ES-3. provides more precision for numbers around 1. Posit system
that shows performance and resources consumption and make
Here regime value is represented as݇, exponent value as ݁ practical level of evaluation, this is considered to be main
and mantissa value as ݂( including the hidden bit 1), thus objective of this paper. It also shows implementation of open
decimal value representation of posit is given by source hardware for posit system it include C++ library which
ಶೄሻೖ
is compatible with Vivado HLS tool. This C++ library right
‫  כ ݏ‬ሺʹሺଶ ሻ ‫ʹ כ‬௘ ‫݂ כ‬ now implements add, sub and mult operations for custom-size
Posit format is determined by the total bit length ሺ݊ሻ and posits.
maximum of exponent bits (ES). Therefore the common R. Chaurasiya, J. Gustafson, R. Shrestha, J. Neudorfer, S.
notation of posit is represented as ൏ ݊ǡ ‫ ܵܧ‬൐ with n-bit posit Nambiar, K. Niyogi, and R. Leupers [6] In this paper, the
and ES exponent bits[1]. author presented the design model of a parameterized
PAU(Posit Arithmetic Unit) generator which can produce PAU
III. LITERATURE SURVEY adders and PAU multipliers of variable bit-length pre-
Manishkumar jaiswal, Hayden.h.so [1] In this paper the synthesis. This synthesizes produce arithmetic operations such
author proposed an open source hardware Posit Arithmetic as adder’s and multiplier’s of any parameterized PAU bit
Code Generator using newly introduced UNUM system called length i.e., ͺ െ ܾ݅‫ݐ‬ǡ ͳ͸ െ ܾ݅‫ݐ‬ǡ ܽ݊݀͵ʹ െ ܾ݅‫ ݏݐ‬and compares
posit system. This posit number system format composes of them with ‫ܧܧܧܫ‬͹ͷͶ െ ʹͲͲͺ adder’s and multiplier’s. Both,

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synthesis are implemented in Application Specific Integrated TABLE I. COMPARISONS OF LITERATURE SURVEY
Circuit (ASIC) and Field Programmable Gate Array (FPGA). Authors Objective Implementation
Manishkumar jaiswal, To perform Arithmetic It is done by using
Junjie Hou1,Yongxin Zhu, Sen Du1, Shijin Song [18] Hayden.h.so operations for Posit coding techniques on
Accuracy and dynamic range plays a major role in data number system format verilog HDL on
representation. Till now, floating point format called IEEE 754 using Verilog HDL XILINX ISE tool and
has been used for data representation. Recently posits are used coding technique. Further implemented in
to replace floats. In this paper the author made comparison FPGA and ASIC tool
kits.
between IEEE 754 system and posit number systems by
Manishkumar jaiswal, To perform Adder and It is done by using
implementing arithmetic operations on hardware tool kit of Hayden.h.so subtraction operations coding techniques on
FPGA and also made comparison for precision, dynamic range for posit number verilog HDL on
and their performances, thus concluding posit achieve better system format using XILINX ISE tool.
performance regarding precision and dynamic range. Verilog HDL coding
technique
Feibao Xiao, Feng Liang, Bin Wu 1, Junzhe Liang, Shuting Manishkumar jaiswal To perform basic Implementation can be
Cheng and Guohe Zhang [19] In this paper the author arithmetic of FP to done in C,C++ and
proposed hardware implementation of posit adder/sub, mult, posit converter, posit to Julia languages.
FP converter, addition/
div in addition with square root operation. The main target of subtraction and
this paper is to develop an arbitrary posit format which multiplier arithmetic
occupies minimum area of circuits used in embedded using software tools
applications. To achieve this, author used alternative add and like C,C++ and Julia.
sub method for divide and square root operations instead of J. L. Gustafson and I. It mainly draw It is a theory paper
Newton Raphson method, and all of these operation are further Yonemoto comparison between which compares about
the Standard IEEE 754 IEEE 754 floats and
implemented on FPGA tool kit. floating point number posits
Stuart F. Oberman. [20] In this paper author used AMD-k7 system and Posit
number system.
processor to implement floating point IEEE 754 division and Yohann Uguen, Luc To perform hardware Implementation is done
square root algorithms using iterative method. It provided Forget and Florent de architecture for posit by using C++ language
accurate approximations and good latency performance at high Dinechin.[ encoder, decoder, PIF using Vivado HLS tool.
frequencies. It also verifies rounding and target precisions. adder and multiplier
using C++ templatized
Peter Malik. [21] In this paper the author implemented library compatible with
divider and multiplicative inverse operations for floating point Vivado HLS.
number system in FPGA. He implemented using 32 bit floats R. Chaurasiya, J. Hardware Hardware Architecture
Gustafson, R. Shrestha, implementation of Implementation is done
singe precision. Main target of this paper is to achieve high J. Neudorfer, S. posit arithmetic using by using cadence tools.
throughput. Nambiar, K. Niyogi, FPGA based scientific
and R. Leupers data analytics and
Sarada musala, Aruna kumari neelam, Bharath compare with IEEE
sreenivasulu.V, Viaya vardhan [23] In this paper the author 754
implemented concurrent error detectable and self-repairable Junjie Hou1,Yongxin In this paper author Here logic is written
carry select adder using NCLaunch tool. Zhu, Sen Du1, Shijin made comparison of using verilog HDL and
Song arithmetic operations, hardware
The author proposed present paper [1] based on all above precision and dynamic implementation is done
previous references, at first he have taken references from ranges between posits on XILINX VIVADO
paper [4] and paper [6]. Paper [4] author made comparison of and IEEE 754 floats. tool and further
floating point and posit number system and paper [6] author dumped on FPGA tool
it
made hardware implementation for arithmetic operations. Feibao Xiao, Feng In this paper hardware Hardware
Paper [5] author executed these operations in C language. Liang, Bin Wu 1, implementation of implementation of the
Paper [18] explains about dynamic range and precision of the Junzhe Liang, Shuting adder/subtractor, specified operations are
posits. Paper [19] also executes arithmetic operations similar to Cheng and Guohe multiplier, square root done on XILINX
paper [1] using different algorithm method. Paper [20 and 21] Zhang and division operations FPGA tool kit
of posits which can
describes about floating point division and square root reduce circuit area are
operation implementation in FPGA. From above references [1] dome on FPGA.
author want to implement these operations in open source Stuart F. Oberman Implementation of Division and square
using verilog HDL which can be accessible to future users, for division and square root operations of IEEE
this first he proposed paper [3] then he taken next step by root algorithms of 754 floats are
implementing addition and multiplication algorithms in verilog IEEE 754 floats on implemented on AMD-
AMD- K7 processor to K7 processor.
which is paper [2]. Then he extended this paper by adding achieve low latency at
division operation to complete basic arithmetic operations and high frequencies.
proposed the present paper [1]. Peter Malik By using different Implementation of
computing algorithms division algorithms of
for division operation floating point numbers
of floating point on FPGA
numbers on FPGA to

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 achieve high through Basic architecture of LOZ detector is shown below
put.
Sarada musala, Aruna By using carry select These adders are
kumari neelam, adder(CSA) to obtain implemented using
Bharath concurrent error NCLaunch tool which
sreenivasulu.V, Viaya detectable and self- gives error free output.
vardhan repairable carry select
adder

IV. POSIT ARITHMETIC OPERATIONS

IMPLEMENTATION
Being the newest number system, Posits are having very
limited applications and research has been undergoing to
extend its format. In present work we proposed basic
arithmetic operations like addition, multiplication and division
operations for posit having 32 bit format and 6 bit ES. This
structure is implemented in pipelined format. This is executed
in open-source hardware tool using verilog coding technique.
The hardware tool we used for implementation is XILINX
ISE14.v. The basic architecture for arithmetic operation flow is Fig. 5. shows LOZ[2:1] architecture [1]
shown in figure 4.
Step 2. Core arithmetic processing
The flow starting with posit data extraction followed by
Core arithmetic processing which performs related arithmetic This block of algorithm works similar to that of the floating
operations then continues with Posit construction, Rounding point arithmetic which executes three main operations such as
and post processing. Explanation for every block is listed addition, multiplication and division. Which are discussed
below. below
a) Arithmetic Addition
It works similar to that of floating point arithmetic
adder unit. Two input sign bit computation is done using XOR
operation followed by mantissa bits addition that includes
exponent and regime bits. Bit shifting is done using dynamic
left shifter.
b) Arithmetic Multiplication
It also follows similar pattern to that of addition i.e., sign
bit computation is done by XOR operation followed by
mantissa bit multiplication using integer multiplier which is
checked for over flow then shifting is done for normalization.
c) Arithmetic Division
After posit extraction sign bit is computed using XOR
operation then exponent bit which is the combination of regime
bits perform subtraction of divisor from dividend value. For
mantissa division Newton-Raphson method is used.
Step 3. construction, Rounding and post processing
Fig. 4. Arithmetic flow [1] This block deals with posit data composition, rounding and
final processing. The main aim of this step is to create required
Step 1. Posit data extraction regime sequence. The required data composition of posit is
obtained by dynamic left shifting of regime output sequence,
In this step all the parameters such as posit word length(N) rounding can be performed to round-to-nearest-even output
and exponent size(ES) values need to be parameterized in value using unit at last place addition bit.
verilog HDL language. At first it checks for any 0 or ∞
exceptional case detection, if sign bit is negative then it convert Step 1 and step 3 are common for all the arithmetic
whole word into its 2’s compliment form then it checks for operations
regime termination bit. For this author used two operations one
is leading one detector(LOZ) which observe termination of 1 at V. RESULTS
sequences of 0 (i.e., 00….01) another is leading zero All the results of arithmetic operation outputs with their
detector(LZD) which observe termination of 0 at sequence of RTL schematics which are executed in Xilinx ISE tool are
1(i.e., 11….10) then to shift from one bit to another author displayed below
used dynamic left shifter using barrel shifter operation.

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A. Output result of (N =32 bit and ES=6 bit) Posit adder: B. Output result of (N =32 bit and ES= 6 bit) Posit
Multiplier:

Fig. 6. shows RTL Schematic of posit arithmetic addition having 32 N-Bit Fig. 8. shows RTL Schematic of posit arithmetic multiplier having 32 N-Bit
and 6 bit ES. and 6 bit ES

The above figure represents RTL schematic of 32 N bit and The above figure represents RTL schematic of 32 N bit and
6 ES bit length of posit arithmetic adder. It utilized 264 slice 6 ES bit length of posit arithmetic multiplier. It utilized 189
registers, 1085 slice LUT’s, 225 fully used LUT-FF pairs, 101 slice registers, 819 slice LUT’s, 154 fully used LUT-FF pairs,
bonded IOB’s and 1 BUFG. 101bonded IOB’s, 1 BUFG and 2 DSP48E1.

Fig. 7. represents output waveforms for posit adder

Here inputs of the posit adder are given in the form of IN1
and IN2 , which is of 32 bit word length and 6 bit exponent Fig. 9. represents output waveforms for posit multiplier
length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed above Here inputs of the posit multiplier are given in the form of
IN1 and IN2 , which is of 32 bit word length and 6 bit
exponent length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed above.

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C. Output result of (N =32 bit and ES =6 bit) Posit Division: length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed below

Fig. 12. represents output waveforms for posit adder

E. Output result of (N =16 bit and ES= 4 bit) Posit

Multiplier:
Here inputs of the posit multiplier are given in the form of
IN1 and IN2 , which is of 16 bit word length and 4 bit
exponent length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed below

Fig. 10. shows RTL Schematic of posit arithmetic division having 32 N-Bit
and 6 bit ES.

The above figure represents RTL schematic of 32 N bit and

6 ES bit length of posit arithmetic division. It utilized 490 slice
registers, 1187 slice LUT’s, 410 fully used LUT-FF pairs,
101bonded IOB’s, 1 RAM/FIFO, 1 BUFG and 6 DSP48E.

Fig. 13. represents output waveforms for posit multiplier

F. Output result of (N =16 bit and ES =4 bit) Posit Division :

Here inputs of the posit division are given in the form of
IN1 and IN2 , which is of 32 bit word length and 6 bit
exponent length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed below

Fig. 11. output waveforms of posit division

Here inputs of the posit division are given in the form of

IN1 and IN2 , which is of 32 bit word length and 6 bit
exponent length. We have taken clock input as CLK as 1. Then
corresponding output waveforms are displayed above.
D. Output result of (N =16 bit and ES=4 bit) Posit adder :
Here inputs of the posit adder are given in the form of IN1 Fig. 14. output waveforms of posit division
and IN2 , which is of 16 bit word length and 4 bit exponent

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 TABLE II. COMPARISON OF 16 AND 32 BIT POSIT ARITHMETIC REFERENCES
OPERATIONS
[1] M. K. Jaiswal, Hayden.K.H.SO (2019). PACoGen: Posit Arithmetic
Operation 32-bit 32-bit 32-bit 16-bit 16-bit 16-bit Core Generator.
add mult div add mult div [2] M. K. Jaiswal and H. K.-H. So, ‘‘Architecture generator for type-3
Clk 6.252 6.286 6.023 5.119 5.230 - unum posit adder/subtractor,’’ in Proc. IEEE Int. Symp. Circuits Syst.
period(ns) (ISCAS), May 2018, pp. 1–5.
[3] Manish Kumar Jaiswal. (2017) Posit Adder HDL Arithmetic. [Online].
Delay(ns) 6.252 6.286 6.023 5.119 5.230 -
Available: https://github.com/manish-kj/Posit-HDL-Arithmetic/
Frequency( 159.936 150.09 166.02 195.35 191.19 - tree/master/Posit-Adder.
MHZ) 4 2 5 0 [4] J. L. Gustafson and I. Yonemoto, (2017). Beating Floating Point at its
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No.of 10 10 14 10 10 - 10.14529/jsfi170206. [Online]. Available:
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[5] Yohann Uguen, Luc Forget and Florent de Dinechin, (2019) Evaluating
No.of D- 326 254 1060 186 159 - the hardware cost of the posit number system. doi:
type F/F’s 10.1109/FPL.2019.00026
No.of 2 1 1 2 1 - [6] R. Chaurasiya, J. Gustafson, R. Shrestha, J. Neudorfer, S. Nambiar, K.
Comparato Niyogi, and R. Leupers, ‘‘Parameterized posit arithmetic hardware
rs generator,’’ in Proc. IEEE 36th Int. Conf. Comput. Design (ICCD), Oct.
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No.of 20 10 11 20 10 -
[7] “IEEE Standard for Floating-Point Arithmetic”, IEEE Std 754-2008, pp.
Multiplexe
1–70, 2008. doi: 10.1109/ieeestd.2008.4610935.
rs
[8] J. L. Gustafson, The End of Error: Unum Computing. CRC Press, Feb.
5, 2015, vol. 24, isbn: 9781482239867.
From the above table we can conclude as the bit size [9] L. van Dam, “Enabling High Performance Posit Arithmetic Applications
increases the delay, frequency and memory parameters Using Hardware Acceleration”, Master’s thesis, Delft University of
gradually increased but the increase in these parameters is very Technology, the Netherlands, Sep. 17, 2018, isbn: 9789461869579.
[10] A. A. D. Barrio, N. Bagherzadeh, and R. Hermida, “Ultra-low-power
less. Among all operations 32-bit division operation consumed adder stage design for exascale floating point units”, ACM Trans.
large memory, frequency and has more D flip flops while 32- Embed. Comput. Syst., vol. 13, no. 3s, 150:1–150:24, Mar. 2014. doi:
bit multiplication operation is having highest delay and clock 10.1145/2567932.
period and both 32 and 16-bit addition operation consists of [11] J. L. Gustafson. (Oct. 10, 2017). Posit Arithmetic, [Online]. Available:
maximum multiplexers. https: //posithub.org/docs/Posits4.pdf (visited on Mar. 13, 2019).
[12] Raúl Murillo Montero (2019). “Study of the posit number system: a
VI. CONCLUSION practical approach” [pdf].
[13] D. Goldberg, “What every computer scientist should know about
In this paper we discussed about recently developed type-3 floating-point arithmetic”, ACM Computing Surveys (CSUR), vol. 23,
Unum system called posit number system. Brief introduction of no. 1, pp. 5–48, Mar. 1991. doi: 10.1145/103162.103163.
[14] IEEE Computer Society Standards Committee and American National
this system and how is gained advantage over IEEE 754
Standards Institute, “IEEE Standard for Binary Floating-Point
floating point number system. We also executed 32-bit and 16- Arithmetic”, ANSI/IEEE Std 754-1985, 1985. doi:
bit posit arithmetic operations such as adder, multiplier and 10.1109/ieeestd.1985.82928.
division operations using open source HDL language in Xilinx [15] “IEEE Standard for Floating-Point Arithmetic”, IEEE Std 754-2008, pp.
ISE tool and its parameter comparison is drawn in a tabular 1–70, 2008. doi: 10.1109/ieeestd.2008.4610935.
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everywhere”, in ACM 1998 workshop on Java for High–Performance
In this work, we implemented arithmetic operations such as Network Computing, Stanford University, 1998, pp. 1–81.
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[Online]. Available: https://posithub.org/docs/posit_standard.pdf (visited
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coding techniques and this whole coding process is executed in [18] J. Hou, Y. Zhu, S. Du, and S. Shong, ‘‘Enhancing accuracy and dynamic
XILINX ISE tool, thus outputs of these operations are range of scientific data analytics by implementing posit arithmetic on
observed and comparison table of the 32-bit and 16-bit posit FPGA,’’ J. Signal Process. Syst., pp. 1–12, Nov. 2018. doi:
arithmetic operations has been included. 10.1007/s11265-018-1420-5.
[19] Feibao Xiao, Feng Liang, Bin Wu 1, Junzhe Liang, Shuting Cheng and
Guohe Zhang, “Posit Arithmetic Hardware Implementations with The
VII. FUTURE SCOPE
Minimum Cost Divider and SquareRoot”., oct 2020.
Since posit number system being in its infant stage, till now [20] S. F. Oberman, ‘‘Floating point division and square root algorithms and
very limited applications are being executed. Many researches implementation in the AMD-K7/sup TM/ microprocessor,’’ in Proc.
14th IEEE Symp. Comput. Arithmetic, Apr. 1999, pp. 106–115.
are being undergoing to use this system in many domains [21] P. Malík, ‘‘High throughput floating-point dividers implemented in
including artificial and machine learning applications. We can FPGA,’’ in Proc. IEEE 18th Int. Symp. Design Diagnostics Electron.
extend these arithmetic operations by using encoder and Circuits Syst., Apr. 2015, pp. 291–294.
decoder operations. And further implementation can be done [22] DISADVANTAGES OF THE FLOATING POINT NUMBER
on FPGA tool kits by comparing them with floating point SYSTEM| Available: https://www.sigarch.org/posit-a-potential-
number system operations. replacement-for-ieee-754/
[23] Sarada Musala, Aruna Kumari Neelam, Bharath Sreenivasulu V & K.
Vijaya Vardhan (2021) Concurrent error detectable and self-repairable
carry select adder, International Journal of
Electronics, DOI: 10.1080/00207217.2021.2001862

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