Q - What is VLSI design automation?

Ans - VLSI Physical Design Automation is essentially the research, development and productization of
algorithms and data structures related to the physical design process. The objective is to investigate
optimal arrangements of devices on a plane (or in three dimensions) and efficient interconnection
schemes between these devices to obtain the desired functionality and performance.
VLSI Design Cycle
A briefly outline all the steps of the VLSI design cycle represented by the flow chart shown in
Figure.
System
Logic Design Fabrication
Specification

Architectural Packaging and

Circuit Design
Design Testing

Behavioural
Physical Design
Design

Fig.1: A simple VLSI Design cycle flow chart.

1. System Specification

• The first step of any design process is to lay down the specifications of the system.
• System specification is a high level representation of the system. The factors to be considered
in this process include:
➢ performance,
➢ functionality, and
➢ physical dimensions (size of the die (chip)).

• The fabrication technology and design techniques are also considered. The specification of a
system is a compromise between market requirements, technology and economical viability.
The end results are specifications for the size, speed, power, and functionality of the VLSI
system.
2. Architectural Design

• The basic architecture of the system is designed in this step. This includes, such decisions as RISC
(Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer), number of ALUs,
Floating Point units, number and structure of pipelines, and size of caches among others. The outcome of
architectural design is a Micro-Architectural Specification (MAS). While MAS is a textual (English like)
description, architects can accurately predict the performance, power and die size of the design based on
such a description.

• These early estimates are critical to determine the viability of a product for a market segment. For
example, for mobile computing (such as lap top computer), low power consumption is a critical factor, due
to limited battery life. Early estimates based on architecture can be used to determine if the design is likely
to meet its power spec.
3. Behavioural or Functional Design

• In this step, main functional units of the system are identified. This also identifies the interconnect requirements
between the units. The area, power, and other parameters of each unit are estimated.

• The behavioral aspects of the system are considered without implementation specific information. For example,
it may specify that a multiplication is required, but exactly in which mode such multiplication may be executed
is not specified. We may use a variety of multiplication hardware depending on the speed and word size
requirements.

• The key idea is to specify behavior, in terms of input, output and timing of each unit, without specifying its
internal structure. The outcome of functional design is usually a timing diagram or other relationships between
units.

• Functional or behavioral design provides quick emulation of the system and allows fast debugging of the full
system. Behavioral design is largely a manual step with little or no automation help available.
4. Logic Design

• In this step the control flow, word widths, register allocation, arithmetic operations, and logic operations of the
design that represent the functional design are derived and tested. This description is called Register Transfer
Level (RTL) description.

• RTL is expressed in a Hardware Description Language (HDL), such as VHDL or Verilog. This description can
be used in simulation and verification. This description consists of Boolean expressions and timing
information.

• The Boolean expressions are minimized to achieve the smallest logic design which conforms to the functional
design. This logic design of the system is simulated and tested to verify its correctness.
5. Circuit Design

• The purpose of circuit design is to develop a circuit representation based on the logic design.

• The Boolean expressions are converted into a circuit representation by taking into consideration the
speed and power requirements of the original design.

• Circuit Simulation is used to verify the correctness and timing of each component. The circuit design
is usually expressed in a detailed circuit diagram. This diagram shows the circuit elements (cells,
macros, gates, transistors) and interconnection between these elements. This representation is also
called a netlist.
6. Physical Design

• In this step the circuit representation (or netlist) is converted into a geometric representation. This geometric
representation of a circuit is called a layout. Layout is created by converting each logic component (cells,
macros, gates, transistors) into a geometric representation (specific shapes in multiple layers), which perform the
intended logic function of the corresponding component.

• Connections between different components are also expressed as geometric patterns typically lines in multiple
layers.

• In many cases, physical design can be completely or partially automated and layout can be generated directly
from netlist by Layout Synthesis tools.

• Most of the layout of a high performance design (such as a microprocessor) may be done using manual design,
while many low to medium performance design or designs which need faster time-to-market may be done
automatically.
7. Fabrication

• After layout and verification, the design is ready for fabrication. Since layout data is typically sent to
fabrication on a tape, the event of release of data is called Tape Out.

• Layout data is converted (or fractured) into photo-lithographic masks, one for each layer. Masks identify
spaces on the wafer, where certain materials need to be deposited, diffused or even removed.

• Silicon crystals are grown and sliced to produce wafers. Extremely small dimensions of VLSI devices
require that the wafers be polished to near perfection. The fabrication process consists of several steps
involving deposition, and diffusion of various materials on the wafer. During each step one mask is used.
Several dozen masks may be used to complete the fabrication process.
8. Packaging, Testing and Debugging

• Finally, the wafer is fabricated and diced into individual chips in a fabrication facility. Each chip is
then packaged and tested to ensure that it meets all the design specifications and that it functions
properly.
New Trends in VLSI Design Cycle

New industrial trends, which seek to significantly alter or effect VLSI fabrication process.
The major contributing factors for the new design cycle are :
a) Increasing interconnect delay
b) Increasing interconnect area
c) Increasing number of metal layers
d) Increasing planning requirements
e) Synthesis
Fig.2: New VLSI design cycle.
a. Increasing interconnect delay
➢ As the fabrication process improves, the interconnect is not scaling at the same rate as the devices. Devices are
becoming smaller and faster, and interconnect has not kept up with that pace.
➢ Almost 60% of a path delay may be due to interconnect.
➢ One solution to interconnect delay and signal integrity issue is insertion of repeaters in long wires.

b. Increasing interconnect area

➢ It has been estimated that a microprocessor die has only 60%-70% of its area covered with active devices. The
rest of the area is needed to accommodate the interconnect. This area also leads to performance degradation. As the
number of transistors grew, the interconnect area increased.
➢ With the introduction of a second metal layer, the interconnect area decreased.
➢ While more metal layers help in reducing the die size, it should be noted that more metal layers (after a certain
number of layers) do not necessarily mean less interconnect area. This is due to the space taken up by the vias on
the lower layers.
c. Increasing number of metal layers
➢ The number of metal layers available for interconnect is increasing.
➢ Currently, a three layer process is common to meet the increasing needs of interconnectivity used for most
designs, while four layer and five layer processes are used mainly for microprocessors.

d. Increasing planning requirements

➢ The most important implication of increasing interconnect delay, area of the die dedicated to interconnect, and
a large number of metal layers is that the relative location of devices is very important.
➢ This includes two new key step:
▪ Block planning : Block planning assigns shapes and locations to main functional blocks.
▪ Signal planning: Signal planning refers to assignment of the three dimensional regions through which
major busses and signals will be routed.
e. Synthesis
The time required to design any block can be reduced if layout can be directly generated or synthesized from a
higher level description.

➢ It basically maps the design to the process technology and the logic cells already pre-designed, pre-
characterized, and pre-tested in the cell library. The synthesis process always tries to meet the design constraints
such as area, speed, and power.

➢ The biggest disadvantage is the area used by synthesized blocks. Such blocks take larger areas than hand crafted
blocks. Depending upon the level of design on which synthesis is introduced, we have two types of synthesis.

I. Logic Block
II. High Level Synthesis
I. Logic Block

• This process converts an Hardware Description Language (HDL) description of a block

into schematics (circuit description) and then produces its Layout.
• Logic synthesis is not applicable for large regular blocks, such as RAMs, ROMs, PLAs
and Data paths, and complete microprocessor chips for two reasons; speed and area.
• Logic synthesis tools are too slow and too area inefficient to deal with such blocks.

II. High Level Synthesis

• This process converts a functional or microarchitectural description into a layout or RTL description.
• High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL)
synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes
an abstract behavioral specification or microarchitectural description into a layout or RTL Fig.3: Synthesis
description. Design step.
• In high level synthesis, input is a description which captures only the behavioral aspects of the
system.
Physical Design Cycle

The input to the physical design cycle is a circuit diagram and the output is the layout of the circuit. This is
accomplished in several stages such as:
i. Partitioning
ii. Floorplanning and Placement
iii. Routing
iv. Compaction
v. Extraction and Verification
 Circuit Design

Partitioning

Floorplanning and
Placement

Routing

Compaction

Extraction and
Verification

Fabrication Fig.4: Physical Design Cycle.

 i. Partitioning

• Partitioning is a process by which the entire VLSI circuit is divided into a smaller number of sub-circuits.
• The partitioning is done such that the number of interconnections between the sub-circuits are minimum.
Typically, the entire circuit is partitioned into a number of blocks based on the functionality.
• Due to the limitations of memory space and computation power available it may not be possible to layout
the entire chip in the same step.
• Partitioning process considers many factors such as:
➢ Size of the blocks
➢ Number of blocks
➢ Number of interconnections between the blocks

Fig.5: Partitioning in physical design cycle.

ii. Floorplanning and Placement

• In this step, it is planned to accommodate all the design components and their interconnects within a minimum
area.
• This step sets up a plan for a good layout alternatives for each blocks having different aspect ratio.
• aspect ratio of M is defined as h/w.
Where, h = height of the rectangular shaped module or block.
w = width of the rectangular shaped module.

• It tentatively places the modules (modules can be blocks, functional units, etc.) at an early stage when details
such as shape, area, I/O pin positions of the modules, etc., are not yet fixed.
• Floorplanning are done by the design engineer in order to find minimum area arrangement for the blocks.
Goal of Floorplanning

▪ To arrange the blocks on the chips

▪ To decide the input / output pad locations
▪ To decide the number of power pads and their locations
▪ To decide the power distribution style
▪ To decide the clock distribution and their locations

Fig.6: A typical floor planning design.

Placement
• In this step, the exact placement of the modules (modules can be gates, standard cells) are done. The details of
the module design are known in this phase. The main goal of placement is to minimize the total area, delay,
congestion, interconnect metrics, etc.
The objectives of the placement step are as follows:

▪ Minimize the chip area.

▪ Minimize the delay on critical paths
▪ Ensure that layout is routable
▪ Minimize power dissipation of the design
▪ Minimize the crosstalk between the signals

Goal of placement
▪ Minimize the total estimated wire length of all the nets
▪ Minimize the interconnect congestion Fig.7: Typical placement in integrated circuit.
 iii. Routing
• Routing simply means drawing paths from the source to the destination in a layout or acts as interconnections
among modules.
• In this step, the interconnection lines are drawn for the signal, power, ground, and clock nets.
• Factors such as critical path, clock skew, crosstalk, congestion, repeater placement, wire spacing, etc., are
considered during the routing.
Goal
The main goal of routing is to complete the interconnections among the blocks according to the specified netlist.

The objectives of routing are to:

▪ Achieve 100% routing

▪ Minimize total wire length in the chip
▪ Minimize area of the chip
▪ Minimize layer changes for interconnection
▪ Minimize net delay on critical paths
• The routing problem is divided into two problems,
I. Global Routing
II. Detailed Routing

I. Global Routing: Global routing is the step where the actual

routing is not done, rather, the routing is planned. It is done at Fig. 8: Horizontal and vertical interconnecting
metal layers.
the top level where routing regions are defined, the nets are
assigned to routing regions, and all channel terminals are
determined.

II. Detailed Routing: The actual interconnections are made.

Detailed routing is classified into two types:
▪ Area routing Fig. 9: Routing of integrated circuit.
▪ Channel routing
Area routing, the routing is carried out with obstacles. It is also Channel routing, dedicated space called
called maze routing. This routing problem is to find a shortest routing channels are provided for routing.
path between two terminals on a grid with obstacles.
iv. Compaction
• Compaction is the process of compressing the layout from all directions to minimize the chip area. In the
verification process, the layout is checked for its correctness.
• By making the chip smaller, wire lengths are reduced, which in turn reduces the signal delay between
components of the circuit.

v. Extraction and Verification

The verification step includes:

▪ Design Rule Checking (DRC): A process which verifies that all geometric patterns meet the design rules
imposed by the fabrication process.
▪ Circuit Extraction: Generates a circuit from the layout to compare with the original netlist.
▪ Performance verification: Extracts geometric information to compute resistance, capacitance, and delay.
▪ Reliability Verification: It ensures that layout will not fail due to electro-migration, self-heat and other effects.
New Trends in Physical Design Cycle

➢ As fabrication technology improves and process enters the deep sub-micron range, it is clear that interconnect
delay is not scaling at the same rate as the gate delay.
➢ In order to reduce interconnect delay several methods can be employed.

Chip level signal planning:

▪ At the chip level, routing of major signals and buses must be planned from early design stages, so that
interconnect distances can be minimized.
▪ The goal is to minimize interconnect distances to improve performance and reduce delays.
▪ Key signals (such as clock signals, data buses, and control lines) must be carefully planned to ensure efficient
communication within the chip.
▪ In addition, these global signals must be routed in the top metal layers, which have low delay per unit length.
Considerations in Signal Planning:

• Global Signals: These are critical signals that span large portions of the chip. Examples include clock signals
and reset lines.
• Routing Layers: Global signals are often routed in the top metal layers, which have lower delay per unit
length.
• Minimizing Distance: By planning the routing early, designers can minimize the distance these signals need to
travel, reducing overall signal propagation delays.
Over-the-Cell (OTC) Routing:
OTC routing is a term used to describe routing over blocks and active areas.

• Over-the-cell routing involves determining the precise paths for interconnecting standard cells, macros, and I/O pins
within the layout.

• It ensures that electrical connections (wires) are efficiently created based on the logical connections present in the
netlist.

• By routing certain blocks over the cells, the number of blocks that need to be routed within the channel is reduced.

• This reduction in the number of tracks in the channel leads to a decrease in chip area. The OTC routing approach
essentially makes routing a three dimensional problem.

• Another effect of the OTC routing approach is that the pins are not brought to the block boundaries for connections to
other blocks. Instead, pins are brought to the top of the block as a sea-of-pins. Thus, concept technically called the
Arbitrary Terminal Model (ATM).
Fig.10: New physical design Cycle.
Design Styles
The design styles can be broadly classified as:
i. Full custom layout
ii. Standard (Semi-custom) layout
On a large chip, each block may use a different layout design style.

i. Full custom Layout

• It requires all components to be designed and verified right from the transistor level.
• This design methodology can be used for mass production and to optimize speed and power. The full custom design
increases the performance of the chip and reduces the area.
• In a full-custom layout, different blocks of a circuit can be placed at any location on a silicon wafer as long as all the
blocks are non-overlapping.
• A preferred style for mass produced chips, since the time required to produce a highly optimized layout can be
justified.
Advantages

• Precise control over transistor placement.

• High performance due to fine-tuning.
• Efficient use of chip area.

Disadvantages

• Time-consuming and requires expertise.

• Expensive development costs.
Fig.11: Full-custom design layout.
ii. Standard layout

• This design methodology is used where there is less time for design and fewer quantities.

• Here, most of the modules are predesigned and pretested. We can add and placed the pre-design module on
some specific place on the silicon wafer.

• This will reduce the design time but it is not optimized and cost-efficient for mass production.

• It has less production time.

• To design an Application Specific Integrated Circuit (ASIC), a semi-custom layout style is usually
preferred.
Advantages:

• Faster development compared to full custom.

• Some customization while maintaining efficiency.
• Suitable for moderate production volumes.

Disadvantage

• Larger surface area.

• Low efficiency.
• larger

Fig.13 : Standard layout structure.

Fig.12 : Standard cell/ module library.

Comparison between Full Custom and Semi-Custom Design

Full Custom Design Standard Design

Complete design, implementation, Use pre-design and pre-tested cell module
placement is done from transistor level for designing
High cost Low cost
More design time required Less design time required
High Circuit Performance Low Circuit performance
Less dependency on the existing More dependency on the existing
technology technology
Can be used for mass production Cannot be used for mass production
Complex circuit layout Simplified circuit layout
Very High Speed Less Speed compared to Full custom
Design
Microprocessor Digital Logics, ASIC
Gate Array

• It involves using a prefabricated chip with components (such as NAND gates, flip-flops, etc.) that
are later interconnected into logic devices according to custom order by adding metal interconnect
layers in the factory.
• Unlike standard cell design, all the cells in gate array are identical.
• These cells are separated by both vertical and horizontal spaces called vertical and horizontal
channels.
• The name ‘gate array’ signifies the fact that each cell may simply be a gate, such as a three input
NAND/NOR gate, digital circuits, mixed-signal designs.
• The gate array wafer is taken into a fabrication facility and routing layers are fabricated on top of
the wafer.
Fig. 14: A conceptual uncommitted gate array. Fig. 15: A conceptual gate array.
Advantage of Gate Array design

• Reduce design time.

• Routability problem conceptually become simpler.
• Less chances of errors.
• Reduced production costs.
• Decreased time for production.

Disadvantages of Gate array design

• Very Limited flexibility.

• Need moderately high area.

Field Programmable Gate Arrays

▪ The Field Programmable Gate Array (FPGA) is a new approach to ASIC design.
▪ An FPGA chip has thousands of logic gates which are to be connected to implement any logic
function.
▪ In FPGAs, cells and interconnect are prefabricated.
▪ A concept can be quickly implemented in the
hardware and checked if it is worth implementing in a large
volume.

▪ The user simply ‘programs’ the interconnect.

▪ FPGA designs provide large scale integration and user
programmability.
Fig.16 : Field programmable Gate Arrays.
It has the following three main components:
▪ I/O block
▪ Array of configurable logic blocks (CLBs)
▪ Programmable Routing interconnects

I/O block

▪ I/O blocks provide a programmable, bidirectional or unidirectional interface between the FPGA
and external devices or pins.
▪ They allow data to flow in and out of the FPGA, enabling communication with other components.
▪ Distribute clock signals to various parts of the FPGA.
▪ Converts external signals (e.g., from sensors or switches) into internal logic levels and Converts
internal logic levels to drive external pins (e.g., LEDs, displays).
Configurable logic blocks (CLB)

▪ CLBs are the fundamental building blocks of an FPGA used to implements different Logic function.
▪ A logic block is simply a memory block which can be programmed to remember the logic table of a
function.
Programmable Routing interconnects
▪ Programmable routing interconnects refer to the configurable pathways that allow signals to flow
between different components (such as logic cells, memory blocks, and I/O pins) on an integrated
circuit.
▪ FPGA allow the user to re-program the interconnect, as many
times as needed.
▪ These interconnects can be programmed to route
signals in specific paths, enabling flexible connections
within the chip. Fig.17 : Field Programmable Gate Arrays.
Advantages of FPGA

▪ Reprogrammable
▪ Reusability
▪ Faster time to market
▪ Low cost

Disadvantages of FPGA

▪ Volatile
▪ Less efficiency
▪ Limited size options
▪ Not good for high volume applications
Sea of Gates

▪ The sea-of-gates design style is based on the use of a prefabricated array of transistors.

▪ Allows a designer to fabricate complex circuits, such as RAMs..

▪ Due to the use to transistors it has a much higher package density of logic implemented on the
chip.

▪ In the absence of routing channels, interconnects have to be completed either by routing through gates,
or by adding more metal or polysilicon interconnection layers.

▪ Routing using metal layer reduces the gate utilization; polysilicon interconnect routing increases the
mask count and increases fabrication time and cost.
Comparison of Different Design Styles

VLSI Style
Full-custom Standard cell Gate array FPGA
Cell size variable Fixed/uneven fixed fixed
height
Cell type variable variable fixed programmable
Cell placement variable in row fixed fixed
Interconnection variable variable variable programmable
s
Design cost high medium medium low
Area compact Compact to moderate large
moderate
Performance high high to moderate low
moderate
Fabricate All layers All layers Routing layers No layers
only